diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml index 78118e07816..dc6ab3e2965 100644 --- a/.github/workflows/nightly_test.yml +++ b/.github/workflows/nightly_test.yml @@ -65,9 +65,8 @@ jobs: - {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"} - {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} - {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"} - - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} - {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""} - - {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} + - {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""} env: DEBIAN_FRONTEND: "noninteractive" diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 0f0dbf3231b..1785cfb2b3c 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -97,7 +97,7 @@ jobs: run: ./dev/${{ matrix.script }} - UniTests: + UnitTests: name: 'U: C++ Unit Tests' runs-on: ubuntu-24.04 steps: @@ -366,6 +366,39 @@ jobs: ./.github/scripts/build.sh ./run_reg_test.py parmys_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }} + SystemVerilog: + name: 'System Verilog Regression' + runs-on: ubuntu-24.04 + steps: + + - uses: actions/setup-python@v5 + with: + python-version: 3.12.3 + + # NOTE: This is using recursive on purpose. In order to use the System + # Verilog feature, need submodules inside of a submodule. + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + + - name: Get number of CPU cores + uses: SimenB/github-actions-cpu-cores@v2 + id: cpu-cores + + - name: Install dependencies + run: ./.github/scripts/install_dependencies.sh + + - uses: hendrikmuhs/ccache-action@v1.2 + + - name: Test + env: + CMAKE_PARAMS: '-DSYNLIG_SYSTEMVERILOG=ON' + NUM_PROC: ${{ steps.cpu-cores.outputs.count }} + run: | + export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + ./.github/scripts/build.sh + ./run_reg_test.py vtr_reg_system_verilog -show_failures -j${{ steps.cpu-cores.outputs.count}} + ODINII: name: 'ODIN-II Basic Test' @@ -508,11 +541,12 @@ jobs: needs: - Build - Format - - UniTests + - UnitTests - Warnings - Regression - Sanitized - Parmys + - SystemVerilog - ODINII - VQM2BLIF - Compatibility diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index f70f150fbe2..3453f95bade 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -39,7 +39,7 @@ endif () if (${WITH_PARMYS}) if (${SYNLIG_SYSTEMVERILOG}) - + set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog) set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build) set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins) @@ -64,6 +64,7 @@ if (${WITH_PARMYS}) "-DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}" "-DCMAKE_POSITION_INDEPENDENT_CODE:BOOL=ON" "-DCMAKE_WARN_DEPRECATED:BOOL=OFF" + # redirect logs to a logfile LOG_BUILD ON @@ -76,54 +77,54 @@ if (${WITH_PARMYS}) DEPENDS yosys ) - # Synlig integration (manages Surelog and UHDM internally) - - # Synlig integration (manages Surelog and UHDM internally) - set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig) - - # Clone Synlig repository and ensure submodules are synced before building + set(SYNLIG_PREFIX_DIR "${CMAKE_CURRENT_SOURCE_DIR}/synlig") + set(SYNLIG_BINARY_DIR "${SYNLIG_PREFIX_DIR}/build") + set(SYNLIG_SOURCE_DIR "${SYNLIG_PREFIX_DIR}/src/synlig") + set(SYNLIG_INSTALL_DIR "${SYNLIG_BINARY_DIR}/install") # Ensure proper install + + # Debug paths to ensure correctness + message("🔍 DEBUG: CMAKE_CURRENT_SOURCE_DIR = ${CMAKE_CURRENT_SOURCE_DIR}") + message("🔍 DEBUG: SYNLIG_PREFIX_DIR = ${SYNLIG_PREFIX_DIR}") + message("🔍 DEBUG: SYNLIG_SOURCE_DIR = ${SYNLIG_SOURCE_DIR}") + message("🔍 DEBUG: SYNLIG_BINARY_DIR = ${SYNLIG_BINARY_DIR}") + message("🔍 DEBUG: SYNLIG_INSTALL_DIR = ${SYNLIG_INSTALL_DIR}") + ExternalProject_Add(synlig - PREFIX "synlig" - + PREFIX ${SYNLIG_PREFIX_DIR} + # Clone the Synlig repository GIT_REPOSITORY https://github.com/chipsalliance/synlig.git GIT_TAG main GIT_PROGRESS TRUE GIT_SHALLOW TRUE - - # Set source and build directories + + # Corrected install directory SOURCE_DIR "${SYNLIG_SOURCE_DIR}" + BINARY_DIR "${SYNLIG_BINARY_DIR}" BUILD_IN_SOURCE FALSE - INSTALL_DIR " " - - # Sync submodules after cloning - - - UPDATE_COMMAND git submodule update --init --recursive third_party/surelog - WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} - - BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" - + + # Ensure submodules are synced (CI sometimes skips this) + UPDATE_COMMAND git submodule update --init --recursive + + # Build and install in one command + BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${SYNLIG_BINARY_DIR} -j4 + # Pass necessary paths and set environment variables CMAKE_CACHE_ARGS "-DCMAKE_BUILD_TYPE:STRING=Release" - "-DSURELOG_PATH=${CMAKE_BINARY_DIR}/surelog" - "-DYOSYS_PATH=${CMAKE_BINARY_DIR}/yosys" - "-DUHDM_INSTALL_DIR=${CMAKE_BINARY_DIR}" - "-DBUILD_DIR=${CMAKE_BINARY_DIR}/synlig-build" - "-DEXPORT_PATH=${CMAKE_BINARY_DIR}/synlig_install/usr/local/bin:$ENV{PATH}" + "-DCMAKE_INSTALL_PREFIX:PATH=${SYNLIG_BINARY_DIR}" + "-DBUILD_DIR=${SYNLIG_BINARY_DIR}" LOG_BUILD ON LOG_UPDATE ON LOG_INSTALL ON LOG_CONFIGURE OFF LOG_OUTPUT_ON_FAILURE ON + + # Ensure dependencies like Yosys and Surelog are built first + DEPENDS yosys + ) - # Ensure dependencies like Yosys are built first - DEPENDS yosys # Ensure submodule sync runs before synlig build - ) endif () endif () @@ -175,4 +176,4 @@ if (VPR_USE_SERVER) $ $ ) -endif() \ No newline at end of file +endif() diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index 5f0888c328f..9226ae1ab3d 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -23,8 +23,9 @@ yosys_script_path = yosys_tcl_path / "synthesis.tcl" # Synlig paths -synlig_path = root_path/"build"/"bin"/"synlig_install" -synlig_exe_path = synlig_path / "usr"/"local"/"bin"/"synlig" +synlig_path = root_path/"libs"/"EXTERNAL"/"synlig" +synlig_exe_path= synlig_path/"build"/"usr"/"local"/"bin"/"synlig" + # PARMYS paths parmys_path = root_path / "parmys" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt index 0ba1c65ca48..feb6b31513b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml button_controller.sv common 1.80 vpr 66.81 MiB -1 -1 0.76 56284 3 0.06 -1 -1 36748 -1 -1 13 3 0 0 success 33883b0-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-21T17:24:52 gh-actions-runner-vtr-auto-spawned151 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68412 3 12 252 216 1 125 28 7 7 49 clb auto 28.2 MiB 0.09 426 1582 344 1156 82 66.8 MiB 0.02 0.00 2.14586 -130.671 -2.14586 2.14586 0.05 0.000235558 0.000213568 0.0116245 0.0106724 40 699 17 1.07788e+06 700622 95414.1 1947.23 0.33 0.0977526 0.0831919 3948 17640 -1 608 14 464 649 15787 5088 2.43268 2.43268 -139.129 -2.43268 0 0 120731. 2463.90 0.02 0.02 0.01 -1 -1 0.02 0.0126647 0.0116072 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml flattened_button_controller.sv common 1.43 vpr 65.39 MiB -1 -1 0.73 56392 2 0.06 -1 -1 35576 -1 -1 1 7 0 0 success v8.0.0-11956-g418d7823e-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-02-08T12:23:30 amir-virtual-machine /home/amir/projects/vtr-verilog-to-routing/vtr_flow/scripts 66956 7 2 17 19 1 9 10 3 3 9 -1 auto 26.9 MiB 0.01 24 30 18 9 3 65.4 MiB 0.00 0.00 0.88747 -3.57662 -0.88747 0.88747 0.00 1.6247e-05 1.1337e-05 0.00023508 0.000196903 -1 -1 -1 -1 26 23 1 53894 53894 6579.40 731.044 0.02 0.00121222 0.00101166 415 887 -1 13 5 16 16 195 127 0.906526 0.906526 -4.03829 -0.906526 0 0 7883.24 875.916 0.00 0.00 0.00 -1 -1 0.00 0.000636943 0.00056915 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt index b98b60543a3..a0adb2d7d7b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml pulse_led.v common 0.78 vpr 65.65 MiB -1 -1 0.33 48464 2 0.02 -1 -1 35352 -1 -1 3 9 0 0 success 33883b0-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-06-21T17:24:52 gh-actions-runner-vtr-auto-spawned151 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67224 9 3 145 109 1 14 15 5 5 25 clb auto 27.3 MiB 0.02 26 177 38 133 6 65.6 MiB 0.00 0.00 1.225 -51.7876 -1.225 1.225 0.01 0.000107722 9.7932e-05 0.00192273 0.00179338 18 44 3 323364 161682 19301.3 772.054 0.02 0.00557779 0.00521101 1386 3298 -1 52 2 13 13 323 175 1.225 1.225 -52.7217 -1.225 0 0 24611.1 984.442 0.00 0.00 0.00 -1 -1 0.00 0.00303037 0.00287872 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml flattened_pulse_width_led.sv common 0.99 vpr 65.24 MiB -1 -1 0.37 46172 2 0.05 -1 -1 35488 -1 -1 1 7 0 0 success v8.0.0-11956-g418d7823e-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-02-08T12:23:30 amir-virtual-machine /home/amir/projects/vtr-verilog-to-routing/vtr_flow/scripts 66808 7 2 17 19 1 9 10 3 3 9 -1 auto 26.7 MiB 0.01 24 30 18 9 3 65.2 MiB 0.00 0.00 0.88747 -3.57662 -0.88747 0.88747 0.00 2.6176e-05 1.9756e-05 0.000231951 0.000196419 -1 -1 -1 -1 26 23 1 53894 53894 6579.40 731.044 0.02 0.00114638 0.000956391 415 887 -1 13 5 16 16 195 127 0.906526 0.906526 -4.03829 -0.906526 0 0 7883.24 875.916 0.00 0.00 0.00 -1 -1 0.00 0.000429714 0.00039152 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt index 36401994979..506b025b0b1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml clock.sv common 1.54 vpr 65.80 MiB -1 -1 0.69 49624 4 0.07 -1 -1 35560 -1 -1 10 3 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:44 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67380 3 12 261 222 1 119 25 6 6 36 clb auto 27.3 MiB 0.13 425 65.8 MiB 0.01 0.00 2.39956 -129.682 -2.39956 2.39956 0.03 9.565e-05 7.3348e-05 0.00427643 0.00376691 30 695 17 646728 538940 51438.4 1428.85 0.08 0.0252184 0.021744 2512 8913 -1 547 11 355 516 15625 5833 0 0 15625 5833 516 418 0 0 882 752 0 0 986 882 0 0 552 459 0 0 6460 1703 0 0 6229 1619 0 0 516 0 0 161 222 192 1871 0 0 2.70547 2.70547 -144.28 -2.70547 0 0 63526.2 1764.62 0.01 0.01 0.01 -1 -1 0.01 0.00924855 0.0087123 +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml flattened_timer.sv common 1.35 vpr 65.39 MiB -1 -1 0.61 50060 2 0.06 -1 -1 35484 -1 -1 1 7 0 0 success v8.0.0-11956-g418d7823e-dirty Release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-52-generic x86_64 2025-02-08T12:23:30 amir-virtual-machine /home/amir/projects/vtr-verilog-to-routing/vtr_flow/scripts 66956 7 2 17 19 1 9 10 3 3 9 -1 auto 26.9 MiB 0.01 24 30 18 9 3 65.4 MiB 0.00 0.00 0.88747 -3.57662 -0.88747 0.88747 0.00 1.9591e-05 1.3949e-05 0.000225148 0.000195545 -1 -1 -1 -1 26 23 1 53894 53894 6579.40 731.044 0.01 0.00104416 0.000877439 415 887 -1 13 5 16 16 195 127 0.906526 0.906526 -4.03829 -0.906526 0 0 7883.24 875.916 0.00 0.00 0.00 -1 -1 0.00 0.000594084 0.000525136