diff --git a/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt b/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt index cd21e4e4f48..70ab6c01dbf 100644 --- a/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt +++ b/vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt @@ -12,4 +12,5 @@ %include "common/vpr.common.txt" %include "timing/vpr.pack.txt" %include "timing/vpr.place.txt" +%include "timing/vpr.ap.txt" %include "timing/vpr.route_fixed_chan_width.txt" diff --git a/vtr_flow/scripts/python_libs/vtr/task.py b/vtr_flow/scripts/python_libs/vtr/task.py index c382501e6bd..fd6fd7640c4 100644 --- a/vtr_flow/scripts/python_libs/vtr/task.py +++ b/vtr_flow/scripts/python_libs/vtr/task.py @@ -55,6 +55,7 @@ def __init__( pad_file=None, additional_files=None, additional_files_list_add=None, + circuit_constraint_list_add=None ): self.task_name = task_name self.config_dir = config_dir @@ -81,6 +82,9 @@ def __init__( self.pad_file = pad_file self.additional_files = additional_files self.additional_files_list_add = additional_files_list_add + self.circuit_constraints = parse_circuit_constraint_list(circuit_constraint_list_add, + self.circuits, + self.archs) # pylint: enable=too-few-public-methods @@ -225,7 +229,9 @@ def load_task_config(config_file) -> TaskConfig: # Interpret the file key_values = {} for line in values: - key, value = line.split("=") + # Split the key and value using only the first equal sign. This allows + # the value to have an equal sign. + key, value = line.split("=", 1) # Trim whitespace key = key.strip() @@ -300,6 +306,73 @@ def check_include_fields(config_file, key_values): ) ) +def parse_circuit_constraint_list( + circuit_constraint_list, circuits_list, arch_list +) -> dict: + """ + Parse the circuit constraints passed in via the config file. + Circuit constraints are expected to have the following syntax: + (, =) + This function generates a dictionary which can be accessed: + circuit_constraints[circuit][constr_key] + If this dictionary returns "None", then the circuit is unconstrained for + that key. + """ + + # Constraint keys that can be specified. + circuit_constraint_keys = set( + [ + "arch", + "device", + "constraints", + ] + ) + + # Initialize the dictionary to be unconstrained for all circuits and keys. + res_circuit_constraints = { + circuit: {constraint_key: None for constraint_key in circuit_constraint_keys} + for circuit in circuits_list + } + + # If there were no circuit constraints passed by the user, return dictionary + # of Nones. + if circuit_constraint_list is None: + return res_circuit_constraints + + # Parse the circuit constraint list + for circuit_constraint in circuit_constraint_list: + # Remove the round brackets. + if circuit_constraint[0] != '(' or circuit_constraint[-1] != ')': + raise VtrError(f"Circuit constraint syntax error: \"{circuit_constraint}\"") + circuit_constraint = circuit_constraint[1:-1] + # Split the circuit and the constraint + split_constraint_line = circuit_constraint.split(',') + if len(split_constraint_line) != 2: + raise VtrError(f"Circuit constraint has too many arguments: \"{circuit_constraint}\"") + circuit = split_constraint_line[0].strip() + constraint = split_constraint_line[1].strip() + # Check that the circuit actually exists. + if circuit not in circuits_list: + raise VtrError(f"Cannot constrain circuit \"{circuit}\", circuit has not been added") + # Parse the constraint + split_constraint = constraint.split("=") + if len(split_constraint) != 2: + raise VtrError(f"Circuit constraint syntax error: \"{circuit_constraint}\"") + constr_key = split_constraint[0].strip() + constr_val = split_constraint[1].strip() + # Check that the constr_key is valid. + if constr_key not in circuit_constraint_keys: + raise VtrError(f"Invalid constraint \"{constr_key}\" used on circuit \"{circuit}\"") + # In the case of arch constraints, make sure this arch exists. + if constr_key == "arch" and constr_val not in arch_list: + raise VtrError(f"Cannot constrain arch \"{constr_key}\", arch has not been added") + # Make sure this circuit is not already constrained with this constr_arg + if res_circuit_constraints[circuit][constr_key] is not None: + raise VtrError(f"Circuit \"{circuit}\" cannot be constrained more than once") + # Add the constraint for this circuit + res_circuit_constraints[circuit][constr_key] = constr_val + + return res_circuit_constraints def shorten_task_names(configs, common_task_prefix): """ @@ -496,6 +569,11 @@ def create_jobs(args, configs, after_run=False) -> List[Job]: ] for arch, circuit, noc_traffic in combinations: + # If the circuit is constrained to only run on a specific arch, and + # this arch is not that arch, skip this combination. + circuit_arch_constraint = config.circuit_constraints[circuit]["arch"] + if circuit_arch_constraint is not None and circuit_arch_constraint != arch: + continue golden_results = load_parse_results( str(PurePath(config.config_dir).joinpath("golden_results.txt")) ) @@ -613,6 +691,10 @@ def create_job( cmd += ["-expect_fail", expected_vpr_status] current_parse_cmd = parse_cmd.copy() + # Apply the command-line circuit constraints provided by the circuit + # constraint list in the config file. + apply_cmd_line_circuit_constraints(cmd, circuit, config) + if config.parse_file: current_parse_cmd += [ "arch={}".format(arch), @@ -697,6 +779,19 @@ def ret_expected_vpr_status(arch, circuit, golden_results, script_params=None): return golden_metrics["vpr_status"] +def apply_cmd_line_circuit_constraints(cmd, circuit, config): + """ + Apply the circuit constraints to the command line. If the circuit is not + constrained for any key, this method will not do anything. + """ + # Check if this circuit is constrained to a specific device. + constrained_device = config.circuit_constraints[circuit]["device"] + if constrained_device is not None: + cmd += ["--device", constrained_device] + # Check if the circuit has constrained atom locations. + circuit_vpr_constraints = config.circuit_constraints[circuit]["constraints"] + if circuit_vpr_constraints is not None: + cmd += ["--read_vpr_constraints", circuit_vpr_constraints] def resolve_vtr_source_file(config, filename, base_dir=""): """ diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics/config/config.txt deleted file mode 100644 index ccc52ba6cc7..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing/fixed_size - -# Add circuits to list to sweep -circuit_list_add=ch_intrinsics.v - -# Add architectures to list to sweep -arch_list_add=fixed_k6_frac_N8_22nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements_ap.txt - -# Script parameters -script_params_common=-track_memory_usage --analytical_place --route --device "unnamed_device" --read_vpr_constraints ../../../../ch_intrinsics_fixed_io.xml - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/config.txt new file mode 100644 index 00000000000..14c21b6851d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/config.txt @@ -0,0 +1,52 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing/fixed_size + +# TODO: Add a path to the atom constraints (different from the place constraints) +# "atom_const_dir" +# TODO: Add a directory next to the config to hold the constraints. + +# Add circuits to list to sweep +circuit_list_add=single_wire.v +circuit_list_add=single_ff.v +circuit_list_add=ch_intrinsics.v +circuit_list_add=diffeq1.v + +# Add architectures to list to sweep +arch_list_add=fixed_k6_frac_N8_22nm.xml + +# Constrain the circuits to a fixed device with fixed IO constraints. +circuit_constraint_list_add=(single_wire.v, arch=fixed_k6_frac_N8_22nm.xml) +circuit_constraint_list_add=(single_wire.v, device=unnamed_device) +circuit_constraint_list_add=(single_wire.v, constraints=../../../../constraints/single_wire_fixed_io.xml) + +circuit_constraint_list_add=(single_ff.v, arch=fixed_k6_frac_N8_22nm.xml) +circuit_constraint_list_add=(single_ff.v, device=unnamed_device) +circuit_constraint_list_add=(single_ff.v, constraints=../../../../constraints/single_ff_fixed_io.xml) + +circuit_constraint_list_add=(ch_intrinsics.v, arch=fixed_k6_frac_N8_22nm.xml) +circuit_constraint_list_add=(ch_intrinsics.v, device=unnamed_device) +circuit_constraint_list_add=(ch_intrinsics.v, constraints=../../../../constraints/ch_intrinsics_fixed_io.xml) + +circuit_constraint_list_add=(diffeq1.v, arch=fixed_k6_frac_N8_22nm.xml) +circuit_constraint_list_add=(diffeq1.v, device=unnamed_device) +circuit_constraint_list_add=(diffeq1.v, constraints=../../../../constraints/diffeq1_fixed_io.xml) + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap.txt + +# Script parameters +script_params_common=-track_memory_usage --analytical_place --route + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt new file mode 100644 index 00000000000..2b004ff8d4a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt @@ -0,0 +1,5 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_k6_frac_N8_22nm.xml single_wire.v common 1.86 vpr 70.71 MiB -1 -1 0.14 16260 1 0.02 -1 -1 29996 -1 -1 0 1 0 0 success v8.0.0-11569-g4abbff8da release VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-17T15:58:41 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72404 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 70.7 MiB 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70.7 MiB 0.09 70.7 MiB 0.09 8 14 1 6.79088e+06 0 166176. 575.005 0.37 0.00145994 0.0013718 20206 45088 -1 19 1 1 1 194 45 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.11 0.00 0.08 -1 -1 0.11 0.00115987 0.00113118 +fixed_k6_frac_N8_22nm.xml single_ff.v common 2.32 vpr 70.91 MiB -1 -1 0.12 16324 1 0.02 -1 -1 29972 -1 -1 1 2 0 0 success v8.0.0-11569-g4abbff8da release VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-17T15:58:41 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72608 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 70.9 MiB 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70.9 MiB 0.09 70.9 MiB 0.09 20 32 1 6.79088e+06 13472 414966. 1435.87 0.65 0.0013976 0.00133449 22510 95286 -1 40 1 2 2 394 99 1.06752 1.06752 -2.06486 -1.06752 0 0 503264. 1741.40 0.20 0.00 0.16 -1 -1 0.20 0.0013263 0.00128456 +fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 6.78 vpr 71.84 MiB -1 -1 0.48 18336 3 0.11 -1 -1 33188 -1 -1 34 99 1 0 success v8.0.0-11569-g4abbff8da release VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-17T15:58:41 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 73568 99 130 240 229 1 238 264 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 71.8 MiB 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 71.8 MiB 0.27 71.8 MiB 0.27 34 2792 13 6.79088e+06 1.00605e+06 618332. 2139.56 3.94 0.383735 0.349796 25102 150614 -1 2694 15 616 987 97889 23015 2.47058 2.47058 -150.612 -2.47058 0 0 787024. 2723.27 0.27 0.11 0.23 -1 -1 0.27 0.0610859 0.0560772 +fixed_k6_frac_N8_22nm.xml diffeq1.v common 24.21 vpr 74.00 MiB -1 -1 0.75 22884 15 0.37 -1 -1 34280 -1 -1 55 162 0 5 success v8.0.0-11569-g4abbff8da release VTR_ASSERT_LEVEL=3 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-17T15:58:41 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 75780 162 96 817 258 1 775 318 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 74.0 MiB 0.68 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.0 MiB 0.68 74.0 MiB 0.66 72 17155 27 6.79088e+06 2.72096e+06 1.19926e+06 4149.71 18.39 3.30386 3.12634 32302 307853 -1 15386 19 3657 8928 1435723 311083 21.8615 21.8615 -1810.62 -21.8615 0 0 1.50317e+06 5201.28 0.50 0.73 0.55 -1 -1 0.50 0.298787 0.283438 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics/ch_intrinsics_fixed_io.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/ch_intrinsics_fixed_io.xml similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics/ch_intrinsics_fixed_io.xml rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/ch_intrinsics_fixed_io.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/diffeq1/diffeq1_fixed_io.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/diffeq1_fixed_io.xml similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/diffeq1/diffeq1_fixed_io.xml rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/diffeq1_fixed_io.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/single_ff_fixed_io.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/single_ff_fixed_io.xml similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/single_ff_fixed_io.xml rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/single_ff_fixed_io.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/single_wire_fixed_io.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/single_wire_fixed_io.xml similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/single_wire_fixed_io.xml rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/constraints/single_wire_fixed_io.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/diffeq1/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/diffeq1/config/config.txt deleted file mode 100644 index 7e7eaa7fd2a..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/diffeq1/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing/fixed_size - -# Add circuits to list to sweep -circuit_list_add=diffeq1.v - -# Add architectures to list to sweep -arch_list_add=fixed_k6_frac_N8_22nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements_ap.txt - -# Script parameters -script_params_common=-track_memory_usage --analytical_place --route --device "unnamed_device" --read_vpr_constraints ../../../../diffeq1_fixed_io.xml - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/config.txt deleted file mode 100644 index 65ff8dbdc1e..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing/fixed_size - -# Add circuits to list to sweep -circuit_list_add=single_ff.v - -# Add architectures to list to sweep -arch_list_add=fixed_k6_frac_N8_22nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements_ap.txt - -# Script parameters -script_params_common=-track_memory_usage --analytical_place --route --device "unnamed_device" --read_vpr_constraints ../../../../single_ff_fixed_io.xml - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/golden_results.txt deleted file mode 100644 index a3367f68e35..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_ff/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -fixed_k6_frac_N8_22nm.xml single_ff.v common 2.76 vpr 70.63 MiB -1 -1 0.13 16160 1 0.23 -1 -1 29588 -1 -1 1 2 0 0 success v8.0.0-11429-g78275509a-dirty release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-02T13:22:58 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72324 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 70.6 MiB 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 70.6 MiB 0.09 70.6 MiB 0.09 20 32 1 6.79088e+06 13472 414966. 1435.87 0.60 0.00144364 0.00136058 22510 95286 -1 40 1 2 2 393 99 1.06752 1.06752 -2.06486 -1.06752 0 0 503264. 1741.40 0.18 0.00 0.13 -1 -1 0.18 0.00126359 0.00121387 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/config.txt deleted file mode 100644 index 6877712cbba..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/config.txt +++ /dev/null @@ -1,28 +0,0 @@ -############################################## -# Configuration file for running experiments -############################################## - -# Path to directory of circuits to use -circuits_dir=benchmarks/verilog - -# Path to directory of architectures to use -archs_dir=arch/timing/fixed_size - -# Add circuits to list to sweep -circuit_list_add=single_wire.v - -# Add architectures to list to sweep -arch_list_add=fixed_k6_frac_N8_22nm.xml - -# Parse info and how to parse -parse_file=vpr_standard.txt - -# How to parse QoR info -qor_parse_file=qor_standard.txt - -# Pass requirements -pass_requirements_file=pass_requirements_ap.txt - -# Script parameters -script_params_common=-track_memory_usage --analytical_place --route --device "unnamed_device" --read_vpr_constraints ../../../../single_wire_fixed_io.xml - diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/golden_results.txt deleted file mode 100644 index c59c3914961..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/single_wire/config/golden_results.txt +++ /dev/null @@ -1,2 +0,0 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -fixed_k6_frac_N8_22nm.xml single_wire.v common 1.76 vpr 71.40 MiB -1 -1 0.12 16768 1 0.02 -1 -1 30048 -1 -1 0 1 0 0 success v8.0.0-11425-g2f84f81f9 release VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-27T10:26:58 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing 73116 1 1 1 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 14 1 6.79088e+06 0 166176. 575.005 0.34 0.00123577 0.00119358 20206 45088 -1 19 1 1 1 194 45 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.10 0.00 0.07 -1 -1 0.10 0.00143806 0.00140336 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/task_list.txt deleted file mode 100644 index d6c7b6615b4..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/task_list.txt +++ /dev/null @@ -1,5 +0,0 @@ -# This extra task list is for running just the basic_ap tasks in isolation. -regression_tests/vtr_reg_strong/basic_ap/single_wire -regression_tests/vtr_reg_strong/basic_ap/single_ff -regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics -regression_tests/vtr_reg_strong/basic_ap/diffeq1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index cd5f997ff8c..ba1d6d95268 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -1,7 +1,4 @@ -regression_tests/vtr_reg_strong/basic_ap/single_wire -regression_tests/vtr_reg_strong/basic_ap/single_ff -regression_tests/vtr_reg_strong/basic_ap/ch_intrinsics -regression_tests/vtr_reg_strong/basic_ap/diffeq1 +regression_tests/vtr_reg_strong/basic_ap regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only regression_tests/vtr_reg_strong/strong_analytic_placer