From b31accc2176e1c85509a7688c455cf6feb396388 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Tue, 2 May 2023 15:45:40 -0600 Subject: [PATCH 01/10] added most up to date arch file --- .../xilinx/simple-7series_correctedSB.xml | 1120 +++++++++++++++++ 1 file changed, 1120 insertions(+) create mode 100644 vtr_flow/arch/xilinx/simple-7series_correctedSB.xml diff --git a/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml b/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml new file mode 100644 index 00000000000..3082ff4e6e1 --- /dev/null +++ b/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml @@ -0,0 +1,1120 @@ + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + 1 0 1 + 1 1 + + + + + 1 0 1 + 1 1 + + + + + 1 0 0 0 1 + 1 0 0 1 + + + + 1 0 0 0 1 + 1 0 0 1 + + + + + + + 1 1 1 0 1 + 1 1 0 1 + + + + + + + + 1 1 1 0 0 1 1 + 1 1 0 0 1 1 + + + + 1 0 0 0 0 0 1 + 1 0 0 0 0 1 + + + + + + 1 1 1 0 0 1 1 + 1 1 0 0 1 1 + + + + + + + 1 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 1 + + + + 1 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 1 + + + + + + + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + + + + + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 + + + + + + + + + 1 0 0 0 1 + 1 0 0 0 + + + + 1 0 0 0 1 + 1 0 0 0 + + + + 1 0 0 0 1 + 1 0 0 0 + + + + 1 0 0 0 1 + 1 0 0 0 + + + + + + 1 0 1 + 0 1 + + + + 1 0 1 + 0 1 + + + + 1 0 1 + 1 0 + + + + 1 0 1 + 1 0 + + + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1.5200000000000002e-10 + 1.5200000000000002e-10 + 1.5e-10 + 1.5e-10 + 1.18e-10 + + + 4.4e-11 + 4.4e-11 + 4.2000000000000004e-11 + 4.6e-11 + 4.8e-11 + + + + + + + + + + + + + + + + + + + + + + + 1.6200000000000002e-10 + 1.6200000000000002e-10 + 1.6e-10 + 1.6e-10 + 1.6e-10 + 1.28e-10 + + + 4.4e-11 + 4.4e-11 + 4.2000000000000004e-11 + 4.6e-11 + 4.5e-11 + 4.8e-11 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file From 6e708e36c38dc4371cb9657a8cb2d20fb99e2c9f Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 15 Jun 2023 17:41:31 -0600 Subject: [PATCH 02/10] Refactored routing. Changes fixed severl issues with multiple connections occuring on L shaped and stub wires. Updated arch has greatly improved min chanel width on larger designs (stereovision0 174->66 after changes). --- .../xilinx/simple-7series_correctedSB.xml | 817 +++++++----------- 1 file changed, 295 insertions(+), 522 deletions(-) diff --git a/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml b/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml index 3082ff4e6e1..ce48bffb905 100644 --- a/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml +++ b/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml @@ -29,7 +29,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -59,7 +59,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -74,7 +74,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -93,17 +93,20 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + + - - + + + + @@ -123,10 +126,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + @@ -144,236 +145,252 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + 1 1 1 - + 1 1 1 - - - 1 1 - 1 - - - - 1 1 - 1 - - - + 1 0 1 1 1 - + 1 0 1 1 1 - - - 1 0 0 0 1 - 1 0 0 1 - - + 1 0 0 0 1 1 0 0 1 - - - - 1 1 1 0 1 - 1 1 0 1 - - - - - - - 1 1 1 0 0 1 1 - 1 1 0 0 1 1 - - + 1 0 0 0 0 0 1 1 0 0 0 0 1 - - - - 1 1 1 0 0 1 1 - 1 1 0 0 1 1 - - - + 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 - + 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 - - - - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 - - - + + + + + + 1 0 0 0 1 1 0 0 0 - + 1 0 0 0 1 1 0 0 0 - + + 1 0 0 0 1 1 0 0 0 - + 1 0 0 0 1 1 0 0 0 - + 1 0 1 0 1 - + 1 0 1 0 1 - + + 1 0 1 1 0 - + 1 0 1 1 0 - + 1 1 1 - + 1 1 1 - + 1 1 1 - + 1 1 1 - + + + 1 1 + 1 + + 1 1 1 - + 1 1 1 - + 1 1 1 - + + + + + + + 1 1 1 - + + + + 1 0 0 0 0 1 1 + 1 0 0 0 1 1 + + + + + + 1 1 1 + 1 1 + + + + + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + 1 1 + 1 + + + + + + 1 0 1 + 1 1 + + + + 1 0 1 + 1 1 + + + + + 1 0 0 0 1 + 1 0 0 1 + + + + + + 1 0 1 + 1 1 + @@ -427,7 +444,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create perform the same logic functions. This is done for real arches such as coffe and stratix. --> - @@ -532,8 +550,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -574,7 +591,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - @@ -703,16 +673,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + - - + + @@ -723,391 +690,197 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - + + - - - - - - + - - - - - - + + + + + + + + - - + + + - - + + - - - + + + - + + - - - + + - - - - - - - - - - + + + + + - - - + + + - - + + - - - - + + + + + - - - + + - - - - - - - + - - - - - - - - + same direction. --> + + + + - - - - + + - - + - + - - + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + - + + - - + - + + + - + - - - - - - - + + - + - - - - - - + + - - - - - - - - - - - - - - - - - - - - + + + - From 45f95c900f4aaf26568df7d36753a5f797fde56e Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 16 May 2024 16:18:37 -0600 Subject: [PATCH 03/10] updated arch to current version --- .../arch/xilinx/7series_BRAM_DSP_cary.xml | 2456 +++++++++++++++++ .../xilinx/simple-7series_correctedSB.xml | 893 ------ 2 files changed, 2456 insertions(+), 893 deletions(-) create mode 100644 vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml delete mode 100644 vtr_flow/arch/xilinx/simple-7series_correctedSB.xml diff --git a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml new file mode 100644 index 00000000000..c361b3417f6 --- /dev/null +++ b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml @@ -0,0 +1,2456 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.CLK clb.I clb.O + clb.CLK clb.I clb.O clb.cout + clb.CLK clb.I clb.O clb.cin + clb.CLK clb.I clb.O + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DSP.clk DSP.A DSP.B DSP.P + DSP.clk DSP.A DSP.B DSP.P + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 + 1 + + + + + 1 1 1 + 1 1 + + + + + 1 1 1 + 1 1 + + + + + 1 1 0 1 1 + 1 1 1 1 + + + + + + + 1 1 0 0 0 1 1 + 1 1 0 0 1 1 + + + + + + + 1 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 1 + + + + 1 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 1 + + + + + + + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 + + + + + + + + + + + 1 0 0 0 1 + 1 0 0 0 + + + + 1 0 0 0 1 + 1 0 0 0 + + + + + 1 0 0 0 1 + 1 0 0 0 + + + + 1 0 0 0 1 + 1 0 0 0 + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml b/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml deleted file mode 100644 index ce48bffb905..00000000000 --- a/vtr_flow/arch/xilinx/simple-7series_correctedSB.xml +++ /dev/null @@ -1,893 +0,0 @@ - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - - 1 0 1 - 1 1 - - - - - 1 0 1 - 1 1 - - - - - 1 0 0 0 1 - 1 0 0 1 - - - - - - - 1 0 0 0 0 0 1 - 1 0 0 0 0 1 - - - - - - - 1 0 0 0 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 0 0 1 - - - - 1 0 0 0 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 - - - - - - - - - - - - 1 0 0 0 1 - 1 0 0 0 - - - - 1 0 0 0 1 - 1 0 0 0 - - - - - 1 0 0 0 1 - 1 0 0 0 - - - - 1 0 0 0 1 - 1 0 0 0 - - - - - - 1 0 1 - 0 1 - - - - 1 0 1 - 0 1 - - - - - 1 0 1 - 1 0 - - - - 1 0 1 - 1 0 - - - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - - - - - - - 1 1 - 1 - - - - - - 1 0 0 0 0 1 1 - 1 0 0 0 1 1 - - - - - - 1 1 1 - 1 1 - - - - - - - - 1 1 - 1 - - - - 1 1 - 1 - - - - - 1 1 - 1 - - - - - - 1 0 1 - 1 1 - - - - 1 0 1 - 1 1 - - - - - 1 0 0 0 1 - 1 0 0 1 - - - - - - 1 0 1 - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1.5200000000000002e-10 - 1.5200000000000002e-10 - 1.5e-10 - 1.5e-10 - 1.18e-10 - - - 4.4e-11 - 4.4e-11 - 4.2000000000000004e-11 - 4.6e-11 - 4.8e-11 - - - - - - - - - - - - - - - - - - - - - - - 1.6200000000000002e-10 - 1.6200000000000002e-10 - 1.6e-10 - 1.6e-10 - 1.6e-10 - 1.28e-10 - - - 4.4e-11 - 4.4e-11 - 4.2000000000000004e-11 - 4.6e-11 - 4.5e-11 - 4.8e-11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file From d15ac0aafa7583772460281f8dd4868443b1b04d Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 6 Jun 2024 09:27:06 -0600 Subject: [PATCH 04/10] fixed global to local interconnect --- .../arch/xilinx/7series_BRAM_DSP_cary.xml | 2858 ++++++++++++----- 1 file changed, 2057 insertions(+), 801 deletions(-) diff --git a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml index c361b3417f6..02bc7f72520 100644 --- a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml +++ b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml @@ -102,7 +102,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + io.outpad io.inpad io.clock io.outpad io.inpad io.clock @@ -115,12 +115,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - + - - + @@ -180,11 +182,12 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + - + - + - - - - - - - - + + + + + + + + + + + + + - - - - - @@ -270,9 +283,12 @@ and VTR's k6_N10_40nm.xml were pulled from to create DSP.clk DSP.A DSP.B DSP.P DSP.clk DSP.A DSP.B DSP.P + DSP.clk DSP.A DSP.B DSP.P + DSP.clk DSP.A DSP.B DSP.P + @@ -294,11 +310,19 @@ and VTR's k6_N10_40nm.xml were pulled from to create with 'clb'--> - + + + + + - - + + + @@ -325,7 +349,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create following muxes for unidirectional wires are pulled from k6_N10_40nm --> - @@ -337,78 +362,79 @@ and VTR's k6_N10_40nm.xml were pulled from to create are calculated by dividing each wire segments count in the horizontal/vertical direction by the total width/hight of the architecture --> - - - 1 1 - 1 + 1 0 1 + 1 1 - - 1 1 - 1 + 1 0 1 + 1 1 - - 1 1 1 - 1 1 + 1 0 0 1 + 1 0 1 - - 1 1 1 - 1 1 + 1 0 0 1 + 1 0 1 - - 1 1 0 1 1 - 1 1 1 1 + 1 0 0 0 0 1 + 1 0 0 0 1 - - 1 1 0 0 0 1 1 - 1 1 0 0 1 1 + 1 0 0 0 0 0 0 1 + 1 0 0 0 0 0 1 - - 1 0 0 0 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 0 1 - - 1 0 0 0 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 0 0 0 1 - - 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 @@ -422,7 +448,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create All diagonal wires are named as follows: 1) a number representing the type of segment as shown bellow 2) the length of the wire (len2,len1,len4) - 3) if the wire is an x or y component + 3) if the wire is an x or y component The following is a data1gram showing how each number correlates to each wire direction: @@ -436,7 +462,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create --> - + @@ -464,6 +491,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create + @@ -491,6 +520,12 @@ and VTR's k6_N10_40nm.xml were pulled from to create + @@ -516,6 +551,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create 1 + @@ -543,40 +580,57 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - 1 0 0 0 0 1 1 - 1 0 0 0 1 1 + 1 0 0 0 0 0 1 1 + 1 0 0 0 0 1 1 - - 1 1 1 - 1 1 + 1 0 1 1 + 1 1 1 - - 1 0 0 0 1 - 1 0 0 1 + 1 0 0 0 0 1 + 1 0 0 0 1 - - 1 0 1 - 1 1 + 1 0 0 1 + 1 0 1 + + + + + + 1 1 + 1 @@ -619,7 +673,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + - + @@ -668,17 +724,20 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + 1.5200000000000002e-10 1.5200000000000002e-10 1.5e-10 1.5e-10 1.18e-10 - + 4.4e-11 4.4e-11 4.2000000000000004e-11 @@ -687,10 +746,14 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - + + + + @@ -707,10 +770,12 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + 1.6200000000000002e-10 1.6200000000000002e-10 1.6e-10 @@ -718,7 +783,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create 1.6e-10 1.28e-10 - + 4.4e-11 4.4e-11 4.2000000000000004e-11 @@ -729,7 +795,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -752,8 +819,10 @@ and VTR's k6_N10_40nm.xml were pulled from to create out_port="adder.sumout" /> - - + + @@ -764,7 +833,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -787,8 +857,10 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + @@ -797,13 +869,17 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - - + - + @@ -864,7 +940,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - @@ -898,7 +975,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -979,7 +1057,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -1007,10 +1086,16 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + + + @@ -1027,108 +1112,131 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + - - + + + + + + + + + + + + - - - - - - - - + + - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -1140,772 +1248,1851 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + - - - - - + + + + - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - - - + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + - - - - - - + + - + + - - + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + - + + + + + + - - + - - - - - + - - - - - - - - - - + + + + + + - + + - - - - - - - - - - + + - - - - + + + + + + + - - - - - - - - - - - - - - + + - - - - - - + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + - + + + + + + - - + - - - - - + - - - - - - - + + + + + + + - - + + - + - - - - + + + - - - + + + - - + + - - - - + + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - + - - - - - + - - - - - - - - - - - - + + + + + + + - - - - + + - - - + - - + + + + + + + - - - - - - - - - - - - - - - - - - + + - - - - - - + + + + - - - - - - + + + + + + + + + + + + + + - - - - - + + + + + + - - + + + + + + - - - - - - + + + + + + + + - - - - + + - + - + + + + - - - - + + + - + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + + + + - - - + + + + + + - - - + + + + + + + + + + + - - + - - - - + + + + - + - - - - + - - - - - - + + + + - - - - - - - - - - + - - - + + + + + - - - + + + + + + + + + + + + + + - - - - - + - - - - - - - - - - - - + + + - - - - - - - - - - - - - - + - - - + - - - + + + + - + + + + + + + + + + + + + + + + - - + + + - - - - - + - - - - + + + - + - + - - - - + + + + - - - - - - + + + + + + - - - - - - - + + + + + + + - - - + + + - - - + + + - - - + - - - - - + - - - - + + + + - + - + - - - - + + + + - - - - - - + + + + + + - - - - - - - + + + + + + + - - - + + + - - - + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - + - - - - + + + + - + - + - - - - + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - - - + + - - - + + - - + + + + + + + - - - + + + - - + - - - - + + + + + + - + + - + + - - - - + + + + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + - - + + + + + - - + + + + + - - + + + + + + + + + + + - + + + + + + + + @@ -1966,7 +3153,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - + + - + @@ -2025,7 +3216,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -2037,11 +3228,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - + - + + to_type="len12_y,len6_y,len6y_stub,4len2D_x,3len2D_x,2len4D_y,len4_x" + to_switchpoint="0" /> + + + @@ -2117,11 +3320,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - @@ -2167,7 +3373,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + + + + @@ -2200,7 +3412,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - @@ -2233,7 +3446,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create to_type="len1_x,len1_y,len2_x,len2x_stub,len4_x,len4x_stub,len2_y,len2y_stub,len6_y,len6y_stub,len1D_y,1len4D_y,4len1D_x,4len2D_x,2len4D_y,3len2D_x" to_switchpoint="0" /> - - - @@ -2333,14 +3549,16 @@ and VTR's k6_N10_40nm.xml were pulled from to create + to_type="len1_y,len2_y,len6_y,len12_y,len18_y,len6y_stub,len2y_stub" + to_switchpoint="0" /> - @@ -2391,9 +3609,11 @@ and VTR's k6_N10_40nm.xml were pulled from to create from_type="len1D_x,2len1D_x,3len1D_x,4len1D_x" from_switchpoint="0" to_type="1len4D_y,2len4D_y,3len4D_y,4len4D_y,len1D_y,2len1D_y,3len1D_y,4len1D_y" to_switchpoint="0" /> - + to_type="len1_y,len2_y,len6_y,len12_y,len18_y,len6y_stub,len2y_stub,stub_y" + to_switchpoint="0" /> @@ -2419,7 +3639,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + from_type="len1_x,len2_x,len4_x,len12_x,len4x_stub,len2x_stub,stub_y" from_switchpoint="0" + to_type="len1_y,len2_y,len6_y,len12_y,len18_y,len6y_stub,len2y_stub,stub_y" + to_switchpoint="0" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + From eaf268b2eec1c6b463d643180cb3b02d81f1959c Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 20 Jun 2024 09:45:10 -0600 Subject: [PATCH 05/10] Extensive notes and fixed most SB issues --- .../arch/xilinx/7series_BRAM_DSP_cary.xml | 492 +++++++++++++----- 1 file changed, 355 insertions(+), 137 deletions(-) diff --git a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml index 02bc7f72520..4f7d4b8351c 100644 --- a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml +++ b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml @@ -131,6 +131,11 @@ and VTR's k6_N10_40nm.xml were pulled from to create unidirectional architecture, an fc value of 20% and any channel width <170 will have no connections to the clb ports. --> + @@ -160,6 +165,10 @@ and VTR's k6_N10_40nm.xml were pulled from to create + + + + clb.CLK clb.I clb.O @@ -603,18 +612,18 @@ and VTR's k6_N10_40nm.xml were pulled from to create 1 1 1 - - 1 0 0 0 0 1 - 1 0 0 0 1 + 1 0 0 0 1 + 1 0 0 1 - - 1 0 0 1 - 1 0 1 + 1 0 1 + 1 1 - - - @@ -1136,9 +1140,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - - + + + + @@ -3227,66 +3338,94 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + - + + - - + - + - + - - + - + - - - - + - - - + - - - + - - + + @@ -3313,90 +3455,108 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - - + - - - - + - + - - - - + + + - - + - - - - - + + - - - + + - - + - - - + @@ -3405,30 +3565,37 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - - + - - + + - + - - + @@ -3437,12 +3604,14 @@ and VTR's k6_N10_40nm.xml were pulled from to create to_type="len1_x,len2_x,len2x_stub,len4_x,len4x_stub,len1_y,len2_y,len2y_stub,len6_y,len6y_stub,4len1D_x,4len2D_x,3len2D_x,3len1D_x,len1D_y,1len4D_y,2len4D_y,2len1D_y" to_switchpoint="0" /> - - - + + - @@ -3450,18 +3619,21 @@ and VTR's k6_N10_40nm.xml were pulled from to create from_switchpoint="0" to_type="len18_y,len12_y" to_switchpoint="0" /> - - + - - + @@ -3469,40 +3641,45 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - - + - - - - + - - + - @@ -3513,33 +3690,42 @@ and VTR's k6_N10_40nm.xml were pulled from to create to_type="len12_x" to_switchpoint="0" /> - + - - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + @@ -3610,39 +3807,52 @@ and VTR's k6_N10_40nm.xml were pulled from to create to_type="1len4D_y,2len4D_y,3len4D_y,4len4D_y,len1D_y,2len1D_y,3len1D_y,4len1D_y" to_switchpoint="0" /> - + - + - + - + - + - - + + - + - + - + - + - - + - + - @@ -3677,7 +3889,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + + @@ -3709,4 +3926,5 @@ and VTR's k6_N10_40nm.xml were pulled from to create + \ No newline at end of file From 8761fe600d72b9eb4ae4a82be06c345b1556fc9a Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 3 Oct 2024 23:18:29 -0600 Subject: [PATCH 06/10] added most up to date arch with extra notes and verified SB and CB. --- .../arch/xilinx/7series_BRAM_DSP_cary.xml | 3718 +++++++---------- 1 file changed, 1592 insertions(+), 2126 deletions(-) diff --git a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml index 4f7d4b8351c..850cf26c05a 100644 --- a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml +++ b/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml @@ -1,31 +1,76 @@ - - - - - + @@ -53,26 +98,24 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - - + + - - + + - - + - @@ -82,18 +125,17 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - + + @@ -102,7 +144,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + io.outpad io.inpad io.clock io.outpad io.inpad io.clock @@ -111,76 +153,137 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + + + + + + - + - - + + + - - + - - - - - + + + + + - - - - - - + + + + - - + + - - + + - + + + + + + + + + + + - clb.CLK clb.I clb.O - clb.CLK clb.I clb.O clb.cout - clb.CLK clb.I clb.O clb.cin - clb.CLK clb.I clb.O + CLB.CLK CLB.I CLB.O CLB.SR1BEG_S0_IN CLB.SR1BEG_S0_OUT CLB.NL1BEG_N3_IN + CLB.NL1BEG_N3_OUT + CLB.CLK CLB.I CLB.O CLB.cout CLB.SR1BEG_S0_IN CLB.SR1BEG_S0_OUT + CLB.NL1BEG_N3_IN CLB.NL1BEG_N3_OUT + CLB.CLK CLB.I CLB.O CLB.cin CLB.SR1BEG_S0_IN CLB.SR1BEG_S0_OUT + CLB.NL1BEG_N3_IN CLB.NL1BEG_N3_OUT + CLB.CLK CLB.I CLB.O CLB.SR1BEG_S0_IN CLB.SR1BEG_S0_OUT CLB.NL1BEG_N3_IN + CLB.NL1BEG_N3_OUT - + - @@ -197,51 +300,20 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 + BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 + BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 + BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 + + + - + @@ -252,50 +324,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - - - - - - - - - - - + DSP.clk DSP.A DSP.B DSP.P DSP.clk DSP.A DSP.B DSP.P DSP.clk DSP.A DSP.B DSP.P DSP.clk DSP.A DSP.B DSP.P - @@ -306,36 +341,18 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - - - + with 'CLB'--> + + + + + + + - @@ -343,7 +360,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + @@ -353,11 +371,95 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -367,81 +469,85 @@ and VTR's k6_N10_40nm.xml were pulled from to create + Frequencies are calculated by dividing each wire segments count in the horizontal/vertical + direction by the total width/hight of the architecture --> + and bidirectional segments within the same segmentlist is needed. For now we declare all segments + as unidirectional --> - - - - + + 1 0 1 1 1 - - + + 1 0 1 1 1 - - + + 1 0 0 1 1 0 1 - - + + 1 0 0 1 1 0 1 - - + + 1 0 0 0 0 1 1 0 0 0 1 - - + + 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 - - - 1 0 0 0 0 0 0 0 0 0 0 0 0 1 - 1 0 0 0 0 0 0 0 0 0 0 0 1 + + + + 1 0 0 0 0 0 0 1 0 0 0 0 0 1 + 1 0 0 0 0 0 0 1 0 0 0 0 1 - - + + + 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 - - + + 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 @@ -449,52 +555,52 @@ and VTR's k6_N10_40nm.xml were pulled from to create + wires into four separate parts so that all intercardinal directions may be specified without + conflict when SB unions occur. + The same thing is done to length 2 wires--> + | <===========|SW |============> | NW NW |============ v v =========| NE + + + --> - - + we get 8.4% per segement type--> + + 1 0 0 0 1 1 0 0 0 - - + + 1 0 0 0 1 1 0 0 0 - - + + 1 0 0 0 1 1 0 0 0 - - + + 1 0 0 0 1 1 0 0 0 @@ -502,28 +608,28 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + 1 0 1 0 1 - - + + 1 0 1 0 1 - - + + 1 0 1 1 0 - - + + 1 0 1 1 0 @@ -535,98 +641,96 @@ and VTR's k6_N10_40nm.xml were pulled from to create (0.023*190=4.5). To compensate this, we split the wires up in a smarter way: type1 has 6 segments per chanel (6/190=3.15%) while the type 2-4 have 4 segments per channel (4/190=2.1%).--> - - + + 1 1 1 - - + + 1 1 1 - - + + 1 1 1 - - + + 1 1 1 - - + + 1 1 1 - - + + 1 1 1 - - + + 1 1 1 - - + + 1 1 1 - - - - - + used to approximate that behavior. --> + + + + 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 - - - + + + 1 0 1 1 1 1 1 - - + + 1 0 0 0 1 1 0 0 1 - - + + 1 0 1 1 1 - - - + + 1 1 1 - @@ -682,7 +786,8 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + - + + + + - + + + + @@ -734,9 +845,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create + LUT. These values are pulled from f4pga/symbiflow's arch file--> 1.5200000000000002e-10 @@ -779,10 +888,11 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + 1.6200000000000002e-10 @@ -821,22 +931,23 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + - - - - - + @@ -848,17 +959,16 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + - + + + b input of the adder is the output of a mux that can choose either O5 or AX. --> @@ -874,8 +984,10 @@ and VTR's k6_N10_40nm.xml were pulled from to create out_port="fle.outMUX" /> - + + + - - + + @@ -913,216 +1025,65 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1.5200000000000002e-10 - 1.5200000000000002e-10 - 1.5e-10 - 1.5e-10 - 1.5e-10 - 1.18e-10 - 1.18e-10 - - - 4.4e-11 - 4.4e-11 - 4.2000000000000004e-11 - 4.6e-11 - 4.8e-11 - 4.8e-11 - 4.8e-11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - 1.5200000000000002e-10 - 1.5200000000000002e-10 - 1.5e-10 - 1.5e-10 - 1.5e-10 - 1.18e-10 - 1.18e-10 - 1.18e-10 - - - 4.4e-11 - 4.4e-11 - 4.2000000000000004e-11 - 4.6e-11 - 4.8e-11 - 4.8e-11 - 4.8e-11 - 4.8e-11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - - - + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + @@ -1253,33 +1218,32 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - + + + + + + + - + - - - - + + - - - - - - + used and should be locked high except with cascade. --> + + + @@ -1289,80 +1253,62 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - - + - - - + + - - - - + used and should be locked high except with cascade. --> + + @@ -1372,83 +1318,60 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - + - - - + - - - - - + + + @@ -1458,84 +1381,61 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + + - - + - - + - - + - + - - - + - - - - - - + + + @@ -1546,83 +1446,59 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - - + - - - + - - - - - - + + + @@ -1632,643 +1508,353 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - + + - - - - - - - - - - - - + + + + + + - - + - - - - - - - - - - - + + + + + + + - - - - - + + - - - - - - - - - - - + - - - + - - + - - - - - + - - + - - - - - - - - + - - - - - - - + + - + - - - - - - - - - - - - + + + + + + + + - - + - - + - - + + - - + - + + + - - - + - - - - - + + + - + - - - - - - - - - - - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + - - + - - + - - - + - - - + - - - - - + + - - - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - - + - - - - - + + - - - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - + - - - - + - - - - - - - - - - - + + + + + + + + - - - - - - - - - + - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - + - - - + - + + - - + - - + - - + - - + - - + + - - + - - - + + + + + + + + - - - - - + + + + + + + + + + + + + + - + - - - + + + - - - - - + + + @@ -2278,80 +1864,64 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - + + - - - - - - - + + + + + @@ -2361,83 +1931,58 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - + - - + - - - - - - + + @@ -2447,83 +1992,60 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + - - + - - + - - + - - + - - - + - - + - - + - - + - + - - + - - - - - - + + + @@ -2534,82 +2056,60 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - + - - + - - + - - + - - + - - + - - + - - + - + + - - + - - - - - - + + + @@ -2619,485 +2119,435 @@ and VTR's k6_N10_40nm.xml were pulled from to create + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + + - - - + + + + - - + + + + + + + + + + + + - - - - + + + + + + + + + + + + + + + + + + + - - + - - + - - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + + + + + + + - - + - - - + - - + + - + - - - - + - - - - + - + - - - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - + - - - - + - + - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - + - - - - + - + - - - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - + - - - - + - + - - - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - + - - - - + - + - - - - - - - - - - - + + + + + + + + - - + - - + - - + - - + - + - - + - - - - + - + - - - - - - - - - - - + + + + + + + + - - + - - + - - - - - + - - + - + - + - - - - - - - - - - - - - - - - - - - - - - + - - + - - + - - + - - - + - - + - - + - + + + @@ -3114,8 +2564,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create in: D(25) out: technicly the ACOUT --> - - + @@ -3134,32 +2583,28 @@ and VTR's k6_N10_40nm.xml were pulled from to create out_port="mult_25x18.P" /> - - - + + + - - + + - + - - + + - + - - + to_switchpoint="0" switch_override="electrical_short" /> + to_type="3len4D_y" to_switchpoint="0" switch_override="electrical_short" /> + to_switchpoint="0" switch_override="electrical_short" /> + to_type="3len1D_y" to_switchpoint="0" switch_override="electrical_short" /> @@ -3313,27 +2756,50 @@ and VTR's k6_N10_40nm.xml were pulled from to create + to_type="2len2D_x" to_switchpoint="0" switch_override="electrical_short" /> + to_type="4len4D_y" to_switchpoint="0" switch_override="electrical_short" /> + to_switchpoint="0" switch_override="electrical_short" /> + to_type="4len1D_y" to_switchpoint="0" switch_override="electrical_short" /> + + - + @@ -3349,35 +2815,30 @@ and VTR's k6_N10_40nm.xml were pulled from to create single connections on diagonal --> - - + - + - - + - @@ -3388,65 +2849,57 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - + - - + - - + - - - - - N1 has 16 connections on its own. The other connections have (64-16)/9=5.3~5 + connections per wire. len1_y has 7 terminating connections per SB.--> + - - - + - - + @@ -3462,36 +2915,31 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - - - - + - + - + - - @@ -3500,50 +2948,48 @@ and VTR's k6_N10_40nm.xml were pulled from to create South bound connections (from top only) --> - - - - + + - + - + + - - - - - - + + @@ -3551,17 +2997,18 @@ and VTR's k6_N10_40nm.xml were pulled from to create to_type="len12_x,len12_y,len18_y,len6_y,len6y_stub,4len2D_x,3len2D_x,2len4D_y,len4_x,len4x_stub" to_switchpoint="0" /> - - + + @@ -3573,33 +3020,41 @@ and VTR's k6_N10_40nm.xml were pulled from to create + NE 2,6 from R --> - + - - + + - + + - + @@ -3608,10 +3063,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create WW4 WW2 interconn --> - + - + @@ -3625,11 +3083,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create - - + + + @@ -3654,11 +3114,13 @@ and VTR's k6_N10_40nm.xml were pulled from to create we leave it becaus it is the one and only outlier. we alwo cant do one type of NE turn in the same direction --> - + - + @@ -3667,40 +3129,41 @@ and VTR's k6_N10_40nm.xml were pulled from to create - + - + - + - - - - + - @@ -3708,7 +3171,10 @@ and VTR's k6_N10_40nm.xml were pulled from to create End connection from wires->stubs --> + Start Perimiter connections. Note that these are not accurate to the 7-seruies. The actual 7-series + chip set wraps wires on the edges of the chip back into the same channel. Since we dont + currently have a way to do this in VTR we simply create highly connected SB along the edges of + the chip. --> @@ -3894,7 +3360,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create to ensure there is always a connection from a stub. --> + to_type="stub_y" to_switchpoint="0" switch_override="electrical_short" /> @@ -3909,7 +3375,7 @@ and VTR's k6_N10_40nm.xml were pulled from to create from_switchpoint="0" to_type="len4x_stub" to_switchpoint="0" /> + to_switchpoint="0" switch_override="electrical_short" /> @@ -132,10 +130,10 @@ - - + @@ -153,7 +151,6 @@ - @@ -168,42 +165,42 @@ + global routing for outputs. This information comes from the tables in + netcracker. Note that this is on a channel basis on the xilinx parts. + because the seven series architecture has a large verity of channel segments, an absolute fc value + is needed to allow interconnect at lower channel widths given that some segment types only + take up a small percentage of the channels in the architecture. For example, the cardinal length 2 + vertical wires (len2_y) only take up 6% of routing segments. Since we are working with a + unidirectional architecture, an fc value of 20% and any channel width <170 will have no + connections to the CLB ports. --> - + + input/output pins note that the ordering matters (i.e. 7-0 means that 7 is the 0th pin). These are + numbered from top to bottom of the INTL: + ## Names of the pips that drive CLB and FF inputs in SLICE_LL: + BYP[_L]7-0 (6-13) Translates to A/B/C/DX inputs in the two SLICE_Ls. BYP for bypass. |__56 inputs! + IMUX[_L]47-0 (14-61) LUT inputs. | + LOGIC_OUTS[_L]23-0 (62-85) BLE outputs. ==> 24 outputs! + + ## Names of pins that drive MUXes: + CTRL[_L]1-0 (2-3) + FAN[_L]7-6 (4-5) + + + ## Name of pin that drives clock: + CLBLL_CLK1 (0) + CLBLL_CLK0 (1) + + Note that this numbering is reversed for our implementation since the ALUT is on the bottom of the + SLICE_L and the DLUT is on the top--> @@ -235,31 +232,31 @@ + L1 and L2 wires directly, + L4 and L6 can also drive and be driven by lut inputs/outputs through SR1BEG_S0 AND NL1BEG_N3 PIPJs. + With some probing in the architecture we discovered the following: + + SR1BEG_S0 connections: + // [46,45,38,37,30,29,22,21,14,13,6,5] + I[1,2,9,10,17,18,25,26,33,34,41,42] can be driven by: + 2 extra: len2_y(SS/NN2), len6_y(NN/SS6), WW1, SS1 + 1 extra: SW2, NW2, SW6, NW6 + + O[3,7,11,15,17,21] can drive: + 2 extra: SS1, len1_x(WW/EE1) + 1 extra: L12, L18, SE2, SS2, SW2, WW2 + + NL1BEG_N3 connections: + I[5,6,13,14,21,22,29,30,37,38,45,46] can be driven by: + 2 extra: WW1, 1len4D_y(SW6, NE6), NN1, 1LEN2D_x(SW2, NE2) + 1 extra: NN2, NN6, NW2, NW6, WW2, WW4 + + O[0,4,8,12,18,22] can drive: + 2 extra: NN1, len1_x (EE/WW1) + 1 extra: EE2, NE2, NN2, NW2 + + to do this have a specially named output/input of the CLB that is heavily muxed. + --> @@ -298,18 +295,11 @@ - - - - - BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 - BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 - BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 - BRAM.clk BRAM.do BRAM.we2 BRAM.we1 BRAM.di BRAM.addr1 BRAM.addr2 - - - + + + + + @@ -323,8 +313,8 @@ - - + + DSP.clk DSP.A DSP.B DSP.P DSP.clk DSP.A DSP.B DSP.P @@ -341,18 +331,24 @@ + + with 'CLB'--> - - - - - + + + + + + + @@ -361,7 +357,7 @@ + 0.65 --> @@ -375,7 +371,7 @@ + is pulled from Project X-ray. --> @@ -406,7 +402,7 @@ mux_trans_size="1.222260" buf_size="auto" /> + switches will be overridden in the switch blocks. --> @@ -467,14 +463,14 @@ + The following segment data is pulled from Table 1 of the NetCraker paper by Morten B. Petersen, + Stefan Nikolić and Mirjana Stojilović: see https://dl.acm.org/doi/10.1145/3431920.3439285. + Frequencies are calculated by dividing each wire segments count in the horizontal/vertical + direction by the total width/hight of the architecture --> + and bidirectional segments within the same segmentlist is needed. For now we declare all segments + as unidirectional --> @@ -525,7 +521,7 @@ + in the direct midle of each segment. --> @@ -554,31 +550,31 @@ + contribution of length 4 + wires into four separate parts so that all intercardinal directions may be specified without + conflict when SB unions occur. + The same thing is done to length 2 wires--> + All diagonal wires are named as follows: + 1) a number representing the type of segment as shown bellow + 2) the length of the wire (len2,len1,len4) + 3) if the wire is an x or y component + + The following is a diagram showing how each number correlates to each wire direction: + + Type 1 Type 2 Type 3 Type 4 + NE |===========> SE | <=========| ^ ==========| SE SW |========= ^ + | | | | | | | | + | | | | | | | | + | | | | | | | | + | <===========|SW |============> | NW NW |============ v v =========| NE + + + --> + we get 8.4% per segement type--> @@ -607,7 +603,7 @@ + 6.45% per type --> @@ -636,11 +632,11 @@ + However, we must be extra careful here because + 9.4/4=2.3% which gives us an uneaven number of wires in each chanel at a width of 190 + (0.023*190=4.5). To compensate this, we split the + wires up in a smarter way: type1 has 6 segments per chanel (6/190=3.15%) while the type 2-4 have 4 + segments per channel (4/190=2.1%).--> @@ -667,7 +663,7 @@ + Again we split this into 6 (6/124=4.8%) and 3 sets of 4 (4/124=3.2%) --> @@ -695,10 +691,10 @@ + used to approximate that behavior. --> + Note that these should never be driven at the middle switches--> @@ -707,7 +703,7 @@ + Note that these should never be driven at the middle switch--> @@ -729,16 +725,16 @@ 1 1 - + @@ -754,16 +750,16 @@ + used here to approximate the seven series IO. Timing values + are changed to match the seven series.--> + Delays below are pulled from the IOBUF description + in f4pga/symbiflow's arch.timing.xml + --> @@ -786,20 +782,19 @@ - + + make it physically equivalent on all sides so that only one definition of I/Os is needed. + --> + timing but we leave this for a latter time. --> @@ -811,7 +806,7 @@ + 81 internal cb connections.--> @@ -819,7 +814,7 @@ + To truely match the 7-series there should be 4 COUTs per slice not 1. --> @@ -845,7 +840,7 @@ + LUT. These values are pulled from f4pga/symbiflow's arch file--> 1.5200000000000002e-10 @@ -889,10 +884,10 @@ + * The delay constant for each 5 lut can be found in symbiflow and are given above. + * The delay for in_port to out_port of each port on the MUXF6 is max=10e-12 as given in the + arch.timing.xml. Min is not given so assumed to be the same as max + * We assume the min value is relativly the same. Max adds the MUXF6 delay.--> 1.6200000000000002e-10 @@ -947,7 +942,7 @@ - + @@ -957,7 +952,7 @@ min="9.900000000000001e-11" /> + Delays are pulled from the f4pga/symbiflow arch --> @@ -967,8 +962,7 @@ - + @@ -1056,8 +1050,8 @@ + SLICE_L. + Values are taken from prjxray-db/artix7/tile_int_l --> @@ -1086,11 +1080,11 @@ + These connections where created by running several tcl script on the Xilinx architecture to + determine which BLE outputs connected to LUT inputs. In doi/10.1109/FCCM.2013.40 it was + found that within the Vertix architecture "each BLE output can only connect to 6 LUT inputs + (and conversely, each LUT input can only be reached by 3 BLE outputs)". From our + expirementiation we found that this also holds for the 7-series. --> @@ -1101,112 +1095,131 @@ - - - - - + + - - - + + - - - - - - - - - - - - - - - - - - - + - - - - + + - - + + + + - - + - - - - - + + + - - - + + + + + + + + - + + + - - + - - - - + + + + + + + + + - + @@ -1218,32 +1231,26 @@ - - - - - - - + + + + + + - + - - - + + + - - - - + + + @@ -1253,62 +1260,64 @@ - - - - - - - - - - - - - + + + + + - + + + + + + + + + + - - + + - + - + - + - + - + - + - + - + - + + - - - - - + + + + + @@ -1318,60 +1327,58 @@ + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + - + - + - + - + - + - + - + - + - - - - - + + + + + @@ -1381,61 +1388,60 @@ + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + - + - + - + - - + - + - + - + - + - - + - - - + + + @@ -1446,59 +1452,60 @@ - - - - - - - - - - - - - + + + + + + + + + + + + - - - + - + - + - + - + - + - + - + - + + - - + - - - + + + @@ -1508,353 +1515,448 @@ - - - - - - - - - - - - + + + + + + + + + + + + - - - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + + + - + + + + + + + + + + + + + + - - - - - - - - - + - - + - + - + + + - + + + - + + + + + + - - + + + + + + + + - - + + - + - - - - - - + + + + + + - - + - + - - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + - - + - - - - - - - + + + + + + + + - + - + - + - + - + + + - - + - - + + - - - - - - + + + + + + - - + - + - + - + - + - - + - - + + - - - - - - + + + + + + - - + - + - + - + - + - - + - + - - - - - - + + + + + + - - + - + - - - + - + - + - - - - - - - - - - - - - - - + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + - - + - + - - + - - - - - - + + + + + + - + - - - - + + - - - + + + + @@ -1864,64 +1966,62 @@ + - - - - - - - - - - - - - - - + + + + + + + + + + + + - - - - + - + - + - + - + - + - + - + - + - - + - - - - - + + + + + @@ -1931,58 +2031,60 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + + - - + - + - + - + - + - + - + - + - + - - - + - - + + + @@ -1992,562 +2094,465 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + - - + - + - + - + - + - + - + - + - + - + - - - + + - - + + - - + + - - - - - - - - - - - - - + + + + + + + + + + + + + + - - + - + - + - + - + - + - + - + - + - - - + - - + + - - + + - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - - + - + - - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + - + + - - + + - + - + - - - - - - - + + + + + + + + - + - + - + - + - + - - - + - + - + + + + + + + - - - - - - - - - - + - + - + - + - + - - - + - + - + - - - - - - + + + + + + - - + - + - + - + - + - - - + - + - + - - - - - - + + + + + + - - + - + - + - + - + - - - + - + - + - - - - - - + + + + + + - - + - + - + - + - + - - + - + - + - - - - - - + + + + + + - - + - + - + + + - + - + + - - + - + - + - + - + + - + - + + + + + + + + + + + + + + + + + block are to be added at a later date --> - @@ -2555,15 +2560,15 @@ + PORTS FOR MULT: + in: A (30->lower 25x2), B (18x2), clk (only if you include the ffs) + out: P (48x2) + + Ports for pre-add: + All the above plus + in: D(25) + out: technicly the ACOUT + --> @@ -2608,114 +2613,114 @@ + width of 190: + Segment_name Designation Count + len1_x WW/EE1 14 + len1_y SS/NN1 14 + len2_x WW/EE2 12 + len2_y SS/NN2 12 + len4_x WW/EE4 24 + len6_y SS/NN6 36 (34 from stub_y) + len12_x WW/EE12 12 + len12_y SS/NN12 12 + len18_y SS/NN18 18 + + 1len4D_y NE/SW6 16 + 2len4D_y SE/NW6 16 + 3len4D_y SE/NW6 16 + 4len4D_y NE/SW6 16 + 1len2D_x NE/SW6 8 + 2len2D_x SE/NW6 8 + 3len2D_x SE/NW6 8 + 4len2D_x NE/SW6 8 + + Totals: NE/SW6 32 + SE/NW6 32 + + len1D_y NE/SW2 6 + 2len1D_y SE/NW2 4 + 3len1D_y SE/NW2 4 + 4len1D_y NE/SW2 4 + len1D_x NE/SW2 6 + 2len1D_x SE/NW2 4 + 3len1D_x SE/NW2 4 + 4len1D_x NE/SW2 4 + + Totals: NE/SW2 10 + SE/NW2 8 + + len6y_stub SS/NN6 12 + len2y_stub SS/NN2 4 + len4x_stub WW/EE4 8 + len2x_stub WW/EE2 4 + stub_y NONE 2 + + Note: As was stated in the netcracker paper, + a channel width in the traditional sense is + a little misleading because the longer L shaped + wires (i.e. len6 diagonals) contribute diffrent + channel widths in the X and Y directions. + Also note that Table 1 in the netcracker paper + clumps the parts of these L shaped wires into + their respective cardinal parts. For example: + length 2 H wires includes the count for both + cardinal length 2 wires and the diagonal + length 2 component of a multi-cardinal + length 6 wire. Same goes for length 1 + (two length 1 components of a diagonal length 2) + and length 4 V wires (a component of the diagonal + length 6). + + + The following are the totals for each wire type. + In cases where a segment is made up of multiple + wire types in the X and Y (i.e. multi-cardinal + wires) the number of wires in the Y channel is + used. + + Designation Count Num_Terminating/Starting_Per_SB + Totals: NN1 7 7 + SS1 7 7 + WW1 7 7 + EE1 7 7 + + NE2 5 2/3 + SE2 4 2 + NW2 4 2 + SW2 5 2/3 + + NN2 8 2 + SS2 8 2 + WW2 8 2 + EE2 8 2 + + NE6 16 2/4 + SE6 16 2/4 + NW6 16 2/4 + SW6 16 2/4 + + NN6 24 2 (1) + SS6 24 2 (1) + + WW4 16 2 + EE4 16 2 + + NN12 6 0/1 + SS12 6 0/1 + WW12 6 0/1 + EE12 6 0/1 + + NN18 9 0/1 + SS18 9 0/1 + + + + NOTE that each multi-cardinal wire is split into two sides of the SB (i.e. NE comes in + from the left and from the bottom). The counts above are for all sides of the SB. + Cut the multi-cardinal values in half to find out the number of wires per side. + + + --> @@ -2773,27 +2778,27 @@ + ? The following wire types have 64 connections out of them: + ? 12.8~13 outputs per wire: + ? SS6, WW4, NN6, SW6, NW6, SS2, WW2, NN2, SW2, NW2, NE2 + ? 16 outputs per wire: + ? EE4, NE6, SE6, EE2, SE2 + ? + ? The follwing L1 wire types have 64 connections out of them: + ? 7.111_~7 outputs per wire: + ? S1, N1 + ? 6.4~7 outputs per wire: + ? W1, E1 + ? + ? Wire types who have feedback: + ? with 16 connections: + ? 3len1D_y, 3len1D_y(bb/tt), 1len2D_x,len1D_x(ll/rr) + ? with 12 connections: + ? 4len4D_y, 4len1D_y(bb/tt), 2len2D_x,2len1D_x(ll/rr) + ? with 8 connections: + ? len2_y,len6_y(bb/tt), len4_x,len2_x(ll/rr) + ? + ? --> @@ -2806,29 +2811,29 @@ + counterparts need to connect. N1 also has 8 cons but we + leave it becaus it is the one and only outlier. we also cant do one type of NE turn in the + same direction--> + with + single connections on diagonal --> + from the bottom of the SB so we are only dealing with NE connections. + Looking at figure 8 in netcracker we see that we connect to four of each + type of wire with the exception of N1. There should be 4/5 wires of this + type per channel (2/3 NE 2/3 SW). From figure 8 in netcracker we see that + NE2 has a total of 64 connections shared between 5 wires. 3 of these + are in the switchblock that comes from the left (from type 4)! + Considering feed back we have (64−12)÷4=13 connections per wire. + We have 2 wires in the from set --> + as found in the + netcracker paper, see figure 8! The NW wire connections are split between 4 segments. + Each wire should make (64−12)÷4=13 connections. So we end up with the same equation as the NW2--> @@ -2848,15 +2853,15 @@ to_switchpoint="0" /> + NN2 and 6 connection --> + wire. --> + connections per wire. --> + NL1 --> + connections per wire. len1_y has 7 terminating connections per SB.--> @@ -2893,12 +2898,12 @@ to_switchpoint="0" /> + Stub connection for L2x--> + stub offshoots we do not count any of the same side connections, instead placing these on the + normal wire types. Because we are coming in from the botom we are only dealing with L2_x stubs + since L4_x stubs only branch down. The number of connections per wire for L2_x (i.e. WW/EE2) is 16 + as stated in the header. There are two stubs terminating per SB.--> @@ -2909,17 +2914,17 @@ + top->botom/left/right --> + slightly diffrent. + For SW6 there are 64 connections going to 5 connections instead of 4. Given this diffrence there + are + (64-12)/5=10.4~10 connections per wire. There are still 2 wires terminating per SB. --> @@ -2929,10 +2934,10 @@ to_switchpoint="0" /> + SE 2,6 from T --> + Therfore we need ~13 connections per wire. 2 terminating wires per SB. We undershoot here since we + overshot above (i.e. round down to 12 instead of up to 14) --> @@ -2945,14 +2950,14 @@ to_switchpoint="0" /> + South bound connections (from top only) --> + SS2, SS6 --> + south bound and north bound wires. + Therefore the counts are the same as the SB above. --> + undershoot here. --> + terminating wires in the from set and there should be 16 wires connected to. --> - - - + + L18 and L12 --> + stub connection for L4x. Same as L2x! in last SB --> - + Right->left/top/bottom --> + NE 2,6 from R --> + technichly WW2, SS2, SS6 is not alowed but we leave it here, N1 also has 8 cons but + we + leave it becaus it is the one and only outlier. we alwo cant do one type of NE turn in the + same direction--> + 6 of these wires in a channel 4/6=2/3 --> + between 5 wires and 16 connections are feedback. + so there should be (64-16)/5=9.6~9 connections per wire. --> + (64-16)/4=12 connections per wire. --> + NW 2,6 from R --> + connections. (64-12)/5=10.4~10 connections per wire --> + WW4 WW2 interconn --> + 6 cons per SB 2/3*to_set rounded up --> + wire --> @@ -3078,13 +3074,13 @@ to_type="len18_y,len12_y" to_switchpoint="0" /> + Technichly len18 and 12 should only be connected to ww4 + not 2--> + WL1 --> + connections per wire. --> @@ -3092,7 +3088,7 @@ + L12 --> @@ -3102,18 +3098,18 @@ + left->right/top/bottom --> + NE 2,6 from L --> + technichly WW2, SS2, SS6 is not alowed but we leave it here, N1 also has 8 cons but + we + leave it becaus it is the one and only outlier. we also cant do one type of NE turn in the + same direction --> + SE 2,6 from L --> + EE4 and EE2 --> + connections per wire --> @@ -3154,44 +3150,42 @@ to_switchpoint="0" /> + EL1 --> - + L12 --> + End connection from wires->stubs --> + Start Perimiter connections. Note that these are not accurate to the 7-seruies. The actual 7-series + chip set wraps wires on the edges of the chip back into the same channel. Since we dont + currently have a way to do this in VTR we simply create highly connected SB along the edges of + the chip. --> + Straight --> + left to right --> + top to bottom --> + right to left --> + bottom to top --> + Same as wilton straight, but turning around a corner --> + Counter-clock-wise turns --> + left to top --> + top to right --> + right to bottom --> + bottom to left --> + Clock-wise turns --> + top to left --> + right to top --> + bottom to right --> + left to bottom --> + Non-corner perimeter SBs --> + Counter-clock-wise turns --> + left to top --> + top to right --> + right to bottom --> + bottom to left --> + Clock-wise turns --> + top to left --> + right to top --> + bottom to right --> + left to bottom --> + We use 'max' style connections here to ensure there are no dangling wires, + otherwise like + core turns --> + L16 drivers --> + End Perimiter connections --> + Start connections with branching stub (i.e. stubs that are not on the same dirrection as + the wire they stem from) --> @@ -3356,8 +3350,8 @@ + No switch override because we are going to be going to other wires as well. this is just + to ensure there is always a connection from a stub. --> @@ -3378,8 +3372,8 @@ to_switchpoint="0" switch_override="electrical_short" /> + Only x dirrected wires have stubs that branch out to a SB perpendicular to the direction + of travel. See Figure 7 in the Netcracker Paper. --> From f3a9ae53f6e1174e8bbbf935c6096b076018a80e Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Tue, 15 Oct 2024 23:12:45 -0600 Subject: [PATCH 08/10] fixed name typo --- .../{7series_BRAM_DSP_cary.xml => 7series_BRAM_DSP_carry.xml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename vtr_flow/arch/xilinx/{7series_BRAM_DSP_cary.xml => 7series_BRAM_DSP_carry.xml} (100%) diff --git a/vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml b/vtr_flow/arch/xilinx/7series_BRAM_DSP_carry.xml similarity index 100% rename from vtr_flow/arch/xilinx/7series_BRAM_DSP_cary.xml rename to vtr_flow/arch/xilinx/7series_BRAM_DSP_carry.xml From 76df5fbe0e642d4dbf82b3b86302dd12fa23b43a Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Thu, 17 Oct 2024 11:29:00 -0600 Subject: [PATCH 09/10] added tests --- ...ss_requirements_vpr_xilinx_fixed_width.txt | 19 +++++++++++ vtr_flow/parse/qor_config/qor_vpr_xilinx.txt | 12 +++++++ .../vtr_xilinx_qor/config/config.txt | 34 +++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt create mode 100644 vtr_flow/parse/qor_config/qor_vpr_xilinx.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt diff --git a/vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt b/vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt new file mode 100644 index 00000000000..5e01a4cc208 --- /dev/null +++ b/vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt @@ -0,0 +1,19 @@ +# Xilinx specific requirements for VTR pass +%include "common/pass_requirements.vpr_status.txt" +%include "timing/pass_requirements.vpr_pack_place.txt" + +#Routing Metrics +routed_wirelength;RangeAbs(0.50,1.50,5) + +#Area metrics +logic_block_area_total;Range(0.5,1.6) +logic_block_area_used;Range(0.5,1.6) +min_chan_width_routing_area_total;Range(0.5,1.6) +min_chan_width_routing_area_per_tile;Range(0.5,1.6) + +#Run-time metrics +crit_path_route_time;RangeAbs(0.10,10.0,2) + + +#Peak memory +max_vpr_mem;RangeAbs(0.5,2.0,102400) \ No newline at end of file diff --git a/vtr_flow/parse/qor_config/qor_vpr_xilinx.txt b/vtr_flow/parse/qor_config/qor_vpr_xilinx.txt new file mode 100644 index 00000000000..649a02d19bb --- /dev/null +++ b/vtr_flow/parse/qor_config/qor_vpr_xilinx.txt @@ -0,0 +1,12 @@ +vpr_status;output.txt;vpr_status=(.*) +total_wirelength;vpr.out;\s*Total wirelength: (\d+) +#total_wirelength_(mcw);vpr.out;Total wirelength:\s*(\d+) +#total_wirelength_(1.3mcw);vpr.crit_path.out;Total wirelength:\s*(\d+) +total_runtime;vpr.out;The entire flow of VPR took (.*) seconds +#pack_time;vpr.out;Packing took (.*) seconds +#place_time;vpr.out;Placement took (.*) seconds +#route_time;vpr.out;Routing took (.*) seconds +#num_pre_packed_nets;vpr.out;Total Nets: (\d+) +#num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+) +crit_path_delay;vpr.crit_path.out;Final critical path: (.*) ns + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt new file mode 100644 index 00000000000..9fc4e235659 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/config.txt @@ -0,0 +1,34 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of architectures to use +archs_dir=arch/xilinx + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Add architectures to list +arch_list_add=7series_BRAM_DSP_carry.xml + +# Add circuits to list to sweep +circuit_list_add=LU32PEEng.v +circuit_list_add=LU8PEEng.v +circuit_list_add=bgm.v +circuit_list_add=stereovision0.v +circuit_list_add=stereovision1.v +circuit_list_add=stereovision2.v + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_xilinx.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_xilinx_fixed_width.txt + +# Xilinx Benchmarks route at the physical channel +# width of the chip which is 190. Flat routing is +# also enabled. +script_params=--route_chan_width 190 --flat_routing on \ No newline at end of file From 9b53ef40702acb2119b3cce9ccad45a657103466 Mon Sep 17 00:00:00 2001 From: Joshua Fife Date: Sat, 19 Oct 2024 22:54:27 -0600 Subject: [PATCH 10/10] added golden --- .../vtr_xilinx_qor/config/golden_results.txt | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt new file mode 100644 index 00000000000..ce120048235 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vtr_xilinx_qor/config/golden_results.txt @@ -0,0 +1,7 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +7series_BRAM_DSP_carry.xml LU32PEEng.v common 19250.12 vpr 3.53 GiB -1 -1 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