From 827bdde269541dac9cd605ace23b00cbbd6fcfc5 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 3 Mar 2020 10:55:19 -0800 Subject: [PATCH 1/2] Adjust vtr_reg_weekly with less effort on Titan, and remove gaussian blur Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- .github/kokoro/continuous/weekly.cfg | 4 +- .github/kokoro/presubmit/weekly.cfg | 4 +- .../vtr_reg_weekly_no_he/task_list.txt | 5 ++ .../vpr_ispd/config/config.txt | 38 ++++++++++++ .../vpr_ispd/config/golden_results.txt | 10 ++++ .../config/config.txt | 35 +++++++++++ .../config/golden_results.txt | 9 +++ .../config/config.txt | 35 +++++++++++ .../config/golden_results.txt | 8 +++ .../config/config.txt | 48 +++++++++++++++ .../config/golden_results.txt | 22 +++++++ .../vtr_reg_titan/config/config.txt | 60 +++++++++++++++++++ .../vtr_reg_titan/config/golden_results.txt | 24 ++++++++ 13 files changed, 298 insertions(+), 4 deletions(-) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/task_list.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/golden_results.txt create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/golden_results.txt create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/config.txt create mode 100755 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/golden_results.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/golden_results.txt diff --git a/.github/kokoro/continuous/weekly.cfg b/.github/kokoro/continuous/weekly.cfg index 25992926771..5ecfeda13d3 100644 --- a/.github/kokoro/continuous/weekly.cfg +++ b/.github/kokoro/continuous/weekly.cfg @@ -36,10 +36,10 @@ env_vars { env_vars { key: "VTR_TEST" - value: "vtr_reg_weekly" + value: "vtr_reg_weekly_no_he" } env_vars { key: "NUM_CORES" - value: "1" + value: "3" } diff --git a/.github/kokoro/presubmit/weekly.cfg b/.github/kokoro/presubmit/weekly.cfg index 493498508a6..bacb0a68db9 100644 --- a/.github/kokoro/presubmit/weekly.cfg +++ b/.github/kokoro/presubmit/weekly.cfg @@ -36,10 +36,10 @@ env_vars { env_vars { key: "VTR_TEST" - value: "vtr_reg_weekly" + value: "vtr_reg_weekly_no_he" } env_vars { key: "NUM_CORES" - value: "1" + value: "3" } diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/task_list.txt new file mode 100644 index 00000000000..bf53394a2a7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/task_list.txt @@ -0,0 +1,5 @@ +regression_tests/vtr_reg_weekly/vtr_reg_titan +regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off +regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch +regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch +regression_tests/vtr_reg_weekly/vpr_ispd diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/config.txt new file mode 100644 index 00000000000..940a0f32268 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/config.txt @@ -0,0 +1,38 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/ispd_blif + +# Path to directory of architectures to use +archs_dir=arch/ispd + +# Add circuits to list to sweep +circuit_list_add=FPGA-example1.blif +circuit_list_add=FPGA-example2.blif +circuit_list_add=FPGA-example3.blif +circuit_list_add=FPGA-example4.blif +circuit_list_add=clk_design1.blif +circuit_list_add=clk_design2.blif +circuit_list_add=clk_design3.blif +circuit_list_add=clk_design4.blif +circuit_list_add=clk_design5.blif + +# Add architectures to list to sweep +arch_list_add=ultrascale_ispd.xml + +# Parse info and how to parse +parse_file=vpr_ispd.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_ispd.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_ispd.txt + +#The ISPD architecture is missing a detailed rouing architecture model and +#timing model, so we only do wirelength-driven packing and placement +script_params=-starting_stage vpr --pack --place --timing_analysis off + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/golden_results.txt new file mode 100644 index 00000000000..6ae56c8092e --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/golden_results.txt @@ -0,0 +1,10 @@ +arch circuit script_params vtr_flow_elapsed_time error num_IO num_CLB num_DSP num_BRAM vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time +ultrascale_ispd.xml FPGA-example1.blif common 62.36 72 220 2 2 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example1.blif/common 4696036 51 20 3417 3407 1 3287 296 168 480 80640 -1 ultrascale_ispd 4.61 29531 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml FPGA-example2.blif common 5665.13 456 39262 200 400 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example2.blif/common 7117412 303 150 545542 542692 1 539559 40318 168 480 80640 -1 ultrascale_ispd 712.51 5830359 4853.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml FPGA-example3.blif common 5157.95 606 30856 200 500 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example3.blif/common 6647732 403 200 431203 428403 1 429172 32162 168 480 80640 -1 ultrascale_ispd 539.91 16335580 4528.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml FPGA-example4.blif common 5383.65 -1 -1 -1 -1 v8.0.0-rc1-1301-g9c76833f6 exited with return code 1 pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example4.blif/common 5722520 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 5368.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml clk_design1.blif common 71.03 109 592 2 2 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design1.blif/common 4720436 57 20 9969 9959 30 9711 705 168 480 80640 -1 ultrascale_ispd 8.47 63424 5.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml clk_design2.blif common 387.99 244 5837 10 10 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design2.blif/common 5114708 137 60 100115 100025 45 97978 6101 168 480 80640 -1 ultrascale_ispd 83.13 924709 241.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml clk_design3.blif common 2467.90 374 22993 50 96 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design3.blif/common 6314720 217 120 400080 399454 35 390926 23513 168 480 80640 -1 ultrascale_ispd 223.80 4772904 2160.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml clk_design4.blif common 5289.21 484 39151 150 366 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design4.blif/common 7472784 292 150 685438 683387 40 669318 40151 168 480 80640 -1 ultrascale_ispd 376.84 8539380 4810.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +ultrascale_ispd.xml clk_design5.blif common 8688.37 515 51693 420 885 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design5.blif/common 8448644 307 150 948147 942073 56 928185 53513 168 480 80640 -1 ultrascale_ispd 545.08 12115275 8024.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/config.txt new file mode 100755 index 00000000000..e3d850b5396 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/config.txt @@ -0,0 +1,35 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/fpu/hardlogic + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=bfly.v +circuit_list_add=bgm.v +circuit_list_add=dscg.v +circuit_list_add=fir.v +circuit_list_add=mm3.v +circuit_list_add=ode.v +circuit_list_add=syn2.v +circuit_list_add=syn7.v + +# Add architectures to list to sweep +arch_list_add=hard_fpu_arch_timing.xml + +# Parse info and how to parse +parse_file=vpr_hard_fpu.txt + +# Pass requirements +pass_requirements_file=pass_requirements_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_fixed_chan_width.txt + +# Parameters for vtr flow +script_params=--route_chan_width 72 --cluster_seed_type max_inputs -track_memory_usage diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/golden_results.txt new file mode 100644 index 00000000000..c8e1e4dc3ce --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/golden_results.txt @@ -0,0 +1,9 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time num_fpu +hard_fpu_arch_timing.xml bfly.v common 3.10 0.03 6620 1 0.02 -1 -1 30892 -1 -1 0 193 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/bfly.v/common 40896 193 64 833 649 1 353 260 24 24 576 io auto 1.44 5339 0.41 2.985 -1309.66 -2.985 7203 559 754 4340409 2003241 1.06129e+06 103149 1.28794e+06 2236.02 13 2.985 -1355.06 -2.985 -40.8482 -0.0851 0.67 3 +hard_fpu_arch_timing.xml bgm.v common 9.40 0.05 8104 1 0.02 -1 -1 31424 -1 -1 0 257 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/bgm.v/common 68076 257 32 1281 693 1 1021 299 38 38 1444 block_FPU auto 4.48 16846 0.95 2.985 -3096.52 -2.985 23528 1716 2179 18887582 10238670 2.90196e+06 343832 3.35777e+06 2325.33 7 2.985 -3435.84 -2.985 -24.8888 -0.0851 3.10 10 +hard_fpu_arch_timing.xml dscg.v common 7.59 0.02 6536 1 0.02 -1 -1 30756 -1 -1 0 129 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/dscg.v/common 50012 129 64 769 585 1 513 198 32 32 1024 block_FPU auto 3.35 7420 0.47 2.985 -1357.81 -2.985 11615 939 1400 17487121 11324201 2.063e+06 171916 2.37490e+06 2319.23 15 2.985 -1527.85 -2.985 -21.8252 -0.0851 3.11 5 +hard_fpu_arch_timing.xml fir.v common 29.85 0.03 6912 1 0.02 -1 -1 31168 -1 -1 37 161 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/fir.v/common 46060 161 32 993 808 1 545 234 30 30 900 block_FPU auto 27.92 6256 0.45 2.985 -1321.72 -2.985 9044 953 1084 5657511 2628249 1.6779e+06 222344 2.03108e+06 2256.75 16 2.985 -1440.07 -2.985 -39.3898 -0.0851 0.85 4 +hard_fpu_arch_timing.xml mm3.v common 1.79 0.02 6268 1 0.02 -1 -1 30584 -1 -1 0 193 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/mm3.v/common 36004 193 32 545 422 1 289 227 21 21 441 io auto 0.81 3143 0.27 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.31 2 +hard_fpu_arch_timing.xml ode.v common 28.03 0.04 7192 1 0.04 -1 -1 33824 -1 -1 151 130 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/ode.v/common 41180 130 72 1194 1103 1 589 355 19 19 361 io auto 26.54 4572 0.53 2.985 -1332.56 -2.985 6704 1347 1462 2963346 1263428 653279 414890 795482. 2203.55 10 2.985 -1412.63 -2.985 -51.2306 -0.0851 0.42 2 +hard_fpu_arch_timing.xml syn2.v common 3.21 0.01 6692 1 0.01 -1 -1 30668 -1 -1 0 161 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/syn2.v/common 44840 161 128 641 490 1 479 293 30 30 900 block_FPU auto 0.95 8082 0.54 2.985 -1449.51 -2.985 10620 855 1085 6898661 3477644 1.6779e+06 137533 2.03108e+06 2256.75 15 2.985 -1571.61 -2.985 -16.1177 -0.0851 1.11 4 +hard_fpu_arch_timing.xml syn7.v common 21.56 0.05 8768 1 0.03 -1 -1 32564 -1 -1 0 161 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch/run011/hard_fpu_arch_timing.xml/syn7.v/common 116068 161 128 1921 499 1 1697 310 54 54 2916 block_FPU auto 2.21 45345 2.15 2.985 -7881.16 -2.985 62752 3660 6311 83146556 48987913 6.08571e+06 722046 6.89978e+06 2366.18 7 2.985 -8658.95 -2.985 -33.6146 -0.0851 15.74 21 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/config.txt new file mode 100755 index 00000000000..b08566c8148 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/config.txt @@ -0,0 +1,35 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/fpu/softlogic + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=bfly.v +circuit_list_add=bgm.v +circuit_list_add=dscg.v +circuit_list_add=fir.v +circuit_list_add=mm3.v +circuit_list_add=ode.v +circuit_list_add=syn2.v +#circuit_list_add=syn7.v + +# Add architectures to list to sweep +arch_list_add=soft_fpu_arch_timing.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_fixed_chan_width.txt + +# Parameters for vtr flow +script_params=--route_chan_width 72 -track_memory_usage diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt new file mode 100755 index 00000000000..c7116c59f98 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_soft_logic_arch/config/golden_results.txt @@ -0,0 +1,8 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time +soft_fpu_arch_timing.xml bfly.v common 215.95 2.31 156612 60 86.59 -1 -1 85888 -1 -1 6856 193 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/bfly.v/common 366296 193 64 23996 24060 1 18159 7113 85 85 7225 clb auto 4.36 224054 98.69 34.9765 -17061.1 -34.9765 369766 169000 477244 74496612 8115875 1.579e+07 1.57144e+07 1.73164e+07 2396.73 37 37.7732 -17999.3 -37.7732 -52.5443 -0.0851 14.20 +soft_fpu_arch_timing.xml bgm.v common 1285.99 10.09 374688 60 619.38 -1 -1 198116 -1 -1 17930 257 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/bgm.v/common 930532 257 32 62096 62128 1 47778 18219 136 136 18496 clb auto 14.02 599778 581.48 37.794 -43291.6 -37.794 974457 418276 1194686 184804914 20284568 4.11556e+07 4.1096e+07 4.47194e+07 2417.79 34 40.4121 -45724.4 -40.4121 -79.272 -0.0851 36.63 +soft_fpu_arch_timing.xml dscg.v common 195.92 2.19 157464 60 81.69 -1 -1 85456 -1 -1 6510 129 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/dscg.v/common 347208 129 64 22497 22561 1 17043 6703 83 83 6889 clb auto 4.13 213027 85.37 37.0018 -15022 -37.0018 349790 161343 461801 71382699 7817388 1.50382e+07 1.49214e+07 1.65016e+07 2395.36 38 39.1641 -15857.5 -39.1641 -48.1156 -0.0851 13.49 +soft_fpu_arch_timing.xml fir.v common 189.41 1.89 139072 59 75.37 -1 -1 81612 -1 -1 6565 161 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/fir.v/common 351256 161 32 22903 22935 1 17506 6758 84 84 7056 clb auto 4.31 202916 85.12 34.1364 -14702.9 -34.1364 341788 178740 488639 72748715 8144233 1.54118e+07 1.50474e+07 1.69066e+07 2396.05 41 36.7396 -15554.3 -36.7396 -51.5873 -0.0851 13.96 +soft_fpu_arch_timing.xml mm3.v common 106.71 1.13 101356 60 40.20 -1 -1 67164 -1 -1 4687 193 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/mm3.v/common 259868 193 32 16466 16498 1 12558 4912 71 71 5041 clb auto 3.00 143468 46.70 34.6668 -10727.4 -34.6668 243298 123661 342173 51403043 5739422 1.09126e+07 1.0743e+07 1.20254e+07 2385.52 38 37.3116 -11272.2 -37.3116 -30.4366 -0.0851 9.31 +soft_fpu_arch_timing.xml ode.v common 83.81 1.15 102292 59 30.35 -1 -1 53828 -1 -1 4036 130 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/ode.v/common 226776 130 72 14268 14340 1 10622 4238 66 66 4356 clb auto 2.51 122251 36.37 33.6539 -11074.2 -33.6539 204853 100470 280711 41910484 4674407 9.38847e+06 9.25095e+06 1.03689e+07 2380.36 40 36.3613 -11663.1 -36.3613 -62.8441 -0.0851 7.76 +soft_fpu_arch_timing.xml syn2.v common 231.74 2.71 176860 60 98.77 -1 -1 90644 -1 -1 7226 161 -1 -1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch/run010/soft_fpu_arch_timing.xml/syn2.v/common 386076 161 128 25115 25243 1 19176 7515 88 88 7744 clb auto 4.78 244865 101.89 35.0658 -19530.7 -35.0658 397867 165069 482594 77261406 8435302 1.69521e+07 1.65624e+07 1.85753e+07 2398.67 29 38.3451 -20568.6 -38.3451 -37.6131 -0.0851 13.55 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/config.txt new file mode 100644 index 00000000000..eddfe7c026a --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/config.txt @@ -0,0 +1,48 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=arm_core.v +circuit_list_add=bgm.v +circuit_list_add=blob_merge.v +circuit_list_add=boundtop.v +circuit_list_add=ch_intrinsics.v +circuit_list_add=diffeq1.v +circuit_list_add=diffeq2.v +circuit_list_add=LU8PEEng.v +circuit_list_add=LU32PEEng.v +circuit_list_add=mcml.v +circuit_list_add=mkDelayWorker32B.v +circuit_list_add=mkPktMerge.v +circuit_list_add=mkSMAdapter4B.v +circuit_list_add=or1200.v +circuit_list_add=raygentop.v +circuit_list_add=sha.v +circuit_list_add=spree.v +circuit_list_add=stereovision0.v +circuit_list_add=stereovision1.v +circuit_list_add=stereovision2.v +circuit_list_add=stereovision3.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script Parameters +script_params=-track_memory_usage --routing_failure_predictor off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/golden_results.txt new file mode 100644 index 00000000000..fd3170b1df4 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -0,0 +1,22 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 254.41 0.94 128156 18 63.44 -1 -1 69012 -1 -1 1035 133 40 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/arm_core.v/common 328540 133 179 18548 18330 1 9251 1387 44 44 1936 memory auto 20.58 155222 21.88 17.3994 -243532 -17.3994 110 225968 46 1.12988e+08 7.77019e+07 1.35867e+07 7017.93 104.19 205877 16 36052 130220 42883095 9930466 19.2222 -270185 -19.2222 0 0 1.73467e+07 8960.09 9.63 +k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 482.04 5.56 359528 14 207.35 -1 -1 143276 -1 -1 2735 257 0 11 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/bgm.v/common 620272 257 32 36582 33970 1 19817 3035 63 63 3969 clb auto 52.84 251309 90.30 19.3036 -23980 -19.3036 76 390974 30 2.36641e+08 1.51758e+08 2.05973e+07 5189.55 89.24 370589 20 88889 400817 30289366 5434412 21.3768 -26583 -21.3768 0 0 2.57532e+07 6488.59 10.74 +k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 95.31 0.30 48456 5 38.85 -1 -1 59576 -1 -1 620 36 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/blob_merge.v/common 176832 36 100 14037 11284 1 3208 756 31 31 961 clb auto 12.41 44836 7.23 13.36 -2549.28 -13.36 62 73676 28 5.14688e+07 3.34143e+07 3.99881e+06 4161.10 29.18 66010 16 12659 59175 2926786 463902 15.1227 -2891.72 -15.1227 0 0 4.96813e+06 5169.75 1.41 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 5.17 0.38 40476 3 0.38 -1 -1 37932 -1 -1 92 142 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/boundtop.v/common 46576 142 192 1071 1141 1 560 426 14 14 196 clb auto 0.57 1699 0.66 2.91223 -445.314 -2.91223 38 3772 13 9.20055e+06 4.95825e+06 467348. 2384.43 1.60 3400 11 1170 1865 103186 29191 3.47632 -537.276 -3.47632 0 0 593372. 3027.41 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 1.98 0.04 8756 3 0.19 -1 -1 36248 -1 -1 65 99 1 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/ch_intrinsics.v/common 40116 99 130 363 493 1 251 295 12 12 144 clb auto 0.13 655 0.32 2.00545 -200.687 -2.00545 48 1472 12 5.66058e+06 4.05111e+06 394078. 2736.65 0.66 1317 10 610 789 58233 19844 2.37898 -234.796 -2.37898 0 0 503203. 3494.47 0.03 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 5.76 0.03 8352 6 0.13 -1 -1 33864 -1 -1 32 162 0 5 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/diffeq1.v/common 54380 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 0.30 4803 0.72 15.4874 -1172.24 -15.4874 56 10316 37 1.21132e+07 3.70461e+06 870502. 3400.40 3.38 9215 24 2857 4421 1787465 459623 17.4767 -1443.1 -17.4767 0 0 1.11200e+06 4343.75 0.31 +k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 7.13 0.03 7712 6 0.07 -1 -1 33388 -1 -1 21 66 0 7 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/diffeq2.v/common 55384 66 96 866 607 1 547 190 18 18 324 mult_36 auto 0.32 4781 0.60 12.0262 -722.877 -12.0262 50 10710 25 1.57076e+07 3.90377e+06 1.01955e+06 3146.77 4.84 9345 19 2973 5773 3034601 722732 13.351 -865.227 -13.351 0 0 1.35341e+06 4177.19 0.40 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 1160.83 3.99 207808 101 75.62 -1 -1 104260 -1 -1 2196 114 44 8 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU8PEEng.v/common 585572 114 102 38222 33863 1 17915 2464 57 57 3249 clb auto 63.62 227004 79.00 66.2215 -51789.1 -66.2215 90 345841 34 1.92089e+08 1.45633e+08 1.94366e+07 5982.34 901.38 318909 21 69380 266324 51230815 12331241 75.9848 -67101.2 -75.9848 0 0 2.47455e+07 7616.35 14.95 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 6471.18 30.56 733972 97 771.07 -1 -1 319308 -1 -1 7491 114 167 32 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU32PEEng.v/common 1986792 114 102 124854 111149 1 59091 7906 102 102 10404 clb auto 206.03 1055428 681.63 66.4782 -325013 -66.4782 128 1430836 25 6.36957e+08 5.07872e+08 8.68880e+07 8351.40 4604.52 1370132 22 215780 902172 301291627 84798612 75.0134 -457649 -75.0134 0 0 1.09718e+08 10545.7 95.27 +k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 4798.33 15.19 805844 24 2921.70 -1 -1 372832 -1 -1 7103 36 159 27 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/mcml.v/common 2376252 36 33 190959 166678 1 61855 7358 100 100 10000 clb auto 190.51 730601 884.90 41.4626 -268085 -41.4626 142 990852 21 6.13558e+08 4.80599e+08 9.13509e+07 9135.09 623.91 963389 21 225338 567871 203556148 58454685 44.1913 -324011 -44.1913 0 0 1.15789e+08 11578.9 68.97 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 36.05 0.58 72440 5 6.42 -1 -1 53068 -1 -1 461 506 44 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/mkDelayWorker32B.v/common 269332 506 553 3647 4145 1 3226 1564 50 50 2500 memory auto 3.33 13851 9.14 6.93554 -1612.33 -6.93554 36 20290 12 1.47946e+08 4.89577e+07 6.56144e+06 2624.58 11.01 19496 14 3173 3667 2881824 796676 7.79224 -1954.08 -7.79224 0 0 8.08089e+06 3232.35 0.81 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 10.14 0.09 15900 2 0.06 -1 -1 34248 -1 -1 29 311 15 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/mkPktMerge.v/common 69128 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.46 8154 1.41 4.03068 -4140.31 -4.03068 34 14954 18 4.25198e+07 9.78293e+06 1.87155e+06 2387.18 6.26 14097 14 2874 3274 2583359 768623 4.41754 -4940.27 -4.41754 0 0 2.30233e+06 2936.64 0.44 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 15.30 0.20 29124 4 1.56 -1 -1 39840 -1 -1 193 193 5 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/mkSMAdapter4B.v/common 78784 193 205 2926 2852 1 1459 596 20 20 400 memory auto 2.53 11452 2.13 4.8081 -2551.77 -4.8081 56 21383 25 2.07112e+07 1.31415e+07 1.41661e+06 3541.53 6.55 18075 16 5248 13314 1166188 273285 5.32122 -3024.85 -5.32122 0 0 1.80858e+06 4521.44 0.37 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 33.88 0.30 39032 8 4.21 -1 -1 43672 -1 -1 252 385 2 1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/or1200.v/common 122884 385 394 4676 4540 1 2422 1034 27 27 729 io auto 6.52 31294 5.24 8.24663 -9413.77 -8.24663 100 46141 21 3.93038e+07 1.50733e+07 4.55173e+06 6243.81 13.24 44152 18 9428 32811 3309145 629591 8.75121 -10459.3 -8.75121 0 0 5.74540e+06 7881.21 0.98 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 13.17 0.23 29400 3 0.98 -1 -1 40440 -1 -1 107 214 0 8 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/raygentop.v/common 72356 214 305 2964 2870 1 1438 634 19 19 361 io auto 2.06 10616 1.81 4.35964 -2534.95 -4.35964 58 22442 27 1.72706e+07 8.93466e+06 1.32779e+06 3678.09 5.56 18936 17 5472 12215 3185481 757535 4.72762 -2948.6 -4.72762 0 0 1.69263e+06 4688.74 0.55 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 231.57 0.56 35840 3 221.47 -1 -1 91388 -1 -1 156 38 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/sha.v/common 67532 38 36 2995 2744 1 1210 230 17 17 289 clb auto 1.72 11055 1.41 8.49849 -2422.16 -8.49849 70 16602 26 1.34605e+07 8.40746e+06 1.24100e+06 4294.11 2.12 15327 19 4211 11679 496185 92511 9.79579 -2831.4 -9.79579 0 0 1.56192e+06 5404.58 0.30 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.35 0.11 19268 15 0.58 -1 -1 35084 -1 -1 65 45 3 1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/spree.v/common 54728 45 32 1272 1229 1 833 146 14 14 196 memory auto 1.80 6931 0.75 9.72618 -6286.63 -9.72618 64 13122 18 9.20055e+06 5.54311e+06 762053. 3888.03 7.60 11660 12 3429 9153 1698005 461570 11.3354 -7496.94 -11.3354 0 0 953435. 4864.47 0.31 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 47.82 1.03 108580 5 8.14 -1 -1 71304 -1 -1 696 157 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision0.v/common 252128 157 197 23836 21789 1 6687 1050 33 33 1089 clb auto 7.00 41588 8.69 2.85337 -13155.3 -2.85337 56 62487 38 6.0475e+07 3.75104e+07 4.09277e+06 3758.28 13.21 57922 15 17790 26843 1185040 231899 3.47455 -15388.1 -3.47455 0 0 5.21984e+06 4793.24 1.29 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 121.41 0.90 91032 3 38.32 -1 -1 84732 -1 -1 678 115 0 40 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision1.v/common 288128 115 145 23136 19549 1 9677 978 40 40 1600 mult_36 auto 7.29 81172 10.80 5.11281 -21915.2 -5.11281 84 136336 50 9.16046e+07 5.23808e+07 8.77086e+06 5481.79 49.75 119753 15 32175 49344 23646761 4826817 5.52308 -25295.9 -5.52308 0 0 1.11533e+07 6970.83 4.27 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 416.17 1.23 138928 3 6.64 -1 -1 202328 -1 -1 1653 149 0 324 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision2.v/common 1269872 149 182 65737 42630 1 35961 2308 104 104 10816 mult_36 auto 22.97 364850 94.98 14.3209 -62260.7 -14.3209 78 500935 50 6.67561e+08 2.17385e+08 5.81687e+07 5378.03 246.95 475565 19 125236 147024 45704114 9196995 15.7318 -74682.7 -15.7318 0 0 7.36102e+07 6805.68 12.03 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.37 0.04 9192 5 0.09 -1 -1 33300 -1 -1 14 11 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off/run023/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31932 11 30 313 321 2 117 55 7 7 49 clb auto 0.22 416 0.09 2.2748 -158.123 -2.2748 30 1085 28 1.07788e+06 754516 77114.5 1573.76 0.13 745 23 517 993 39807 13979 2.5423 -185.389 -2.5423 0 0 95414.1 1947.23 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/config.txt new file mode 100644 index 00000000000..ae848d08efb --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/config.txt @@ -0,0 +1,60 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif + +# Path to directory of architectures to use +archs_dir=arch/titan + +# Add circuits to list to sweep +# Note that the circuits are roughly sorted so that some small +# circuits run first (to detect early failures), followed by larger +# circuits (so they do not start last) + +#Large benchmarks +circuit_list_add=directrf_stratixiv_arch_timing.blif +circuit_list_add=bitcoin_miner_stratixiv_arch_timing.blif +circuit_list_add=LU230_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_chip2_stratixiv_arch_timing.blif +circuit_list_add=LU_Network_stratixiv_arch_timing.blif + +#Small benchmarks +circuit_list_add=neuron_stratixiv_arch_timing.blif +circuit_list_add=sparcT1_core_stratixiv_arch_timing.blif +circuit_list_add=stereo_vision_stratixiv_arch_timing.blif +circuit_list_add=cholesky_mc_stratixiv_arch_timing.blif + +#Mixed order of large and small +circuit_list_add=gsm_switch_stratixiv_arch_timing.blif +circuit_list_add=mes_noc_stratixiv_arch_timing.blif +circuit_list_add=dart_stratixiv_arch_timing.blif +circuit_list_add=denoise_stratixiv_arch_timing.blif +circuit_list_add=sparcT2_core_stratixiv_arch_timing.blif +circuit_list_add=cholesky_bdti_stratixiv_arch_timing.blif +circuit_list_add=minres_stratixiv_arch_timing.blif +circuit_list_add=stap_qrd_stratixiv_arch_timing.blif +circuit_list_add=openCV_stratixiv_arch_timing.blif +circuit_list_add=bitonic_mesh_stratixiv_arch_timing.blif +circuit_list_add=segmentation_stratixiv_arch_timing.blif +circuit_list_add=SLAM_spheric_stratixiv_arch_timing.blif +circuit_list_add=des90_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +#The Titan benchmarks are run at a fixed channel width of 300 to simulate a Stratix IV-like routing architecture +#A large number of routing iterations is set to ensure the router doesn't give up to easily on the larger benchmarks +#To be more run-time comparable to commercial tools like Quartus, we run with higher placer effort (inner_num=2) and lower astar_fac (1.0) +#Set a 48hr timeout so they don't run forever +script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map -timeout 172800 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/golden_results.txt new file mode 100644 index 00000000000..fd988da6465 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_titan/config/golden_results.txt @@ -0,0 +1,24 @@ +arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time +stratixiv_arch.timing.xml gaussianblur_stratixiv_arch_timing.blif common 56012.57 558 104911 2 12 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/gaussianblur_stratixiv_arch_timing.blif/common 33616388 166 392 1872320 1859014 1 1211091 105483 399 296 118104 LAB auto 7491.89 22269288 45222.81 860.262 -8.02815e+07 -860.262 31133826 3816844 20128152 16444723514 1330151422 0 0 2.38992e+09 20235.7 23 857.441 -1.15078e+08 -857.441 0 0 2607.86 +stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 15390.49 319 61450 240 2535 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/directrf_stratixiv_arch_timing.blif/common 20578488 62 257 1374456 930989 2 679939 64544 317 235 74495 M9K auto 899.20 12610547 12944.78 11.1291 -2.77017e+06 -11.1291 14352742 1921135 3468780 6114643355 877213849 0 0 1.42890e+09 19181.1 14 13.014 -3.72054e+06 -13.014 0 0 1102.89 +stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 15372.62 385 32463 0 1331 0 1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/bitcoin_miner_stratixiv_arch_timing.blif/common 14494440 353 32 1446409 1087537 2 848822 34180 225 167 37575 LAB auto 684.48 10111344 13568.44 7.45251 -1.57126e+06 -7.45251 11475946 2666194 3937911 4524252328 679329544 0 0 7.28440e+08 19386.3 49 7.70614 -2.07364e+06 -7.70614 0 0 846.84 +stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 7715.06 373 16585 116 5040 16 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/LU230_stratixiv_arch_timing.blif/common 20450460 178 195 663067 568001 2 413013 22130 430 319 137170 M9K auto 933.33 14322237 5636.60 27.6725 -4.5081e+06 -27.6725 16434901 1132225 2273789 3469699084 582895956 0 0 2.85688e+09 20827.3 16 28.6549 -7.69099e+06 -28.6549 0 0 650.63 +stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 25946.50 1891 33495 3 506 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/sparcT1_chip2_stratixiv_arch_timing.blif/common 13618168 815 1076 764693 760412 1423 418391 35895 279 207 57753 io auto 1486.56 6487121 7527.25 23.3281 -6.08248e+06 -23.3281 8004883 1203064 3982684 3196821530 388552600 0 0 1.11162e+09 19247.9 22 24.2434 -6.9249e+06 -24.2434 0 0 619.78 +stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 6988.94 406 31055 112 1175 0 2 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/LU_Network_stratixiv_arch_timing.blif/common 13024780 85 185 721554 630079 28 404375 32750 220 163 35860 LAB auto 735.21 4597990 5693.93 6.6685 -1.81212e+06 -6.6685 5809928 885967 1875899 1940464885 319870307 0 0 6.95754e+08 19402.0 19 7.30405 -2.1603e+06 -7.30405 0 0 316.91 +stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 507.91 77 3125 89 136 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 3339548 42 35 119888 86875 1 51266 3427 129 96 12384 DSP auto 79.54 586789 330.73 7.46763 -213859 -7.46763 761976 106796 178227 276123877 56632068 0 0 2.43110e+08 19631.0 14 8.09718 -257888 -8.09718 0 0 39.42 +stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 764.20 310 3926 1 128 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/sparcT1_core_stratixiv_arch_timing.blif/common 2330200 173 137 92814 91975 1 57408 4365 82 61 5002 LAB auto 260.63 931429 394.63 7.70952 -511997 -7.70952 1255594 220149 783644 646029046 84514392 0 0 9.74073e+07 19473.7 16 8.44632 -604741 -8.44632 0 0 69.90 +stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 480.27 506 3238 76 113 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/stereo_vision_stratixiv_arch_timing.blif/common 2794436 172 334 127090 94090 3 61780 3933 129 96 12384 DSP auto 64.68 568636 332.40 8.15241 -148103 -8.15241 649504 130476 194053 206707491 30147865 0 0 2.43110e+08 19631.0 14 8.62596 -176693 -8.62596 0 0 26.91 +stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 694.15 262 4746 59 444 16 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/cholesky_mc_stratixiv_arch_timing.blif/common 3560388 111 151 140214 108592 1 66048 5527 125 93 11625 M9K auto 106.53 802239 427.01 6.70278 -416520 -6.70278 1152988 153904 340803 627381186 140125446 0 0 2.28063e+08 19618.3 19 7.4038 -521616 -7.4038 0 0 97.63 +stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 4123.78 136 21477 0 1848 0 1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/gsm_switch_stratixiv_arch_timing.blif/common 10695588 100 36 504627 490068 5 201500 23462 255 189 48195 M9K auto 668.35 4158388 3006.65 9.5929 -2.5031e+06 -9.5929 5299580 492372 1498935 1420350756 203928479 0 0 9.29962e+08 19295.8 14 10.1094 -3.17437e+06 -10.1094 0 0 220.20 +stratixiv_arch.timing.xml mes_noc_stratixiv_arch_timing.blif common 7149.19 5 23635 0 800 0 8 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/mes_noc_stratixiv_arch_timing.blif/common 10116672 3 2 577696 547568 17 347176 24448 193 143 27599 LAB auto 1319.08 3723316 5201.84 12.6589 -4.13974e+06 -12.6589 5041101 855666 2556569 2516225131 268678125 0 0 5.39298e+08 19540.5 18 13.6826 -4.89561e+06 -13.6826 0 0 434.63 +stratixiv_arch.timing.xml dart_stratixiv_arch_timing.blif common 1485.16 69 7014 0 530 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/dart_stratixiv_arch_timing.blif/common 4463580 23 46 223304 202401 1 132117 7613 138 102 14076 M9K auto 353.41 1968046 931.66 13.1025 -1.55624e+06 -13.1025 2373096 366782 927818 921011305 118409405 0 0 2.76641e+08 19653.4 15 14.0867 -1.86536e+06 -14.0867 0 0 115.25 +stratixiv_arch.timing.xml denoise_stratixiv_arch_timing.blif common 4286.81 852 14047 24 359 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/denoise_stratixiv_arch_timing.blif/common 6392636 264 588 355537 274786 1 219013 15282 150 111 16650 LAB auto 355.53 2770688 3591.58 867.795 -1.07057e+06 -867.795 3338520 747685 2229688 1963358632 240028160 0 0 3.27533e+08 19671.7 24 863.179 -1.29478e+06 -863.179 0 0 218.79 +stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 3739.28 451 14737 0 260 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/sparcT2_core_stratixiv_arch_timing.blif/common 5674256 239 212 302755 300220 1 185030 15448 153 113 17289 LAB auto 642.87 3638916 2727.52 10.3998 -1.02342e+06 -10.3998 4660731 664149 2588723 2219204545 279767155 0 0 3.40245e+08 19679.8 18 11.0031 -1.33667e+06 -11.0031 0 0 258.43 +stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 1781.92 162 9699 132 600 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/cholesky_bdti_stratixiv_arch_timing.blif/common 6441796 94 68 331744 255478 1 156337 10593 169 125 21125 DSP auto 255.34 1835231 1184.86 8.49239 -1.0141e+06 -8.49239 2533756 374579 808365 1516372378 306058858 0 0 4.15904e+08 19687.8 19 8.76751 -1.33995e+06 -8.76751 0 0 228.35 +stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 1985.93 229 7832 78 1459 0 1 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/minres_stratixiv_arch_timing.blif/common 7811308 129 100 316623 257480 3 183853 9599 225 167 37575 M9K auto 338.90 2123707 1335.02 7.33966 -732493 -7.33966 2871463 413630 831392 1026886265 180806641 0 0 7.28440e+08 19386.3 16 9.09684 -944812 -9.09684 0 0 146.58 +stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 2278.81 150 15893 75 553 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/stap_qrd_stratixiv_arch_timing.blif/common 5496912 68 82 284051 234177 1 143550 16671 158 117 18486 LAB auto 242.68 2174334 1782.30 6.40055 -840743 -6.40055 2735109 331264 836736 1120310702 186275140 0 0 3.64007e+08 19691.0 14 7.00779 -1.10637e+06 -7.00779 0 0 151.08 +stratixiv_arch.timing.xml openCV_stratixiv_arch_timing.blif common 1883.27 208 7087 213 785 40 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/openCV_stratixiv_arch_timing.blif/common 7092760 106 102 279132 212552 1 169051 8333 209 155 32395 DSP auto 300.16 2709397 1227.23 10.2274 -1.03646e+06 -10.2274 3445227 465395 1042301 1461555086 265863722 0 0 6.29758e+08 19440.0 13 11.4 -1.33573e+06 -11.4 0 0 216.53 +stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 2591.86 119 7206 85 1664 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/bitonic_mesh_stratixiv_arch_timing.blif/common 8304028 87 32 233978 190746 1 147040 9074 242 179 43318 M9K auto 454.64 3750483 1669.58 13.1611 -1.94904e+06 -13.1611 4890603 507038 1636751 1959026319 349354600 0 0 8.37664e+08 19337.6 16 14.4378 -2.31692e+06 -14.4378 0 0 292.77 +stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 1558.36 441 6925 15 481 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/segmentation_stratixiv_arch_timing.blif/common 3983972 72 369 178312 137832 1 108441 7862 136 101 13736 M9K auto 172.34 1421758 1191.09 865.067 -477850 -865.067 1771129 375066 1139340 1043805644 129786978 0 0 2.69876e+08 19647.3 24 860.66 -621222 -860.66 0 0 115.83 +stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 1000.06 479 5394 37 0 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/SLAM_spheric_stratixiv_arch_timing.blif/common 3027768 323 156 140638 111354 1 76831 5910 95 70 6650 LAB auto 171.45 1186527 682.64 80.439 -353722 -80.439 1504973 243650 816054 860319174 127001166 0 0 1.29896e+08 19533.2 15 79.3818 -394291 -79.3818 0 0 96.47 +stratixiv_arch.timing.xml des90_stratixiv_arch_timing.blif common 1273.20 117 4186 44 860 0 0 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vtr_reg_titan/run022/stratixiv_arch.timing.xml/des90_stratixiv_arch_timing.blif/common 4789208 85 32 138853 110549 1 88035 5207 171 127 21717 M9K auto 249.92 1677715 785.49 11.6774 -998647 -11.6774 2297838 290790 889357 989134409 176518163 0 0 4.27406e+08 19680.7 15 12.6718 -1.15089e+06 -12.6718 0 0 143.75 From c09dbe1f0d10e7d0cbed605d18e21b27921ed852 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 3 Mar 2020 11:51:08 -0800 Subject: [PATCH 2/2] Add monitor loop to enable visiblity into long running test. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- .github/kokoro/steps/vtr-test.sh | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/.github/kokoro/steps/vtr-test.sh b/.github/kokoro/steps/vtr-test.sh index 13fcf89d94c..ce39d8b4a61 100644 --- a/.github/kokoro/steps/vtr-test.sh +++ b/.github/kokoro/steps/vtr-test.sh @@ -24,5 +24,18 @@ echo $PWD pwd pwd -L pwd -P + +( + while : + do + date + uptime + free -h + sleep 300 + done +) & +MONITOR=$! + export VPR_NUM_WORKERS=1 ./run_reg_test.pl $VTR_TEST -show_failures -j$NUM_CORES +kill $MONITOR