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When running VPR with the Z1000 architecture and flat routing enabled, I encountered the following issue:
Circuit successfully routed with a channel width factor of 100.
# Synchronize the packed netlist to routing optimization
/home/hosamue3/vtr-verilog-to-routing/vpr/src/base/clustered_netlist.cpp:25 block_pb: Assertion 'valid_block_id(id)' failed.
./vtr.sh: line 12: 2497610 Aborted (core dumped) $VTR_ROOT/vpr/vpr $VTR_ROOT/vtr_flow/arch/zeroasic/z1000/z1000.xml $VTR_ROOT/vtr_flow/benchmarks/blif/4/bw.blif --flat_routing on --route_chan_width 100 --device z1000 --clock_modeling route --constant_net_method route --const_gen_inference none --sweep_dangling_primary_ios off --sweep_dangling_nets off --allow_dangling_combinational_nodes on --sweep_constant_primary_outputs off --sweep_dangling_blocks off -j12 --read_rr_graph $VTR_ROOT/vtr_flow/arch/zeroasic/z1000/z1000_rr_graph.xml
It seems that the circuit routes correctly, but afterwards, a block id assertion is triggered. Similarly, when I turned on graphics to visualize intra-cluster routing, I ran into the error:
Circuit successfully routed with a channel width factor of 100.
/home/hosamue3/vtr-verilog-to-routing/vpr/src/util/vpr_utils.cpp:1771 get_rr_node_cluster_blk_id_pb_graph_pin: Assertion 'blk_id != ClusterBlockId::INVALID()' failed.
./gui.sh: line 14: 2498796 Aborted (core dumped) $VTR_ROOT/vpr/vpr $VTR_ROOT/vtr_flow/arch/zeroasic/z1000/z1000.xml $VTR_ROOT/vtr_flow/benchmarks/blif/4/bw.blif --disp on --analysis --flat_routing on --route_chan_width 100 --device z1000 --clock_modeling route --constant_net_method route --const_gen_inference none --sweep_dangling_primary_ios off --sweep_dangling_nets off --allow_dangling_combinational_nodes on --sweep_constant_primary_outputs off --sweep_dangling_blocks off -j12 --read_rr_graph $VTR_ROOT/vtr_flow/arch/zeroasic/z1000/z1000_rr_graph.xml
Alex suggested that this issue might be caused by the architecture’s perimeter of empty tiles.
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