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Description
Latest automated weekly test failed. Documenting the issues below:
- vtr_reg_nightly_test1:
- One failure
- Small circuit (mult119.v) with <100 blocks
- Minimum channel width changed to 42 (Golden result = 24)
- Everything else stayed more or less the same
- Same number of clustered blocks
- Placement went for way longer and never entered the second stage
- vtr_reg_nightly_test3:
- One failure
- Small circuit (sha.v) with ~200 blocks
- Minimum channel width changed to 68 (Golden result = 52)
- CPD actually improved by a negligible amount (10.757ns vs 10.9834ns)
- vtr_reg_nightly_test4:
- One failure
- Medium/large circuit (titan minres) with ~14k blocks
- TWL actually improved by a negligible amount (1633788 vs 1655917)
- CPD changed from 4.851ns to 6.367ns
- Circuit has 4 clock domains, other 3 were either better or not noticably worse
The failures started from bc4a791.
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