Set up yosys-slang to be used as a frontend for Yosys

Author: loglav03

vtr_flow/misc/yosys/synthesis.tcl

@@ -1,6 +1,7 @@
 yosys -import
 
 plugin -i parmys
+plugin -i slang
 yosys -import
 
 read_verilog -nomem2reg +/parmys/vtr_primitives.v
@@ -24,17 +25,20 @@ if {[catch {set synlig $::env(synlig_exe_path)} err]} {
 # output file: ZZZ
 
 parmys_arch -a QQQ
+if {$env(PARSER) == "slang" } {
+	puts "Using yosys-slang read_slang command"
+	read_slang XXX
+}
 
-if {$env(PARSER) == "surelog" } {
-	puts "Using Synlig read_uhdm command"
-	
-	exec $synlig -p "read_uhdm XXX"
+#if {$env(PARSER) == "surelog" } {
+#	puts "Using Synlig read_uhdm command"
+#	exec $synlig -p "read_uhdm XXX"
 
-} elseif {$env(PARSER) == "system-verilog" } {
-	puts "Using Synlig read_systemverilog "
-	exec $synlig -p "read_systemverilog XXX"
-	
-} elseif {$env(PARSER) == "default" } {
+#} elseif {$env(PARSER) == "system-verilog" } {
+#	puts "Using Synlig read_systemverilog "
+#	exec $synlig -p "read_systemverilog XXX"
+#	} 
+elseif {$env(PARSER) == "default" } {
 	puts "Using Yosys read_verilog command"
 	read_verilog -sv -nolatches XXX
 } else {
@@ -74,13 +78,17 @@ techmap -map +/parmys/aldffe2dff.v
 opt -full
 
 # Separate options for Parmys execution (Verilog or SystemVerilog)
-if {$env(PARSER) == "default"} {
+if {$env(PARSER) == "default" || $env(PARSER) == "slang"} {
     # For Verilog, use -nopass for a simpler, faster flow
     parmys -a QQQ -nopass -c CCC YYY
-} elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} {
-    # For Synlig SystemVerilog, run additional passes to handle complexity
-    parmys -a QQQ -c CCC YYY
-}
+} #elseif {$env(PARSER) == "slang"} {
+    # For Slang, run additional passes to handle complexity
+#    parmys -a QQQ -c CCC YYY
+#}
+#elseif {$env(PARSER) == "system-verilog" || $env(PARSER) == "surelog"} {
+#    # For Synlig SystemVerilog, run additional passes to handle complexity
+#    parmys -a QQQ -c CCC YYY
+#}
 
 opt -full
 
@@ -95,4 +103,4 @@ stat
 
 hierarchy -check -auto-top -purge_lib
 
-write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
+write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

vtr_flow/scripts/python_libs/vtr/parmys/parmys.py

@@ -22,7 +22,8 @@
     ".ys": "RTLIL",
 }
 
-YOSYS_PARSERS = ["default", "surelog", "system-verilog"]
+#YOSYS_PARSERS = ["default", "surelog", "system-verilog"]
+YOSYS_PARSERS = ["default", "slang"]
 
 
 def create_circuits_list(main_circuit, include_files):
@@ -246,7 +247,7 @@ def run(
         del parmys_args["parser"]
     else:
         raise vtr.VtrError(
-            "Invalid parser is specified for Yosys, available parsers are [{}]".format(
+            parmys_args["parser"] + "Invalid parser is specified for Yosys, available parsers are [{}]".format(
                 " ".join(str(x) for x in YOSYS_PARSERS)
             )
         )

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt

@@ -35,4 +35,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt

@@ -32,4 +32,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt

@@ -34,4 +34,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 -parser system-verilog
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang