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[libs][arch] fix sb_type sb_sub_type name
1 parent 2b101ef commit edd3617

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7 files changed

+39
-39
lines changed

7 files changed

+39
-39
lines changed

libs/libarchfpga/src/arch_util.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ void free_type_descriptors(std::vector<t_logical_block_type>& type_descriptors)
201201
}
202202

203203
static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_descriptors) {
204-
for (auto& type : type_descriptors) {
204+
for (t_logical_block_type& type : type_descriptors) {
205205
if (type.pb_type) {
206206
if (type.pb_graph_head) {
207207
free_pb_graph(type.pb_graph_head);
@@ -428,8 +428,8 @@ t_logical_block_type get_empty_logical_type(const char* name /*=EMPTY_BLOCK_NAME
428428
std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type) {
429429
std::unordered_set<t_logical_block_type_ptr> equivalent_sites;
430430

431-
for (auto& sub_tile : type->sub_tiles) {
432-
for (auto logical_block : sub_tile.equivalent_sites) {
431+
for (const t_sub_tile& sub_tile : type->sub_tiles) {
432+
for (t_logical_block_type_ptr logical_block : sub_tile.equivalent_sites) {
433433
equivalent_sites.insert(logical_block);
434434
}
435435
}
@@ -841,7 +841,7 @@ e_power_estimation_method power_method_inherited(e_power_estimation_method paren
841841

842842
void SyncModelsPbTypes(t_arch* arch,
843843
const std::vector<t_logical_block_type>& Types) {
844-
for (auto& Type : Types) {
844+
for (const t_logical_block_type& Type : Types) {
845845
if (Type.pb_type != nullptr) {
846846
SyncModelsPbTypes_rec(arch, Type.pb_type);
847847
}
@@ -977,7 +977,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation,
977977
}
978978

979979
const t_segment_inf* find_segment(const t_arch* arch, std::string_view name) {
980-
for (const auto& segment : arch->Segments) {
980+
for (const t_segment_inf& segment : arch->Segments) {
981981
if (segment.name == name) {
982982
return &segment;
983983
}
@@ -1038,7 +1038,7 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po
10381038
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
10391039
InstPort annot_in(annotation.input_pins);
10401040
if (annot_in.port_name() == port->name) {
1041-
for (const auto& [key, val] : annotation.annotation_entries) {
1041+
for (const auto& [key, _] : annotation.annotation_entries) {
10421042
if (key == annot_type) {
10431043
return true;
10441044
}
@@ -1051,12 +1051,12 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po
10511051

10521052
bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port) {
10531053
for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
1054-
for (const auto& annot_in_str : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
1054+
for (const std::string& annot_in_str : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
10551055
InstPort in_pins(annot_in_str);
1056-
for (const auto& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
1056+
for (const std::string& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
10571057
InstPort out_pins(annot_out_str);
10581058
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
1059-
for (const auto& [key, val] : annotation.annotation_entries) {
1059+
for (const auto& [key, _] : annotation.annotation_entries) {
10601060
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
10611061
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
10621062
return true;
@@ -1072,7 +1072,7 @@ bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_
10721072

10731073
void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTileTypes,
10741074
std::vector<t_logical_block_type>& LogicalBlockTypes) {
1075-
for (auto& physical_tile : PhysicalTileTypes) {
1075+
for (t_physical_tile_type& physical_tile : PhysicalTileTypes) {
10761076
if (physical_tile.index == EMPTY_TYPE_INDEX) continue;
10771077

10781078
auto eq_sites_set = get_equivalent_sites_set(&physical_tile);
@@ -1093,7 +1093,7 @@ void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTile
10931093
std::sort(equivalent_sites.begin(), equivalent_sites.end(), criteria);
10941094

10951095
for (t_logical_block_type& logical_block : LogicalBlockTypes) {
1096-
for (auto site : equivalent_sites) {
1096+
for (t_logical_block_type_ptr site : equivalent_sites) {
10971097
if (logical_block.name == site->pb_type->name) {
10981098
logical_block.equivalent_tiles.push_back(&physical_tile);
10991099
break;

libs/libarchfpga/src/echo_arch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
184184
break;
185185
}
186186

187-
switch (arch->SBType) {
187+
switch (arch->sb_type) {
188188
case (WILTON):
189189
fprintf(Echo, "\tSwitch Block: type wilton fs %d\n", arch->Fs);
190190
break;

libs/libarchfpga/src/parse_switchblocks.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -200,8 +200,8 @@ t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiu
200200
t_wire_switchpoints wire_switchpoints;
201201
wire_switchpoints.segment_name = get_attribute(node, "type", loc_data).value();
202202

203-
auto points_str = get_attribute(node, "switchpoint", loc_data).value();
204-
for (const auto& point_str : vtr::StringToken(points_str).split(",")) {
203+
std::string points_str = get_attribute(node, "switchpoint", loc_data).value();
204+
for (const std::string& point_str : vtr::StringToken(points_str).split(",")) {
205205
int switchpoint = vtr::atoi(point_str);
206206
wire_switchpoints.switchpoints.push_back(switchpoint);
207207
}
@@ -229,13 +229,13 @@ static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchp
229229
/* parses the wire types specified in the comma-separated 'ch' char array into the vector wire_points_vec.
230230
* Spaces are trimmed off */
231231
static void parse_comma_separated_wire_types(const char* ch, std::vector<t_wire_switchpoints>& wire_switchpoints) {
232-
auto types = vtr::StringToken(ch).split(",");
232+
std::vector<std::string> types = vtr::StringToken(ch).split(",");
233233

234234
if (types.empty()) {
235235
archfpga_throw(__FILE__, __LINE__, "parse_comma_separated_wire_types: found empty wireconn wire type entry\n");
236236
}
237237

238-
for (const auto& type : types) {
238+
for (const std::string& type : types) {
239239
t_wire_switchpoints wsp;
240240
wsp.segment_name = type;
241241

@@ -245,15 +245,15 @@ static void parse_comma_separated_wire_types(const char* ch, std::vector<t_wire_
245245

246246
/* parses the wirepoints specified in the comma-separated 'ch' char array into the vector wire_points_vec */
247247
static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire_switchpoints>& wire_switchpoints) {
248-
auto points = vtr::StringToken(ch).split(",");
248+
std::vector<std::string> points = vtr::StringToken(ch).split(",");
249249
if (points.empty()) {
250250
archfpga_throw(__FILE__, __LINE__, "parse_comma_separated_wire_points: found empty wireconn wire point entry\n");
251251
}
252252

253-
for (const auto& point_str : points) {
253+
for (const std::string& point_str : points) {
254254
int point = vtr::atoi(point_str);
255255

256-
for (auto& wire_switchpoint : wire_switchpoints) {
256+
for (t_wire_switchpoints& wire_switchpoint : wire_switchpoints) {
257257
wire_switchpoint.switchpoints.push_back(point);
258258
}
259259
}
@@ -404,7 +404,7 @@ void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch) {
404404
}
405405

406406
/* check that specified wires exist */
407-
for (const auto& wireconn : sb->wireconns) {
407+
for (const t_wireconn_inf& wireconn : sb->wireconns) {
408408
check_wireconn(arch, wireconn);
409409
}
410410

@@ -464,7 +464,7 @@ static void check_bidir_switchblock(const t_permutation_map* permutation_map) {
464464

465465
static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn) {
466466
for (const t_wire_switchpoints& wire_switchpoints : wireconn.from_switchpoint_set) {
467-
auto seg_name = wire_switchpoints.segment_name;
467+
std::string seg_name = wire_switchpoints.segment_name;
468468

469469
//Make sure the segment exists
470470
const t_segment_inf* seg_info = find_segment(arch, seg_name);
@@ -485,7 +485,7 @@ static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn) {
485485
}
486486

487487
for (const t_wire_switchpoints& wire_switchpoints : wireconn.to_switchpoint_set) {
488-
auto seg_name = wire_switchpoints.segment_name;
488+
std::string seg_name = wire_switchpoints.segment_name;
489489

490490
//Make sure the segment exists
491491
const t_segment_inf* seg_info = find_segment(arch, seg_name);

libs/libarchfpga/src/physical_types.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2282,10 +2282,10 @@ struct t_noc_inf {
22822282
std::string noc_router_tile_name;
22832283
};
22842284

2285-
/* Detailed routing architecture */
2285+
// Detailed routing architecture
22862286
struct t_arch {
2287-
/** Stores unique strings used as key and values in <metadata> tags,
2288-
* i.e. implements a flyweight pattern to save memory.*/
2287+
/// Stores unique strings used as key and values in <metadata> tags,
2288+
/// i.e. implements a flyweight pattern to save memory.
22892289
mutable vtr::string_internment strings;
22902290
std::vector<vtr::interned_string> interned_strings;
22912291

@@ -2322,8 +2322,8 @@ struct t_arch {
23222322
// End of tileable architecture options
23232323

23242324
t_chan_width_dist Chans;
2325-
enum e_switch_block_type SBType;
2326-
enum e_switch_block_type SBSubType;
2325+
enum e_switch_block_type sb_type;
2326+
enum e_switch_block_type sb_sub_type;
23272327
std::vector<t_switchblock_inf> switchblocks;
23282328
float R_minW_nmos;
23292329
float R_minW_pmos;

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2327,7 +2327,7 @@ struct ArchReader {
23272327
arch_->Chans.chan_y_dist.xpeak = 0;
23282328
arch_->Chans.chan_y_dist.dc = 0;
23292329
arch_->ipin_cblock_switch_name.push_back(std::string("generic"));
2330-
arch_->SBType = WILTON;
2330+
arch_->sb_type = WILTON;
23312331
arch_->Fs = 3;
23322332
default_fc_.specified = true;
23332333
default_fc_.in_value_type = e_fc_value_type::FRACTIONAL;

libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -451,7 +451,7 @@ void xml_read_arch(const char* ArchFile,
451451
arch->switches = process_switches(Next, timing_enabled, loc_data);
452452

453453
/* Process switchblocks. This depends on switches */
454-
bool switchblocklist_required = (arch->SBType == CUSTOM); //require this section only if custom switchblocks are used
454+
bool switchblocklist_required = (arch->sb_type == CUSTOM); //require this section only if custom switchblocks are used
455455
SWITCHBLOCKLIST_REQD = BoolToReqOpt(switchblocklist_required);
456456

457457
/* Process segments. This depends on switches */
@@ -2923,13 +2923,13 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
29232923
Prop = get_attribute(Cur, "type", loc_data).value();
29242924
/* Parse attribute 'type', representing the major connectivity pattern for switch blocks */
29252925
if (strcmp(Prop, "wilton") == 0) {
2926-
arch->SBType = WILTON;
2926+
arch->sb_type = WILTON;
29272927
} else if (strcmp(Prop, "universal") == 0) {
2928-
arch->SBType = UNIVERSAL;
2928+
arch->sb_type = UNIVERSAL;
29292929
} else if (strcmp(Prop, "subset") == 0) {
2930-
arch->SBType = SUBSET;
2930+
arch->sb_type = SUBSET;
29312931
} else if (strcmp(Prop, "custom") == 0) {
2932-
arch->SBType = CUSTOM;
2932+
arch->sb_type = CUSTOM;
29332933
custom_switch_block = true;
29342934
} else {
29352935
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
@@ -2944,17 +2944,17 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
29442944
std::string sub_type_str = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string("");
29452945
if (!sub_type_str.empty()) {
29462946
if (sub_type_str == std::string("wilton")) {
2947-
arch->SBSubType = WILTON;
2947+
arch->sb_sub_type = WILTON;
29482948
} else if (sub_type_str == std::string("universal")) {
2949-
arch->SBSubType = UNIVERSAL;
2949+
arch->sb_sub_type = UNIVERSAL;
29502950
} else if (sub_type_str == std::string("subset")) {
2951-
arch->SBSubType = SUBSET;
2951+
arch->sb_sub_type = SUBSET;
29522952
} else {
29532953
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
29542954
"Unknown property %s for switch block subtype x\n", sub_type_str.c_str());
29552955
}
29562956
} else {
2957-
arch->SBSubType = arch->SBType;
2957+
arch->sb_sub_type = arch->sb_type;
29582958
}
29592959

29602960
ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block);

vpr/src/base/setup_vpr.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -427,8 +427,8 @@ static void setup_switches(const t_arch& Arch,
427427
*/
428428
static void setup_routing_arch(const t_arch& Arch,
429429
t_det_routing_arch& RoutingArch) {
430-
RoutingArch.switch_block_type = Arch.SBType;
431-
RoutingArch.switch_block_subtype = Arch.SBSubType;
430+
RoutingArch.switch_block_type = Arch.sb_type;
431+
RoutingArch.switch_block_subtype = Arch.sb_sub_type;
432432
RoutingArch.R_minW_nmos = Arch.R_minW_nmos;
433433
RoutingArch.R_minW_pmos = Arch.R_minW_pmos;
434434
RoutingArch.Fs = Arch.Fs;

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