[libs][arch] fix sb_type sb_sub_type name

Author: amin1377

libs/libarchfpga/src/arch_util.cpp

@@ -201,7 +201,7 @@ void free_type_descriptors(std::vector<t_logical_block_type>& type_descriptors)
 }
 
 static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_descriptors) {
-    for (auto& type : type_descriptors) {
+    for (t_logical_block_type& type : type_descriptors) {
         if (type.pb_type) {
             if (type.pb_graph_head) {
                 free_pb_graph(type.pb_graph_head);
@@ -428,8 +428,8 @@ t_logical_block_type get_empty_logical_type(const char* name /*=EMPTY_BLOCK_NAME
 std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type) {
     std::unordered_set<t_logical_block_type_ptr> equivalent_sites;
 
-    for (auto& sub_tile : type->sub_tiles) {
-        for (auto logical_block : sub_tile.equivalent_sites) {
+    for (const t_sub_tile& sub_tile : type->sub_tiles) {
+        for (t_logical_block_type_ptr logical_block : sub_tile.equivalent_sites) {
             equivalent_sites.insert(logical_block);
         }
     }
@@ -841,7 +841,7 @@ e_power_estimation_method power_method_inherited(e_power_estimation_method paren
 
 void SyncModelsPbTypes(t_arch* arch,
                        const std::vector<t_logical_block_type>& Types) {
-    for (auto& Type : Types) {
+    for (const t_logical_block_type& Type : Types) {
         if (Type.pb_type != nullptr) {
             SyncModelsPbTypes_rec(arch, Type.pb_type);
         }
@@ -977,7 +977,7 @@ void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation,
 }
 
 const t_segment_inf* find_segment(const t_arch* arch, std::string_view name) {
-    for (const auto& segment : arch->Segments) {
+    for (const t_segment_inf& segment : arch->Segments) {
         if (segment.name == name) {
             return &segment;
         }
@@ -1038,7 +1038,7 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po
     for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
         InstPort annot_in(annotation.input_pins);
         if (annot_in.port_name() == port->name) {
-            for (const auto& [key, val] : annotation.annotation_entries) {
+            for (const auto& [key, _] : annotation.annotation_entries) {
                 if (key == annot_type) {
                     return true;
                 }
@@ -1051,12 +1051,12 @@ bool has_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* po
 
 bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_port, std::string_view out_port) {
     for (const t_pin_to_pin_annotation& annotation : pb_type->annotations) {
-        for (const auto& annot_in_str : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
+        for (const std::string& annot_in_str : vtr::StringToken(annotation.input_pins).split(" \t\n")) {
             InstPort in_pins(annot_in_str);
-            for (const auto& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
+            for (const std::string& annot_out_str : vtr::StringToken(annotation.output_pins).split(" \t\n")) {
                 InstPort out_pins(annot_out_str);
                 if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
-                    for (const auto& [key, val] : annotation.annotation_entries) {
+                    for (const auto& [key, _] : annotation.annotation_entries) {
                         if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
                             || key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
                             return true;
@@ -1072,7 +1072,7 @@ bool has_combinational_annotation(const t_pb_type* pb_type, std::string_view in_
 
 void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTileTypes,
                                  std::vector<t_logical_block_type>& LogicalBlockTypes) {
-    for (auto& physical_tile : PhysicalTileTypes) {
+    for (t_physical_tile_type& physical_tile : PhysicalTileTypes) {
         if (physical_tile.index == EMPTY_TYPE_INDEX) continue;
 
         auto eq_sites_set = get_equivalent_sites_set(&physical_tile);
@@ -1093,7 +1093,7 @@ void link_physical_logical_types(std::vector<t_physical_tile_type>& PhysicalTile
         std::sort(equivalent_sites.begin(), equivalent_sites.end(), criteria);
 
         for (t_logical_block_type& logical_block : LogicalBlockTypes) {
-            for (auto site : equivalent_sites) {
+            for (t_logical_block_type_ptr site : equivalent_sites) {
                 if (logical_block.name == site->pb_type->name) {
                     logical_block.equivalent_tiles.push_back(&physical_tile);
                     break;

libs/libarchfpga/src/echo_arch.cpp

@@ -184,7 +184,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
             break;
     }
 
-    switch (arch->SBType) {
+    switch (arch->sb_type) {
         case (WILTON):
             fprintf(Echo, "\tSwitch Block: type wilton fs %d\n", arch->Fs);
             break;

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -200,8 +200,8 @@ t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, const pugiu
     t_wire_switchpoints wire_switchpoints;
     wire_switchpoints.segment_name = get_attribute(node, "type", loc_data).value();
 
-    auto points_str = get_attribute(node, "switchpoint", loc_data).value();
-    for (const auto& point_str : vtr::StringToken(points_str).split(",")) {
+    std::string points_str = get_attribute(node, "switchpoint", loc_data).value();
+    for (const std::string& point_str : vtr::StringToken(points_str).split(",")) {
         int switchpoint = vtr::atoi(point_str);
         wire_switchpoints.switchpoints.push_back(switchpoint);
     }
@@ -229,13 +229,13 @@ static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchp
 /* parses the wire types specified in the comma-separated 'ch' char array into the vector wire_points_vec.
  * Spaces are trimmed off */
 static void parse_comma_separated_wire_types(const char* ch, std::vector<t_wire_switchpoints>& wire_switchpoints) {
-    auto types = vtr::StringToken(ch).split(",");
+    std::vector<std::string> types = vtr::StringToken(ch).split(",");
 
     if (types.empty()) {
         archfpga_throw(__FILE__, __LINE__, "parse_comma_separated_wire_types: found empty wireconn wire type entry\n");
     }
 
-    for (const auto& type : types) {
+    for (const std::string& type : types) {
         t_wire_switchpoints wsp;
         wsp.segment_name = type;
 
@@ -245,15 +245,15 @@ static void parse_comma_separated_wire_types(const char* ch, std::vector<t_wire_
 
 /* parses the wirepoints specified in the comma-separated 'ch' char array into the vector wire_points_vec */
 static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire_switchpoints>& wire_switchpoints) {
-    auto points = vtr::StringToken(ch).split(",");
+    std::vector<std::string> points = vtr::StringToken(ch).split(",");
     if (points.empty()) {
         archfpga_throw(__FILE__, __LINE__, "parse_comma_separated_wire_points: found empty wireconn wire point entry\n");
     }
 
-    for (const auto& point_str : points) {
+    for (const std::string& point_str : points) {
         int point = vtr::atoi(point_str);
 
-        for (auto& wire_switchpoint : wire_switchpoints) {
+        for (t_wire_switchpoints& wire_switchpoint : wire_switchpoints) {
             wire_switchpoint.switchpoints.push_back(point);
         }
     }
@@ -404,7 +404,7 @@ void check_switchblock(const t_switchblock_inf* sb, const t_arch* arch) {
     }
 
     /* check that specified wires exist */
-    for (const auto& wireconn : sb->wireconns) {
+    for (const t_wireconn_inf& wireconn : sb->wireconns) {
         check_wireconn(arch, wireconn);
     }
 
@@ -464,7 +464,7 @@ static void check_bidir_switchblock(const t_permutation_map* permutation_map) {
 
 static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn) {
     for (const t_wire_switchpoints& wire_switchpoints : wireconn.from_switchpoint_set) {
-        auto seg_name = wire_switchpoints.segment_name;
+        std::string seg_name = wire_switchpoints.segment_name;
 
         //Make sure the segment exists
         const t_segment_inf* seg_info = find_segment(arch, seg_name);
@@ -485,7 +485,7 @@ static void check_wireconn(const t_arch* arch, const t_wireconn_inf& wireconn) {
     }
 
     for (const t_wire_switchpoints& wire_switchpoints : wireconn.to_switchpoint_set) {
-        auto seg_name = wire_switchpoints.segment_name;
+        std::string seg_name = wire_switchpoints.segment_name;
 
         //Make sure the segment exists
         const t_segment_inf* seg_info = find_segment(arch, seg_name);

libs/libarchfpga/src/physical_types.h

@@ -2282,10 +2282,10 @@ struct t_noc_inf {
     std::string noc_router_tile_name;
 };
 
-/* Detailed routing architecture */
+// Detailed routing architecture
 struct t_arch {
-    /** Stores unique strings used as key and values in <metadata> tags,
-     * i.e. implements a flyweight pattern to save memory.*/
+    /// Stores unique strings used as key and values in <metadata> tags,
+    /// i.e. implements a flyweight pattern to save memory.
     mutable vtr::string_internment strings;
     std::vector<vtr::interned_string> interned_strings;
 
@@ -2322,8 +2322,8 @@ struct t_arch {
     // End of tileable architecture options
 
     t_chan_width_dist Chans;
-    enum e_switch_block_type SBType;
-    enum e_switch_block_type SBSubType;
+    enum e_switch_block_type sb_type;
+    enum e_switch_block_type sb_sub_type;
     std::vector<t_switchblock_inf> switchblocks;
     float R_minW_nmos;
     float R_minW_pmos;

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -2327,7 +2327,7 @@ struct ArchReader {
         arch_->Chans.chan_y_dist.xpeak = 0;
         arch_->Chans.chan_y_dist.dc = 0;
         arch_->ipin_cblock_switch_name.push_back(std::string("generic"));
-        arch_->SBType = WILTON;
+        arch_->sb_type = WILTON;
         arch_->Fs = 3;
         default_fc_.specified = true;
         default_fc_.in_value_type = e_fc_value_type::FRACTIONAL;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -451,7 +451,7 @@ void xml_read_arch(const char* ArchFile,
         arch->switches = process_switches(Next, timing_enabled, loc_data);
 
         /* Process switchblocks. This depends on switches */
-        bool switchblocklist_required = (arch->SBType == CUSTOM); //require this section only if custom switchblocks are used
+        bool switchblocklist_required = (arch->sb_type == CUSTOM); //require this section only if custom switchblocks are used
         SWITCHBLOCKLIST_REQD = BoolToReqOpt(switchblocklist_required);
 
         /* Process segments. This depends on switches */
@@ -2923,13 +2923,13 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
     Prop = get_attribute(Cur, "type", loc_data).value();
     /* Parse attribute 'type', representing the major connectivity pattern for switch blocks */
     if (strcmp(Prop, "wilton") == 0) {
-        arch->SBType = WILTON;
+        arch->sb_type = WILTON;
     } else if (strcmp(Prop, "universal") == 0) {
-        arch->SBType = UNIVERSAL;
+        arch->sb_type = UNIVERSAL;
     } else if (strcmp(Prop, "subset") == 0) {
-        arch->SBType = SUBSET;
+        arch->sb_type = SUBSET;
     } else if (strcmp(Prop, "custom") == 0) {
-        arch->SBType = CUSTOM;
+        arch->sb_type = CUSTOM;
         custom_switch_block = true;
     } else {
         archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
@@ -2944,17 +2944,17 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
     std::string sub_type_str = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string("");
     if (!sub_type_str.empty()) {
         if (sub_type_str == std::string("wilton")) {
-            arch->SBSubType = WILTON;
+            arch->sb_sub_type = WILTON;
         } else if (sub_type_str == std::string("universal")) {
-            arch->SBSubType = UNIVERSAL;
+            arch->sb_sub_type = UNIVERSAL;
         } else if (sub_type_str == std::string("subset")) {
-            arch->SBSubType = SUBSET;
+            arch->sb_sub_type = SUBSET;
         } else {
             archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
                            "Unknown property %s for switch block subtype x\n", sub_type_str.c_str());
         }
     } else {
-        arch->SBSubType = arch->SBType;
+        arch->sb_sub_type = arch->sb_type;
     }
 
     ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block);

vpr/src/base/setup_vpr.cpp

@@ -427,8 +427,8 @@ static void setup_switches(const t_arch& Arch,
  */
 static void setup_routing_arch(const t_arch& Arch,
                                t_det_routing_arch& RoutingArch) {
-    RoutingArch.switch_block_type = Arch.SBType;
-    RoutingArch.switch_block_subtype = Arch.SBSubType;
+    RoutingArch.switch_block_type = Arch.sb_type;
+    RoutingArch.switch_block_subtype = Arch.sb_sub_type;
     RoutingArch.R_minW_nmos = Arch.R_minW_nmos;
     RoutingArch.R_minW_pmos = Arch.R_minW_pmos;
     RoutingArch.Fs = Arch.Fs;