update golden results

soheilshahrouz · soheilshahrouz · commit dbe9903b2b1e · 2024-11-09T17:57:55.000-05:00
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	crit_path_delay_mcw	clk_to_clk_cpd	clk_to_clk2_cpd	clk_to_input_cpd	clk_to_output_cpd	clk2_to_clk2_cpd	clk2_to_clk_cpd	clk2_to_input_cpd	clk2_to_output_cpd	input_to_input_cpd	input_to_clk_cpd	input_to_clk2_cpd	input_to_output_cpd	output_to_output_cpd	output_to_clk_cpd	output_to_clk2_cpd	output_to_input_cpd	clk_to_clk_setup_slack	clk_to_clk2_setup_slack	clk_to_input_setup_slack	clk_to_output_setup_slack	clk2_to_clk2_setup_slack	clk2_to_clk_setup_slack	clk2_to_input_setup_slack	clk2_to_output_setup_slack	input_to_input_setup_slack	input_to_clk_setup_slack	input_to_clk2_setup_slack	input_to_output_setup_slack	output_to_output_setup_slack	output_to_clk_setup_slack	output_to_clk2_setup_slack	output_to_input_setup_slack	clk_to_clk_hold_slack	clk_to_clk2_hold_slack	clk_to_input_hold_slack	clk_to_output_hold_slack	clk2_to_clk2_hold_slack	clk2_to_clk_hold_slack	clk2_to_input_hold_slack	clk2_to_output_hold_slack	input_to_input_hold_slack	input_to_clk_hold_slack	input_to_clk2_hold_slack	input_to_output_hold_slack	output_to_output_hold_slack	output_to_clk_hold_slack	output_to_clk2_hold_slack	output_to_input_hold_slack	
-k6_frac_N10_mem32K_40nm_clk_buf.xml	multiclock_buf.blif	common	1.48876	0.545	-1	-1	-1	0.545	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.293	-1	-1	-1	0.293	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+k6_frac_N10_mem32K_40nm_clk_buf.xml	multiclock_buf.blif	common	1.6599674	0.545	-1	-1	-1	0.545	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.293	-1	-1	-1	0.293	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt
@@ -1,8 +1,8 @@
 arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_global_nets	num_routed_nets	
 timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_ideal_--route_chan_width_60	0.30	vpr	57.61 MiB		-1	-1	0.06	19388	1	0.02	-1	-1	33516	-1	-1	1	2	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	58988	2	1	3	4	1	3	4	3	3	9	-1	auto	19.1 MiB	0.00	4	9	6	3	0	57.6 MiB	0.00	0.00	0.55447	-0.91031	-0.55447	0.55447	0.00	1.4209e-05	1.0635e-05	0.000112608	8.885e-05	-1	2	1	18000	18000	14049.7	1561.07	0.00	0.00111531	0.00103596	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
 timing/k6_N10_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_route_--route_chan_width_60	0.30	vpr	57.69 MiB		-1	-1	0.06	19244	1	0.02	-1	-1	33536	-1	-1	1	2	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	59076	2	1	3	4	1	3	4	3	3	9	-1	auto	19.2 MiB	0.00	6	9	5	2	2	57.7 MiB	0.00	0.00	0.48631	-0.91031	-0.48631	0.48631	0.00	1.4475e-05	1.0195e-05	0.000102982	7.9111e-05	-1	4	1	18000	18000	15707.9	1745.32	0.00	0.00110914	0.00104203	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_ideal_--route_chan_width_60	26.57	parmys	203.92 MiB		-1	-1	21.33	208816	2	1.49	-1	-1	61188	-1	-1	155	5	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	61088	5	156	191	347	1	163	316	15	15	225	clb	auto	21.3 MiB	0.03	22	75566	54444	2848	18274	59.7 MiB	0.07	0.00	1.49664	-15.129	-1.49664	1.49664	0.00	0.000225009	0.000209684	0.0166386	0.0154931	-1	38	6	3.042e+06	2.79e+06	863192.	3836.41	0.01	0.0221087	0.0205962	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
-timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_route_--route_chan_width_60	26.99	parmys	204.15 MiB		-1	-1	21.52	209052	2	1.49	-1	-1	60656	-1	-1	155	5	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	60972	5	156	191	347	1	163	316	15	15	225	clb	auto	21.3 MiB	0.03	25	77716	55619	3345	18752	59.5 MiB	0.13	0.00	1.47823	-14.9031	-1.47823	1.47823	0.00	0.000388878	0.000358886	0.0289108	0.0266306	-1	38	3	3.042e+06	2.79e+06	892591.	3967.07	0.01	0.0351201	0.0324031	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_ideal_--route_chan_width_60	26.57	parmys	203.92 MiB		-1	-1	21.33	208816	2	1.49	-1	-1	61188	-1	-1	155	5	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	61088	5	156	191	347	1	163	316	15	15	225	clb	auto	21.3 MiB	0.03	22	75566	54444	2848	18274	59.7 MiB	0.07	0.00	1.49664	-15.129	-1.49664	1.49664	0.00	0.000225009	0.000209684	0.0166386	0.0154931	-1	57	6	3.042e+06	2.79e+06	863192.	3836.41	0.01	0.0221087	0.0205962	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	154	9	
+timing/k6_N10_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_route_--route_chan_width_60	26.99	parmys	204.15 MiB		-1	-1	21.52	209052	2	1.49	-1	-1	60656	-1	-1	155	5	-1	-1	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	60972	5	156	191	347	1	163	316	15	15	225	clb	auto	21.3 MiB	0.03	25	77716	55619	3345	18752	59.5 MiB	0.13	0.00	1.47823	-14.9031	-1.47823	1.47823	0.00	0.000388878	0.000358886	0.0289108	0.0266306	-1	57	3	3.042e+06	2.79e+06	892591.	3967.07	0.01	0.0351201	0.0324031	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	153	10	
 timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_ideal_--route_chan_width_60	0.35	vpr	63.08 MiB		-1	-1	0.08	19324	1	0.02	-1	-1	33472	-1	-1	1	2	0	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64592	2	1	3	4	1	3	4	3	3	9	-1	auto	24.5 MiB	0.00	4	9	6	2	1	63.1 MiB	0.00	0.00	0.55247	-0.90831	-0.55247	0.55247	0.00	1.3129e-05	9.703e-06	0.000103951	8.1123e-05	-1	2	2	53894	53894	12370.0	1374.45	0.00	0.00116445	0.00109439	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	2	
 timing/k6_N10_mem32K_40nm.xml	microbenchmarks/d_flip_flop.v	common_--clock_modeling_route_--route_chan_width_60	0.35	vpr	62.96 MiB		-1	-1	0.08	19876	1	0.02	-1	-1	33484	-1	-1	1	2	0	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	64468	2	1	3	4	1	3	4	3	3	9	-1	auto	24.3 MiB	0.00	6	9	5	2	2	63.0 MiB	0.00	0.00	0.48631	-0.90831	-0.48631	0.48631	0.00	1.5477e-05	1.1104e-05	0.000110622	8.6576e-05	-1	8	1	53894	53894	14028.3	1558.70	0.00	0.00113491	0.00106717	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0	3	
 timing/k6_N10_mem32K_40nm.xml	verilog/mkPktMerge.v	common_--clock_modeling_ideal_--route_chan_width_60	6.10	vpr	71.24 MiB		-1	-1	1.09	28164	2	0.15	-1	-1	37372	-1	-1	32	311	15	0	success	84e0337	release IPO VTR_ASSERT_LEVEL=3	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-08-22T23:40:08	gh-actions-runner-vtr-auto-spawned3	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	72952	311	156	972	1128	1	953	514	28	28	784	memory	auto	33.0 MiB	0.48	8979	193966	70726	114124	9116	71.2 MiB	1.31	0.03	4.11528	-4394.91	-4.11528	4.11528	0.00	0.00488787	0.00418834	0.465058	0.395185	-1	13380	12	4.25198e+07	9.94461e+06	2.96205e+06	3778.13	0.38	0.643724	0.557601	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	15	938	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt
@@ -1,3 +1,3 @@
  arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  total_swap	  accepted_swap	  rejected_swap	  aborted_swap	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_num_rr_graph_nodes	  crit_path_num_rr_graph_edges	  crit_path_collapsed_nodes	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_create_rr_graph_time	  crit_path_create_intra_cluster_rr_graph_time	  crit_path_tile_lookahead_computation_time	  crit_path_router_lookahead_computation_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
  k6_frac_N10_40nm.xml	  test_eblif.eblif	  common	  0.12	  vpr	  60.11 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  3	  -1	  -1	  success	  e1c7cb1	  Release IPO VTR_ASSERT_LEVEL=3	  GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64	  2024-09-24T03:42:01	  fv-az1118-845	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  61552	  3	  1	  5	  6	  1	  4	  5	  3	  3	  9	  -1	  auto	  21.6 MiB	  0.00	  9	  12	  1	  9	  2	  60.1 MiB	  0.00	  0.00	  0.52647	  -0.88231	  -0.52647	  0.52647	  0.00	  1.0349e-05	  7.103e-06	  8.7732e-05	  6.8547e-05	  20	  10	  1	  53894	  53894	  4880.82	  542.314	  0.00	  0.00111687	  0.00105846	  379	  725	  -1	  6	  1	  3	  3	  36	  25	  0.605178	  0.605178	  -1.1507	  -0.605178	  0	  0	  6579.40	  731.044	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00107362	  0.00104552	 
- k6_frac_N10_40nm.xml	  conn_order.eblif	  common	  0.12	  vpr	  59.98 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	  -1	  -1	  success	  e1c7cb1	  Release IPO VTR_ASSERT_LEVEL=3	  GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64	  2024-09-24T03:42:01	  fv-az1118-845	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  61420	  2	  1	  4	  5	  1	  3	  4	  3	  3	  9	  -1	  auto	  21.6 MiB	  0.00	  6	  9	  2	  3	  4	  60.0 MiB	  0.00	  0.00	  0.69084	  -1.21731	  -0.69084	  0.69084	  0.00	  1.4366e-05	  1.0429e-05	  0.000128779	  0.000106057	  20	  9	  1	  53894	  53894	  4880.82	  542.314	  0.00	  0.00110538	  0.00104614	  379	  725	  -1	  5	  1	  2	  2	  25	  19	  0.940178	  0.940178	  -1.48482	  -0.940178	  0	  0	  6579.40	  731.044	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00106677	  0.00104008	 
+ k6_frac_N10_40nm.xml	  conn_order.eblif	  common	  0.12	  vpr	  59.98 MiB	  	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  1	  2	  -1	  -1	  success	  e1c7cb1	  Release IPO VTR_ASSERT_LEVEL=3	  GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64	  2024-09-24T03:42:01	  fv-az1118-845	  /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing	  61420	  2	  1	  4	  5	  1	  3	  4	  3	  3	  9	  -1	  auto	  21.6 MiB	  0.00	  6	  9	  2	  3	  4	  60.0 MiB	  0.00	  0.00	  0.69084	  -1.21731	  -0.69084	  0.69084	  0.00	  1.4366e-05	  1.0429e-05	  0.000128779	  0.000106057	  20	  9	  1	  53894	  53894	  4880.82	  542.314	  0.00	  0.00110538	  0.00104614	  379	  725	  -1	  3	  1	  2	  2	  25	  19	  1.6923204	  1.6923204	  -2.22723	  -1.6923204	  0	  0	  6579.40	  731.044	  0.00	  0.00	  0.00	  -1	  -1	  0.00	  0.00106677	  0.00104008	 
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt
@@ -1,2 +1,2 @@
 arch	circuit	script_params	crit_path_delay_mcw	clk_to_clk_cpd	clk_to_clk2_cpd	clk_to_input_cpd	clk_to_output_cpd	clk2_to_clk2_cpd	clk2_to_clk_cpd	clk2_to_input_cpd	clk2_to_output_cpd	input_to_input_cpd	input_to_clk_cpd	input_to_clk2_cpd	input_to_output_cpd	output_to_output_cpd	output_to_clk_cpd	output_to_clk2_cpd	output_to_input_cpd	clk_to_clk_setup_slack	clk_to_clk2_setup_slack	clk_to_input_setup_slack	clk_to_output_setup_slack	clk2_to_clk2_setup_slack	clk2_to_clk_setup_slack	clk2_to_input_setup_slack	clk2_to_output_setup_slack	input_to_input_setup_slack	input_to_clk_setup_slack	input_to_clk2_setup_slack	input_to_output_setup_slack	output_to_output_setup_slack	output_to_clk_setup_slack	output_to_clk2_setup_slack	output_to_input_setup_slack	clk_to_clk_hold_slack	clk_to_clk2_hold_slack	clk_to_input_hold_slack	clk_to_output_hold_slack	clk2_to_clk2_hold_slack	clk2_to_clk_hold_slack	clk2_to_input_hold_slack	clk2_to_output_hold_slack	input_to_input_hold_slack	input_to_clk_hold_slack	input_to_clk2_hold_slack	input_to_output_hold_slack	output_to_output_hold_slack	output_to_clk_hold_slack	output_to_clk2_hold_slack	output_to_input_hold_slack	
-k6_frac_N10_mem32K_40nm_clk_buf.xml	multiclock_buf.blif	common	1.48876	0.545	-1	-1	-1	0.545	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.293	-1	-1	-1	0.293	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+k6_frac_N10_mem32K_40nm_clk_buf.xml	multiclock_buf.blif	common	1.65996	0.545	-1	-1	-1	0.545	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	0.293	-1	-1	-1	0.293	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt

Original file line number	Diff line number	Diff line change
`@@ -1,2 +1,2 @@`
`1`	`1`	arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack
`2`		`-k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.48876 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1`
	`2`	`+k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.6599674 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1`