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[Infra] Cleaned Up Include Files in VPR Base Directory
Many include files in the base directory contained includes to other headers which they do not use. This causes many CPP files to include way more header files than they need, increasing the incremental build time. This process needs to be done on the entire VTR repo, but I found that the base directory was one of the biggest culprits of this and the hardest to untangle.
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49 files changed

+65
-78
lines changed

libs/libarchfpga/src/arch_types.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
#define TOKENS " \t\n"
1717

1818
/* Value for UNDEFINED data */
19-
constexpr int UNDEFINED = -1;
19+
constexpr int ARCH_FPGA_UNDEFINED_VAL = -1;
2020

2121
/* Maximum value for minimum channel width to avoid overflows of short data type. */
2222
constexpr int MAX_CHANNEL_WIDTH = 8000;

libs/libarchfpga/src/arch_util.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -444,7 +444,7 @@ t_physical_tile_type get_empty_physical_type(const char* name /*= EMPTY_BLOCK_NA
444444
type.capacity = 0;
445445
type.num_drivers = 0;
446446
type.num_receivers = 0;
447-
type.area = UNDEFINED;
447+
type.area = ARCH_FPGA_UNDEFINED_VAL;
448448
type.switchblock_locations = vtr::Matrix<e_sb_type>({{size_t(type.width), size_t(type.height)}}, e_sb_type::FULL);
449449
type.switchblock_switch_overrides = vtr::Matrix<int>({{size_t(type.width), size_t(type.height)}}, DEFAULT_SWITCH);
450450
type.is_input_type = false;

libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2887,7 +2887,7 @@ static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pu
28872887
"Unknown property %s for chan_width_distr x\n", Prop);
28882888
}
28892889

2890-
chan->peak = get_attribute(Node, "peak", loc_data).as_float(UNDEFINED);
2890+
chan->peak = get_attribute(Node, "peak", loc_data).as_float(ARCH_FPGA_UNDEFINED_VAL);
28912891
chan->width = get_attribute(Node, "width", loc_data, hasWidth).as_float(0);
28922892
chan->xpeak = get_attribute(Node, "xpeak", loc_data, hasXpeak).as_float(0);
28932893
chan->dc = get_attribute(Node, "dc", loc_data, hasDc).as_float(0);
@@ -2994,7 +2994,7 @@ static void ProcessTileProps(pugi::xml_node Node,
29942994
/* Load properties */
29952995
PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1);
29962996
PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1);
2997-
PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
2997+
PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL);
29982998

29992999
if (atof(Prop) < 0) {
30003000
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
@@ -4264,8 +4264,8 @@ static std::vector<t_arch_switch_inf> ProcessSwitches(pugi::xml_node Parent,
42644264
static void ProcessSwitchTdel(pugi::xml_node Node, const bool timing_enabled, t_arch_switch_inf& arch_switch, const pugiutil::loc_data& loc_data) {
42654265
/* check if switch node has the Tdel property */
42664266
bool has_Tdel_prop = false;
4267-
float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
4268-
if (Tdel_prop_value != UNDEFINED) {
4267+
float Tdel_prop_value = get_attribute(Node, "Tdel", loc_data, ReqOpt::OPTIONAL).as_float(ARCH_FPGA_UNDEFINED_VAL);
4268+
if (Tdel_prop_value != ARCH_FPGA_UNDEFINED_VAL) {
42694269
has_Tdel_prop = true;
42704270
}
42714271

libs/librrgraph/src/base/rr_graph_storage.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -464,7 +464,7 @@ size_t t_rr_graph_storage::count_rr_switches(
464464

465465
if (arch_switch_inf[iswitch].fixed_Tdel()) {
466466
//If delay is independent of fanin drop the unique fanin info
467-
fanin = UNDEFINED;
467+
fanin = ARCH_FPGA_UNDEFINED_VAL;
468468
}
469469

470470
if (arch_switch_fanins[iswitch].count(fanin) == 0) { //New fanin for this switch
@@ -482,7 +482,7 @@ size_t t_rr_graph_storage::count_rr_switches(
482482
for(size_t iswitch = 0; iswitch < arch_switch_counts.size(); ++iswitch) {
483483
if(arch_switch_fanins[iswitch].empty()){
484484
if(arch_switch_inf[iswitch].fixed_Tdel()){
485-
arch_switch_fanins[iswitch][UNDEFINED] = num_rr_switches++;
485+
arch_switch_fanins[iswitch][ARCH_FPGA_UNDEFINED_VAL] = num_rr_switches++;
486486
}
487487
}
488488
}
@@ -504,8 +504,8 @@ void t_rr_graph_storage::remap_rr_node_switch_indices(const t_arch_switch_fanin&
504504
int switch_index = edge_switch_[edge];
505505
int fanin = node_fan_in_[to_node];
506506

507-
if (switch_fanin[switch_index].count(UNDEFINED) == 1) {
508-
fanin = UNDEFINED;
507+
if (switch_fanin[switch_index].count(ARCH_FPGA_UNDEFINED_VAL) == 1) {
508+
fanin = ARCH_FPGA_UNDEFINED_VAL;
509509
}
510510

511511
auto itr = switch_fanin[switch_index].find(fanin);

libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -516,7 +516,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
516516
vtr::vector<RRIndexedDataId, std::vector<float>> switch_R_total(rr_indexed_data.size());
517517
vtr::vector<RRIndexedDataId, std::vector<float>> switch_T_total(rr_indexed_data.size());
518518
vtr::vector<RRIndexedDataId, std::vector<float>> switch_Cinternal_total(rr_indexed_data.size());
519-
vtr::vector<RRIndexedDataId, short> switches_buffered(rr_indexed_data.size(), UNDEFINED);
519+
vtr::vector<RRIndexedDataId, short> switches_buffered(rr_indexed_data.size(), ARCH_FPGA_UNDEFINED_VAL);
520520

521521
/*
522522
* Walk through the RR graph and collect all R and C values of all the nodes,
@@ -542,7 +542,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
542542
double avg_switch_Cinternal = 0;
543543
int num_switches = 0;
544544
int num_shorts = 0;
545-
short buffered = UNDEFINED;
545+
short buffered = ARCH_FPGA_UNDEFINED_VAL;
546546
calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list);
547547

548548
if (num_switches == 0) {
@@ -561,13 +561,13 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph,
561561
switch_R_total[cost_index].push_back(avg_switch_R);
562562
switch_T_total[cost_index].push_back(avg_switch_T);
563563
switch_Cinternal_total[cost_index].push_back(avg_switch_Cinternal);
564-
if (buffered == UNDEFINED) {
564+
if (buffered == ARCH_FPGA_UNDEFINED_VAL) {
565565
/* this segment does not have any outgoing edges to other general routing wires */
566566
continue;
567567
}
568568

569569
/* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */
570-
if (switches_buffered[cost_index] == UNDEFINED) {
570+
if (switches_buffered[cost_index] == ARCH_FPGA_UNDEFINED_VAL) {
571571
switches_buffered[cost_index] = buffered;
572572
} else {
573573
if (switches_buffered[cost_index] != buffered) {
@@ -644,7 +644,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou
644644
avg_switch_Cinternal = 0;
645645
num_switches = 0;
646646
num_shorts = 0;
647-
buffered = UNDEFINED;
647+
buffered = ARCH_FPGA_UNDEFINED_VAL;
648648
for (const auto& edge : fan_in_list[node]) {
649649
/* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */
650650
if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) {
@@ -659,7 +659,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou
659659
avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel;
660660
avg_switch_Cinternal += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cinternal;
661661

662-
if (buffered == UNDEFINED) {
662+
if (buffered == ARCH_FPGA_UNDEFINED_VAL) {
663663
if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).buffered()) {
664664
buffered = 1;
665665
} else {

vpr/src/base/CheckArch.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
1+
#include "arch_util.h"
12
#include "vpr_types.h"
23
#include "vpr_error.h"
3-
#include "globals.h"
4-
#include "echo_files.h"
5-
#include "read_xml_arch_file.h"
64
#include "CheckArch.h"
75

86
/******** Function Prototypes ********/

vpr/src/base/CheckArch.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
#ifndef CHECKARCH_H
22
#define CHECKARCH_H
33

4+
#include "physical_types.h"
5+
46
void CheckArch(const t_arch& Arch);
57

68
#endif

vpr/src/base/atom_lookup.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,11 @@
22
#define ATOM_LOOKUP_H
33
#include "atom_lookup_fwd.h"
44

5-
#include <unordered_map>
6-
7-
#include "vtr_bimap.h"
85
#include "vtr_vector_map.h"
96
#include "vtr_range.h"
107

118
#include "atom_netlist_fwd.h"
129
#include "clustered_netlist_fwd.h"
13-
#include "vpr_types.h"
1410
#include "tatum/TimingGraphFwd.hpp"
1511

1612
#include "vtr_optional.h"

vpr/src/base/atom_netlist.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22

33
#include "atom_netlist.h"
44
#include "logic_types.h"
5+
#include "netlist_utils.h"
56
#include "vpr_error.h"
67
#include "vtr_assert.h"
78

vpr/src/base/atom_netlist.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,6 @@
6868
#include <vector>
6969
#include <unordered_map>
7070

71-
#include "vtr_range.h"
7271
#include "vtr_logic.h"
7372
#include "vtr_vector_map.h"
7473

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