Updating configs for vtr_reg_system_verilog tests. They now read in multiple .sv files instead of single flattened .sv files (with the exception of the f4pga_pulse_width_led test since it uses .v files instead of .sv)

Author: loglav03

vtr_flow/misc/yosys/synthesis.tcl

@@ -1,5 +1,4 @@
 yosys -import
-#puts "Files in here: [glob -nocomplain *]"
 plugin -i parmys
 
 read_verilog -nomem2reg +/parmys/vtr_primitives.v
@@ -38,7 +37,7 @@ parmys_arch -a QQQ
 #	}
 
 if {$env(PARSER) == "slang" } {
-	# Create a file list containing the name(s) of file(s)
+	# Create a file list containing the name(s) of file(s) \
 	# to read together with read_slang
 	set sv_files {}
 	set v_files {}
@@ -57,10 +56,10 @@ if {$env(PARSER) == "slang" } {
 		}
 	}
 	close $fh
-	if {[llength $sv_files] > 0} {
+	#if {[llength $sv_files] > 0} {
 		#puts "Using Yosys read_slang command"
 		#read_slang -C $readfile
-	}
+	#}
 	puts "Using Yosys read_slang command"
 	read_slang -C $readfile
 } elseif {$env(PARSER) == "default" } {

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test4/koios_medium/config/config.txt

@@ -46,4 +46,4 @@ qor_parse_file=qor_standard.txt
 pass_requirements_file=pass_requirements_fixed_chan_width.txt
 
 #Script parameters
-script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300
+script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt

@@ -12,14 +12,14 @@ archs_dir=arch/timing
 
 
 # Add circuits to list to sweep
-#include_list_add=display_control.sv
-#include_list_add=timer.sv
-#include_list_add=debounce.sv
+include_list_add=display_control.sv
+include_list_add=timer.sv
+include_list_add=debounce.sv
 
 # Add circuits to list to sweep
-#circuit_list_add=button_controller.sv
+#circuit_list_add=flattened_button_controller.sv
 
-circuit_list_add=flattened_button_controller.sv
+circuit_list_add=button_controller.sv
 
 
 # Add architectures to list to sweep

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt

@@ -12,13 +12,14 @@ archs_dir=arch/timing
 
 
 # Add circuits to list to sweep
-#include_list_add=timer.sv
-#include_list_add=display_control.sv
-#include_list_add=time_counter.sv
-#include_list_add=modify_count.sv
+include_list_add=modify_count.sv
+include_list_add=display_control.sv
+include_list_add=time_counter.sv
+include_list_add=timer.sv
 
 # Add circuits to list to sweep
-circuit_list_add=flattened_timer.sv
+#circuit_list_add=flattened_timer.sv
+circuit_list_add=clock.sv
 
 
 # Add architectures to list to sweep

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/config.txt

@@ -0,0 +1,37 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/system_verilog/koios_sv
+includes_dir=benchmarks/system_verilog/koios_sv
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+
+# Add circuits to list to sweep
+#include_list_add=display_control.sv
+#include_list_add=timer.sv
+#include_list_add=debounce.sv
+
+# Add circuits to list to sweep
+circuit_list_add=deepfreeze.style1.sv
+
+
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang

vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt

@@ -1,3 +1,4 @@
 regression_tests/vtr_reg_system_verilog/f4pga_button_controller/
+#regression_tests/vtr_reg_system_verilog/koios_sv/
 regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/
 regression_tests/vtr_reg_system_verilog/f4pga_timer/