Merge branch 'master' into yosys_to_submodule

Author: loglav03

.github/workflows/nightly_test_manual.yml

@@ -50,6 +50,7 @@ jobs:
         make get_ispd_benchmarks
         ./dev/upgrade_vtr_archs.sh
         make get_symbiflow_benchmarks
+        make get_zeroasic_rr_graphs
 
     # Build VTR using the default build options.
     - name: 'Build VTR'
@@ -133,4 +134,4 @@ jobs:
       with:
         name: nightly_tests_golden
         path: |
-          vtr_flow/**/vtr_reg_nightly*/**/golden_results.txt
+          vtr_flow/**/vtr_reg_nightly*/**/golden_results.txt

CMakeLists.txt

@@ -360,6 +360,14 @@ add_custom_target(get_symbiflow_benchmarks
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
     COMMENT "Downloading (~100MB) and extracting SymbiFlow architectures (~2.7GB) into VTR source tree.")
 
+#
+# Zero ASIC RR Graph Files
+#
+add_custom_target(get_zeroasic_rr_graphs
+    COMMAND ./vtr_flow/scripts/get_zeroasic_rr_graphs.py --vtr_flow_dir ./vtr_flow
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+    COMMENT "Downloading (~2MB) and extracting Zero ASIC RR graphs (~0.1GB) into VTR source tree.")
+
 #
 # Unit Testing
 #

doc/.gitignore

@@ -1,2 +1,3 @@
 #Sphinx
 _build
+.venv

doc/README

@@ -14,19 +14,22 @@ Currently VTR's documenation is automatically built by https://readthedocs.org/p
 How to build documentation
 --------------------------
 
-To build the documentation locally you need sphinx installed:
+To build the documentation locally you need to to install Doxygen (Optional) and the python dependencies. You can use your distribution's package manager to install Doxygen. Ubuntu and Debian users can use the following command:
 
-    For ubuntu/debian based systems:
+    $ sudo apt install doxygen
 
-        $ apt-get install python-sphinx
+While Fedora and RHEL users can use the following command:
 
-    To properly build citations and the bibliography, we use the sphinxcontrib-bibtex extension:
+    $ sudo dnf install doxygen
 
-        $ pip install sphinxcontrib-bibtex
+You can install python dependencies by fist optionally making a virtual environment:
 
-    To install all the python requirements:
+    $ python -m venv .venv
+    $ source .venv/bin/activate
 
-        $ pip install -r requirements.txt
+And then using the requirements file to install the dependencies:
+
+    $ pip install -r requirements.txt
 
 To build the documentation just run:
 

doc/requirements.txt

@@ -2,11 +2,12 @@
 # used by Read The Docs to install python required
 # modules with pip.
 
-sphinx<7
+# Pinned sphinx's version to avoid breakage in future
+sphinx == 8.2.3
 sphinx_rtd_theme
 
 # Support custom domains
-sphinxcontrib-domaintools
+git+https://github.com/AmirhosseinPoolad/sphinxcontrib-domaintools
 
 # Support Markdown
 sphinx-markdown-tables

doc/src/conf.py

@@ -67,13 +67,13 @@
 master_doc = "index"
 
 project = "Verilog-to-Routing"
-copyright = "2012-2022, VTR Developers"
+copyright = "2012-2025, VTR Developers"
 author = "VTR Developers"
 
 version = get_vtr_version()
 release = get_vtr_release()
 
-language = None
+language = "en"
 
 exclude_patterns = ["_build"]
 
@@ -87,8 +87,6 @@
 
 html_theme = "sphinx_rtd_theme"
 
-html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
-
 html_logo = "_static/vtr_logo.svg"
 
 html_favicon = "_static/favicon.ico"

doc/src/vpr/command_line_usage.rst

@@ -1824,6 +1824,20 @@ The following options are only valid when the router is in timing-driven mode (t
 
      **Default:** ``map``
 
+.. option:: --router_initial_acc_cost_chan_congestion_threshold <float>
+
+    Utilization threshold above which initial accumulated routing cost (acc_cost) is increased to penalize congested channels.
+    Used to bias routing away from highly utilized regions during early routing iterations.
+
+    **Default:** ``0.5``
+
+.. option:: --router_initial_acc_cost_chan_congestion_weight <float>
+    Weight applied to the excess channel utilization (above threshold) when computing the initial accumulated cost (acc_cost)of routing resources.
+
+    Higher values make the router more sensitive to early congestion.
+
+    **Default:** ``0.5``
+
 .. option:: --router_max_convergence_count <float>
 
     Controls how many times the router is allowed to converge to a legal routing before halting.

libs/librrgraph/src/base/check_rr_graph.cpp

@@ -53,9 +53,9 @@ void check_rr_graph(const RRGraphView& rr_graph,
                     const t_chan_width& chan_width,
                     const e_graph_type graph_type,
                     bool is_flat) {
-    e_route_type route_type = DETAILED;
+    e_route_type route_type = e_route_type::DETAILED;
     if (graph_type == e_graph_type::GLOBAL) {
-        route_type = GLOBAL;
+        route_type = e_route_type::GLOBAL;
     }
 
     auto total_edges_to_node = std::vector<int>(rr_graph.num_nodes());
@@ -420,7 +420,7 @@ void check_rr_node(const RRGraphView& rr_graph,
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                 "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh);
             }
-            if (route_type == GLOBAL && xlow != xhigh) {
+            if (route_type == e_route_type::GLOBAL && xlow != xhigh) {
                 VPR_ERROR(VPR_ERROR_ROUTE,
                           "in check_rr_node: node %d spans multiple channel segments (not allowed for global routing).\n", inode);
             }
@@ -431,7 +431,7 @@ void check_rr_node(const RRGraphView& rr_graph,
                 VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
                                 "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh);
             }
-            if (route_type == GLOBAL && ylow != yhigh) {
+            if (route_type == e_route_type::GLOBAL && ylow != yhigh) {
                 VPR_ERROR(VPR_ERROR_ROUTE,
                           "in check_rr_node: node %d spans multiple channel segments (not allowed for global routing).\n", inode);
             }
@@ -480,7 +480,7 @@ void check_rr_node(const RRGraphView& rr_graph,
 
         case e_rr_type::CHANX:
         case e_rr_type::CHANY:
-            if (route_type == DETAILED) {
+            if (route_type == e_route_type::DETAILED) {
                 nodes_per_chan = chan_width.max;
                 tracks_per_node = 1;
             } else {

libs/librrgraph/src/base/rr_graph_builder.cpp

@@ -26,13 +26,9 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
     e_rr_type node_type = node_storage_.node_type(node);
     short node_ptc_num = node_storage_.node_ptc_num(node);
     short node_layer = node_storage_.node_layer(node);
-    short node_twist = node_storage_.node_ptc_twist(node);
-    int node_offset = 0;
 
     for (int ix = node_storage_.node_xlow(node); ix <= node_storage_.node_xhigh(node); ix++) {
         for (int iy = node_storage_.node_ylow(node); iy <= node_storage_.node_yhigh(node); iy++) {
-            node_ptc_num += node_twist * node_offset;
-            node_offset++;
 
             switch (node_type) {
                 case e_rr_type::SOURCE:

libs/librrgraph/src/base/rr_graph_builder.h

@@ -205,11 +205,6 @@ class RRGraphBuilder {
         node_storage_.set_node_layer(id, layer);
     }
 
-    /** @brief set the ptc twist increment number for TILEABLE rr graphs (for more information see rr_graph_storage.h twist increment comment) */
-    inline void set_node_ptc_twist_incr(RRNodeId id, int twist){
-        node_storage_.set_node_ptc_twist_incr(id, twist);
-    }
-
 
     /** @brief set_node_pin_num() is designed for logic blocks, which are IPIN and OPIN nodes */
     inline void set_node_pin_num(RRNodeId id, int new_pin_num) {
@@ -325,11 +320,6 @@ class RRGraphBuilder {
         node_storage_.resize(size);
     }
 
-    /** @brief This function resize node ptc twist increment; Since it is only used for tileable rr-graph, we don't put it in general resize function*/
-    inline void resize_ptc_twist_incr(size_t size){
-        node_storage_.resize(size);
-    }
-
     /** @brief This function resize rr_switch to accomidate size RR Switch. */
     inline void resize_switches(size_t size) {
         rr_switch_inf_.resize(size);

libs/librrgraph/src/base/rr_graph_storage.cpp

@@ -635,11 +635,6 @@ void t_rr_graph_storage::set_node_layer(RRNodeId id, short layer) {
     node_layer_[id] = layer;
 }
 
-void t_rr_graph_storage::set_node_ptc_twist_incr(RRNodeId id, short twist_incr){
-    VTR_ASSERT(!node_ptc_twist_incr_.empty());
-    node_ptc_twist_incr_[id] = twist_incr;
-}
-
 void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) {
     node_ptc_[id].ptc_.pin_num = new_ptc_num; //TODO: eventually remove
 }
@@ -821,7 +816,6 @@ t_rr_graph_view t_rr_graph_storage::view() const {
         vtr::make_const_array_view_id(node_fan_in_),
         vtr::make_const_array_view_id(node_layer_),
         node_name_,
-        vtr::make_const_array_view_id(node_ptc_twist_incr_),
         vtr::make_const_array_view_id(edge_src_node_),
         vtr::make_const_array_view_id(edge_dest_node_),
         vtr::make_const_array_view_id(edge_switch_),

libs/librrgraph/src/base/rr_graph_storage.h

@@ -251,18 +251,6 @@ class t_rr_graph_storage {
         return std::nullopt;  // Return an empty optional if key is not found
     }
 
-    /** @brief Find the twist number that RR node uses to change ptc number across the same track.
-     * By default this number is zero, meaning that ptc number across the same track should be the same.
-     * This number is only meaningful for CHANX/CHANY nodes, not the other nodes.
-     */
-    short node_ptc_twist(RRNodeId id) const{
-        //check whether node_ptc_twist_incr has been allocated
-        if(node_ptc_twist_incr_.empty()){
-            return 0;
-        }
-        return node_ptc_twist_incr_[id];
-    }
-
     /**
      * @brief Returns the node ID of the virtual sink for the specified clock network name.
      *
@@ -504,7 +492,6 @@ class t_rr_graph_storage {
         node_ptc_.reserve(node_storage_.capacity());
         node_ptc_.resize(node_storage_.size());
         node_layer_.resize(node_storage_.size());
-        node_ptc_twist_incr_.resize(node_storage_.size());
     }
 
     /** @brief  Reserve storage for RR nodes. */
@@ -525,11 +512,6 @@ class t_rr_graph_storage {
         node_layer_.resize(size);
     }
 
-    /** @brief We only allocate the ptc twist increment array while building tileable rr-graphs */
-    void resize_ptc_twist_incr(size_t size){
-        node_ptc_twist_incr_.resize(size);
-    }
-
     /** @brief Number of RR nodes that can be accessed. */
     size_t size() const {
         return node_storage_.size();
@@ -551,7 +533,6 @@ class t_rr_graph_storage {
         node_layer_.clear();
         node_name_.clear();
         virtual_clock_network_root_idx_.clear();
-        node_ptc_twist_incr_.clear();
         edge_src_node_.clear();
         edge_dest_node_.clear();
         edge_switch_.clear();
@@ -585,7 +566,6 @@ class t_rr_graph_storage {
         node_first_edge_.shrink_to_fit();
         node_fan_in_.shrink_to_fit();
         node_layer_.shrink_to_fit();
-        node_ptc_twist_incr_.shrink_to_fit();
         edge_src_node_.shrink_to_fit();
         edge_dest_node_.shrink_to_fit();
         edge_switch_.shrink_to_fit();
@@ -620,7 +600,6 @@ class t_rr_graph_storage {
     void set_node_name(RRNodeId id, const std::string& new_name);
     void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2);
     void set_node_layer(RRNodeId id, short layer);
-    void set_node_ptc_twist_incr(RRNodeId id, short twist);
     void set_node_cost_index(RRNodeId, RRIndexedDataId new_cost_index);
     void set_node_rc_index(RRNodeId, NodeRCIndex new_rc_index);
     void set_node_capacity(RRNodeId, short new_capacity);
@@ -872,15 +851,6 @@ class t_rr_graph_storage {
      */
     std::unordered_map<std::string, RRNodeId> virtual_clock_network_root_idx_;
 
-    /** @brief
-     *Twist Increment number is defined for CHANX/CHANY nodes; it is useful for layout of tileable FPGAs used by openFPGA.
-     *It gives us a new track index in each tile a longer wire crosses, which enables us to make long wires with a repeated single-tile pattern that "twists" the wires as they cross the tile.
-     *For example, an L4 wire would change tracks 4 times with metal shorts [e.g. 0, 2, 4, 6] and track 6 would drive a switch -- together this implements an L4 wire with only one layout tile.
-     * Twist increment number is only meaningful for CHANX and CHANY nodes; it is 0 for other node types.
-     * We also don't bother allocating this storage if the FPGA is not specified to be tileable; instead in that case the twist for all nodes will always be returned as 0.
-     */
-    vtr::vector<RRNodeId, short> node_ptc_twist_incr_;
-
     /** @brief Edge storage */
     vtr::vector<RREdgeId, RRNodeId> edge_src_node_;
     vtr::vector<RREdgeId, RRNodeId> edge_dest_node_;
@@ -954,7 +924,6 @@ class t_rr_graph_view {
         const vtr::array_view_id<RRNodeId, const t_edge_size> node_fan_in,
         const vtr::array_view_id<RRNodeId, const short> node_layer,
         const std::unordered_map<RRNodeId, std::string>& node_name,
-        const vtr::array_view_id<RRNodeId, const short> node_ptc_twist_incr,
         const vtr::array_view_id<RREdgeId, const RRNodeId> edge_src_node,
         const vtr::array_view_id<RREdgeId, const RRNodeId> edge_dest_node,
         const vtr::array_view_id<RREdgeId, const short> edge_switch,
@@ -965,7 +934,6 @@ class t_rr_graph_view {
         , node_fan_in_(node_fan_in)
         , node_layer_(node_layer)
         , node_name_(node_name)
-        , node_ptc_twist_incr_(node_ptc_twist_incr)
         , edge_src_node_(edge_src_node)
         , edge_dest_node_(edge_dest_node)
         , edge_switch_(edge_switch)
@@ -1055,20 +1023,6 @@ class t_rr_graph_view {
         return std::nullopt;  // Return an empty optional if key is not found
     }
 
-    /**
-     * @brief Retrieve the twist number (if available) that the given RRNodeId used for its PTC number.
-     *
-     * @param id The RRNodeId for which to retrieve the twist number.
-     * @return The twist number used for the PTC number, or a default value if not available.
-     */
-    short node_ptc_twist_incr(RRNodeId id) const{
-        //check if ptc twist increment allocated
-        if(node_ptc_twist_incr_.empty()){
-            return 0; //if it is not allocated we just assume that is zero
-        }
-        return node_ptc_twist_incr_[id];
-    }
-
     /**
      * @brief Prefetches hot RR node data required for optimization.
      *
@@ -1183,7 +1137,6 @@ class t_rr_graph_view {
     vtr::array_view_id<RRNodeId, const t_edge_size> node_fan_in_;
     vtr::array_view_id<RRNodeId, const short> node_layer_;
     const std::unordered_map<RRNodeId, std::string>& node_name_;
-    vtr::array_view_id<RRNodeId, const short> node_ptc_twist_incr_;
     vtr::array_view_id<RREdgeId, const RRNodeId> edge_src_node_;
     vtr::array_view_id<RREdgeId, const RRNodeId> edge_dest_node_;
     vtr::array_view_id<RREdgeId, const short> edge_switch_;

libs/librrgraph/src/base/rr_graph_type.h

@@ -13,7 +13,8 @@ struct t_chan_width {
     std::vector<int> y_list;
 };
 
-enum e_route_type {
+/// @brief Specifies whether global routing or combined global and detailed routing is performed.
+enum class e_route_type {
     GLOBAL,
     DETAILED
 };

libs/librrgraph/src/base/rr_graph_view.h

@@ -223,12 +223,6 @@ class RRGraphView {
         return node_storage_.node_layer(node);
     }
 
-    /** @brief Return the ptc number twist of a specified node.
-    */
-    inline short node_ptc_twist(RRNodeId node) const {
-        return node_storage_.node_ptc_twist(node);
-    }
-
     /** @brief Return the first outgoing edge of a specified node.
     */
     inline RREdgeId node_first_edge(RRNodeId node) const {

libs/librrgraph/src/base/rr_node_types.h

@@ -103,8 +103,8 @@ typedef vtr::Range<edge_idx_iterator> edge_idx_range;
 
 typedef std::vector<std::map<int, int>> t_arch_switch_fanin;
 
-/*
- * Resistance/Capacitance data for an RR Nodes
+/**
+ * @brief Resistance/Capacitance data for an RR Node.
  *
  * In practice many RR nodes have the same values, so they are fly-weighted
  * to keep t_rr_node small. Each RR node holds an rc_index which allows
@@ -121,8 +121,8 @@ typedef std::vector<std::map<int, int>> t_arch_switch_fanin;
 struct t_rr_rc_data {
     t_rr_rc_data(float Rval, float Cval) noexcept;
 
-    float R;
-    float C;
+    float R;    ///< Resistance to go through an RR node
+    float C;    ///<  Total capacitance of an RR node.
 };
 
 // This is the data type of fast lookups of an rr-node given an (rr_type, layer, x, y, and the side)