Merge pull request #2336 from CAS-Atlantic/yosys-upgrade-0.30

yosys-0.32

Author: vaughnbetz

dev/subtree_config.xml

@@ -58,7 +58,7 @@
         name="yosys"
         internal_path="yosys"
         external_url="https://github.com/YosysHQ/yosys.git"
-        default_external_ref="yosys-0.26"/>
+        default_external_ref="yosys-0.32"/>
     <subtree
         name="parmys"
         internal_path="parmys"

libs/EXTERNAL/CMakeLists.txt

@@ -30,7 +30,7 @@ if (${WITH_PARMYS})
                 PREFIX "surelog"
 
                 GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git
-                GIT_TAG 900fb2499c7d3f793409999eabee63db513814b4 # yosys-systemverilog release ac4454e-2023-01-13
+                GIT_TAG v1.71
                 GIT_PROGRESS TRUE
 
                 # setting source, build and install directories
@@ -61,7 +61,7 @@ if (${WITH_PARMYS})
                 PREFIX "f4pga-plugins"
 
                 GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git
-                GIT_TAG e81b0c14d554fbf9cef14dd33155f441242d5ca2 # yosys-systemverilog release ac4454e-2023-01-13
+                GIT_TAG v1.20230808
                 GIT_PROGRESS TRUE
 
                 # setting source, build and install directories

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt

@@ -29,4 +29,4 @@ qor_parse_file=qor_rr_graph.txt
 pass_requirements_file=pass_requirements_verify_rr_graph.txt
 
 # Script parameters
-script_params = -verify_rr_graph --route_chan_width 130
+script_params = -verify_rr_graph --route_chan_width 140