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soheilshahrouzsoheilshahrouz
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update golden results under strong/3d_sb
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‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
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3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 71.34 vpr 1.36 GiB 42 749 0 0 0 0 success v8.0.0-13084-g071ad3865 release IPO VTR_ASSERT_LEVEL=2 GNU 13.3.0 on Linux-6.8.0-60-generic x86_64 2025-06-17T09:37:40 betzgrp-wintermute /home/pooladam/vtr-verilog-to-routing 1422780 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1078.3 MiB 9.92 177076 59415 231119 41859 176714 12546 1389.4 MiB 9.77 0.12 5.0611 4.98951 -4167.4 -3.98951 2.39536 0.05 0.0396378 0.0362787 3.19934 2.68399 98367 7.77974 31434 2.48608 27998 37986 40517554 9161896 0 0 2.54084e+07 20860.8 16 2001132 6214436 -1 5.10947 2.56202 -5359.28 -4.10947 0 0 8.18 -1 -1 1389.4 MiB 8.15 4.82313 4.13218 1389.4 MiB -1 20.52
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
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3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 88.85 vpr 1.32 GiB 42 749 0 0 0 0 success 6611f58 release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.11.0-1015-azure x86_64 2025-07-07T15:33:41 pkrvmbietmlfzoi /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 1381732 13 29 26295 20086 1 12646 791 29 21 1218 LAB auto 1081.5 MiB 16.07 177076 63614 267679 55374 197040 15265 1349.3 MiB 18.12 0.27 5.78021 5.10014 -7339.61 -4.10014 3.58366 0.04 0.0417697 0.0325042 3.43428 2.7049 98045 7.75427 24287 1.92083 27991 37896 11877643 2760195 0 0 2.54084e+07 20860.8 13 2001132 6214436 -1 5.22229 2.88547 -6120.28 -4.22229 0 0 11.83 -1 -1 1349.3 MiB 5.88 5.20722 4.27128 1349.3 MiB -1 20.29

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