[CI] Added Quick Titanium S10 Tests

The titanium benchmarks were not being tested by the CI. Added the
Titanium benchmarks which could be run in under around 2 hours to
NightlyTest7.

5 circuits in this benchmark set currently fail through VTR. The
failures are mainly in the initial placer, which is struggling to create
an initial placement when logical blocks can be placed into different
physical block types which are constrained resources.

Author: AlexandreSinger

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt

@@ -1,5 +1,6 @@
 regression_tests/vtr_reg_nightly_test7/ap_titan
 regression_tests/vtr_reg_nightly_test7/titan_other_run_flat
+regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor
 #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_run_flat
 #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat
 #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat

vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/titanium_s10_quick_qor/config/config.txt

@@ -0,0 +1,58 @@
+##############################################
+# Configuration file for running experiments
+##############################################
+#
+# These are only the Titanium benchmarks which
+# could be run in under around 2 hours.
+#
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/titan_blif/titan_new/stratix10
+
+# Path to directory of SDCs to use
+sdc_dir=benchmarks/titan_blif/titan_new/stratix10
+
+# Path to directory of architectures to use
+archs_dir=arch/titan
+
+# Add circuits to list to sweep
+circuit_list_add=ASU_LRN_stratix10_arch_timing.blif
+# circuit_list_add=ChainNN_LRN_LG_stratix10_arch_timing.blif
+# circuit_list_add=ChainNN_ELT_LG_stratix10_arch_timing.blif
+# circuit_list_add=ChainNN_BSC_LG_stratix10_arch_timing.blif
+circuit_list_add=ASU_ELT_stratix10_arch_timing.blif
+circuit_list_add=ASU_BSC_stratix10_arch_timing.blif
+circuit_list_add=tdfir_stratix10_arch_timing.blif
+# circuit_list_add=pricing_stratix10_arch_timing.blif
+circuit_list_add=mem_tester_stratix10_arch_timing.blif
+circuit_list_add=mandelbrot_stratix10_arch_timing.blif
+circuit_list_add=channelizer_stratix10_arch_timing.blif
+circuit_list_add=fft1d_offchip_stratix10_arch_timing.blif
+circuit_list_add=DLA_LRN_stratix10_arch_timing.blif
+# circuit_list_add=matrix_mult_stratix10_arch_timing.blif
+circuit_list_add=fft1d_stratix10_arch_timing.blif
+circuit_list_add=fft2d_stratix10_arch_timing.blif
+circuit_list_add=DLA_ELT_stratix10_arch_timing.blif
+circuit_list_add=DLA_BSC_stratix10_arch_timing.blif
+circuit_list_add=jpeg_deco_stratix10_arch_timing.blif
+circuit_list_add=nyuzi_stratix10_arch_timing.blif
+circuit_list_add=sobel_stratix10_arch_timing.blif
+
+# Add architectures to list to sweep
+arch_list_add=stratix10_arch.timing.xml
+
+# Parse info and how to parse
+parse_file=vpr_titan_s10.txt
+
+# How to parse QoR info
+qor_parse_file=qor_vpr_titan.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_vpr_titan_s10.txt
+
+# The Titanium benchmarks are run at a fixed channel width of 400 to simulate a
+# Stratix 10-like routing architecture. A large number of routing iterations is
+# set to ensure the router doesn't give up too easily on the larger benchmarks.
+script_params=-starting_stage vpr --route_chan_width 400 --max_router_iterations 400 --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5
+