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Merge pull request #3156 from verilog-to-routing/yosys_to_submodule
Converting Yosys to Submodule
2 parents 7840430 + 7743d86 commit 82f57c2

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‎.gitmodules

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Original file line numberDiff line numberDiff line change
@@ -10,3 +10,6 @@
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[submodule "libs/EXTERNAL/libezgl"]
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path = libs/EXTERNAL/libezgl
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url = https://github.com/verilog-to-routing/ezgl.git
13+
[submodule "libs/EXTERNAL/yosys"]
14+
path = libs/EXTERNAL/yosys
15+
url = https://github.com/YosysHQ/yosys.git

‎CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -413,24 +413,6 @@ if(${WITH_ABC})
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add_subdirectory(abc)
414414
endif()
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416-
if(${WITH_PARMYS}) # define cmake params to compile Yosys
417-
add_definitions("-D_YOSYS_")
418-
419-
set(MAKE_PROGRAM "$(MAKE)")
420-
if(${CMAKE_GENERATOR} STREQUAL "Ninja")
421-
set(MAKE_PROGRAM "make")
422-
endif()
423-
424-
# Commented out since a make file should not call another make command with
425-
# threads. It should pass this information from the parent automatically.
426-
# if(NOT DEFINED "${CMAKE_BUILD_PARALLEL_LEVEL}")
427-
# set(CUSTOM_BUILD_PARALLEL_LEVEL 16)
428-
# else()
429-
# set(CUSTOM_BUILD_PARALLEL_LEVEL "${CMAKE_BUILD_PARALLEL_LEVEL}")
430-
# endif()
431-
add_subdirectory(yosys)
432-
endif()
433-
434416
add_subdirectory(libs) #libs/CMakeLists.txt handles adding warnings flags to non-external libraries
435417

436418
if(${WITH_PARMYS})

‎dev/subtree_config.xml

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Original file line numberDiff line numberDiff line change
@@ -49,11 +49,6 @@
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internal_path="vtr_flow/benchmarks/system_verilog/fx68k"
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external_url="https://github.com/ijor/fx68k.git"
5151
default_external_ref="master"/>
52-
<subtree
53-
name="yosys"
54-
internal_path="yosys"
55-
external_url="https://github.com/YosysHQ/yosys.git"
56-
default_external_ref="yosys-0.32"/>
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<subtree
5853
name="parmys"
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internal_path="parmys"

‎libs/EXTERNAL/CMakeLists.txt

Lines changed: 42 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,47 @@ endif ()
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# The VTR root CMakeFile initializes the WITH_PARMYS
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if (${WITH_PARMYS})
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41+
cmake_minimum_required(VERSION 3.16)
42+
43+
#project(yosys)
44+
45+
# Create a target out of the library compilation result
46+
SET(YOSYS_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys)
47+
SET(YOSYS_BUILD_DIR ${CMAKE_BINARY_DIR}/bin/yosys)
48+
49+
add_definitions("-D_YOSYS_")
50+
set(MAKE_PROGRAM "$(MAKE)")
51+
set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w")
52+
if(${CMAKE_GENERATOR} STREQUAL "Ninja")
53+
set(CURRENT_CPPFLAGS "-w")
54+
endif()
55+
56+
#Initialize yosys submodules
57+
execute_process(
58+
COMMAND git submodule update --init
59+
WORKING_DIRECTORY ${YOSYS_SRC_DIR}
60+
)
61+
execute_process(
62+
COMMAND ${GIT_EXECUTABLE} submodule foreach --recursive git\ submodule\ update\ --init
63+
WORKING_DIRECTORY ${YOSYS_SRC_DIR}
64+
)
65+
66+
# how to build the result of the library
67+
add_custom_command(OUTPUT ${YOSYS_BUILD_DIR}
68+
COMMAND ${MAKE_PROGRAM} -C ${YOSYS_SRC_DIR}
69+
ENABLE_ABC=0
70+
PREFIX=${CMAKE_BINARY_DIR}
71+
72+
COMMAND ${MAKE_PROGRAM}
73+
-C ${YOSYS_SRC_DIR}
74+
install
75+
ENABLE_ABC=0
76+
PREFIX=${CMAKE_BINARY_DIR}
77+
78+
WORKING_DIRECTORY ${YOSYS_SRC_DIR})
79+
80+
add_custom_target(yosys ALL DEPENDS ${YOSYS_BUILD_DIR})
81+
4182
if (${SYNLIG_SYSTEMVERILOG})
4283

4384
set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
@@ -175,4 +216,4 @@ if (VPR_USE_SERVER)
175216
$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/sockpp/include>
176217
$<INSTALL_INTERFACE:include>
177218
)
178-
endif()
219+
endif()

‎libs/EXTERNAL/yosys

Submodule yosys added at 53c22ab

‎parmys/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ add_library(parmys SHARED
1919
)
2020
target_include_directories(parmys PUBLIC ${LIB_INCLUDE_DIRS})
2121
target_include_directories(parmys PUBLIC ${LIB_INCLUDE_DIRS_O})
22-
target_include_directories(parmys PUBLIC ${VTR_SOURCE_DIR}/yosys/share/include)
22+
target_include_directories(parmys PUBLIC ${VTR_SOURCE_DIR}/libs/EXTERNAL/yosys/share/include)
2323

2424
add_definitions("-D_YOSYS_")
2525
add_dependencies(parmys yosys)

‎parmys/regression_test/benchmark/task/freecores/synthesis_result.json

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@@ -483,7 +483,7 @@
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"Average Path": 3,
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"Estimated LUTs": 4777,
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"Total Node": 1957,
486-
"Wires": 5594,
486+
"Wires": 5592,
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"Wire Bits": 10106,
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"Public Wires": 240,
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"Public Wire Bits": 240,

‎parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json

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@@ -95,21 +95,21 @@
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"test_name": "and/replicate_and_int_wide/no_arch",
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"exit": 1,
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"errors": [
98-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
98+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
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]
100100
},
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"and/replicate_and_ultra_wide/no_arch": {
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"test_name": "and/replicate_and_ultra_wide/no_arch",
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"exit": 1,
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"errors": [
105-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
105+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
106106
]
107107
},
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"and/replicate_and_wide/no_arch": {
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"test_name": "and/replicate_and_wide/no_arch",
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"exit": 1,
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"errors": [
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"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
112+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
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]
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},
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"DEFAULT": {

‎parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json

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@@ -94,21 +94,21 @@
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"test_name": "nand/replicate_nand_int_wide/no_arch",
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"exit": 1,
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"errors": [
97-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
97+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
9898
]
9999
},
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"nand/replicate_nand_ultra_wide/no_arch": {
101101
"test_name": "nand/replicate_nand_ultra_wide/no_arch",
102102
"exit": 1,
103103
"errors": [
104-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
104+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
105105
]
106106
},
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"nand/replicate_nand_wide/no_arch": {
108108
"test_name": "nand/replicate_nand_wide/no_arch",
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"exit": 1,
110110
"errors": [
111-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
111+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
112112
]
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},
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"DEFAULT": {

‎parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json

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"test_name": "nor/replicate_nor_int_wide/no_arch",
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"exit": 1,
102102
"errors": [
103-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
103+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
104104
]
105105
},
106106
"nor/replicate_nor_ultra_wide/no_arch": {
107107
"test_name": "nor/replicate_nor_ultra_wide/no_arch",
108108
"exit": 1,
109109
"errors": [
110-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
110+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
111111
]
112112
},
113113
"nor/replicate_nor_wide/no_arch": {
114114
"test_name": "nor/replicate_nor_wide/no_arch",
115115
"exit": 1,
116116
"errors": [
117-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
117+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
118118
]
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},
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"DEFAULT": {

‎parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json

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@@ -95,21 +95,21 @@
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"test_name": "or/replicate_or_int_wide/no_arch",
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"exit": 1,
9797
"errors": [
98-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
98+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
9999
]
100100
},
101101
"or/replicate_or_ultra_wide/no_arch": {
102102
"test_name": "or/replicate_or_ultra_wide/no_arch",
103103
"exit": 1,
104104
"errors": [
105-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
105+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
106106
]
107107
},
108108
"or/replicate_or_wide/no_arch": {
109109
"test_name": "or/replicate_or_wide/no_arch",
110110
"exit": 1,
111111
"errors": [
112-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
112+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
113113
]
114114
},
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"DEFAULT": {

‎parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json

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"test_name": "xnor/replicate_xnor_int_wide/no_arch",
5555
"exit": 1,
5656
"errors": [
57-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
57+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
5858
]
5959
},
6060
"xnor/replicate_xnor_ultra_wide/no_arch": {
6161
"test_name": "xnor/replicate_xnor_ultra_wide/no_arch",
6262
"exit": 1,
6363
"errors": [
64-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
64+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
6565
]
6666
},
6767
"xnor/replicate_xnor_wide/no_arch": {
6868
"test_name": "xnor/replicate_xnor_wide/no_arch",
6969
"exit": 1,
7070
"errors": [
71-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
71+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
7272
]
7373
},
7474
"xnor/xnor_indexed_port/no_arch": {

‎parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json

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"test_name": "xor/replicate_xor_int_wide/no_arch",
5252
"exit": 1,
5353
"errors": [
54-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
54+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
5555
]
5656
},
5757
"xor/replicate_xor_ultra_wide/no_arch": {
5858
"test_name": "xor/replicate_xor_ultra_wide/no_arch",
5959
"exit": 1,
6060
"errors": [
61-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
61+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
6262
]
6363
},
6464
"xor/replicate_xor_wide/no_arch": {
6565
"test_name": "xor/replicate_xor_wide/no_arch",
6666
"exit": 1,
6767
"errors": [
68-
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2754."
68+
"Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746."
6969
]
7070
},
7171
"xor/xor_indexed_port/no_arch": {

‎parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json

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@@ -464,7 +464,7 @@
464464
"Estimated LUTs": 22752,
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"Total Node": 5094,
466466
"Wires": 24045,
467-
"Wire Bits": 37311,
467+
"Wire Bits": 37590,
468468
"Public Wires": 5228,
469469
"Public Wire Bits": 5228,
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"Total Cells": 24019,

‎parmys/regression_test/benchmark/task/syntax/synthesis_result.json

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@@ -2924,8 +2924,8 @@
29242924
"Average Path": 4,
29252925
"Estimated LUTs": 101,
29262926
"Total Node": 67,
2927-
"Wires": 213,
2928-
"Wire Bits": 269,
2927+
"Wires": 212,
2928+
"Wire Bits": 268,
29292929
"Public Wires": 177,
29302930
"Public Wire Bits": 177,
29312931
"Total Cells": 145,
@@ -2964,8 +2964,8 @@
29642964
"Average Path": 5,
29652965
"Estimated LUTs": 25938,
29662966
"Total Node": 34130,
2967-
"Wires": 76078,
2968-
"Wire Bits": 84564,
2967+
"Wires": 76077,
2968+
"Wire Bits": 84563,
29692969
"Public Wires": 75169,
29702970
"Public Wire Bits": 75169,
29712971
"Total Cells": 59068,
@@ -4048,8 +4048,8 @@
40484048
"Average Path": 4,
40494049
"Estimated LUTs": 101,
40504050
"Total Node": 33,
4051-
"Wires": 104,
4052-
"Wire Bits": 169,
4051+
"Wires": 103,
4052+
"Wire Bits": 168,
40534053
"Public Wires": 71,
40544054
"Public Wire Bits": 71,
40554055
"Total Cells": 111,
@@ -4086,8 +4086,8 @@
40864086
"Average Path": 4,
40874087
"Estimated LUTs": 33,
40884088
"Total Node": 33,
4089-
"Wires": 104,
4090-
"Wire Bits": 169,
4089+
"Wires": 103,
4090+
"Wire Bits": 168,
40914091
"Public Wires": 71,
40924092
"Public Wire Bits": 71,
40934093
"Total Cells": 111,

‎parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json

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@@ -318,7 +318,7 @@
318318
"Average Path": 2,
319319
"Estimated LUTs": 2852,
320320
"Total Node": 1381,
321-
"Wires": 3620,
321+
"Wires": 3619,
322322
"Wire Bits": 5288,
323323
"Public Wires": 119,
324324
"Public Wire Bits": 119,

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