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Adjust vtr_reg_weekly with less effort on Titan, and remove gaussian blur
Signed-off-by: Keith Rothman <[email protected]>
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13 files changed

+298
-4
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‎.github/kokoro/continuous/weekly.cfg

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@@ -36,10 +36,10 @@ env_vars {
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env_vars {
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key: "VTR_TEST"
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value: "vtr_reg_weekly"
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value: "vtr_reg_weekly_no_he"
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}
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env_vars {
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key: "NUM_CORES"
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value: "1"
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value: "3"
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}

‎.github/kokoro/presubmit/weekly.cfg

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@@ -36,10 +36,10 @@ env_vars {
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env_vars {
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key: "VTR_TEST"
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value: "vtr_reg_weekly"
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value: "vtr_reg_weekly_no_he"
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}
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env_vars {
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key: "NUM_CORES"
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value: "1"
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value: "3"
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}

‎vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/task_list.txt

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regression_tests/vtr_reg_weekly/vtr_reg_titan
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regression_tests/vtr_reg_weekly/vtr_reg_qor_chain_predictor_off
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regression_tests/vtr_reg_weekly/vtr_reg_fpu_hard_block_arch
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regression_tests/vtr_reg_weekly/vtr_reg_fpu_soft_logic_arch
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regression_tests/vtr_reg_weekly/vpr_ispd

‎vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/config.txt

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#
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############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/ispd_blif
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# Path to directory of architectures to use
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archs_dir=arch/ispd
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# Add circuits to list to sweep
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circuit_list_add=FPGA-example1.blif
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circuit_list_add=FPGA-example2.blif
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circuit_list_add=FPGA-example3.blif
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circuit_list_add=FPGA-example4.blif
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circuit_list_add=clk_design1.blif
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circuit_list_add=clk_design2.blif
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circuit_list_add=clk_design3.blif
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circuit_list_add=clk_design4.blif
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circuit_list_add=clk_design5.blif
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# Add architectures to list to sweep
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arch_list_add=ultrascale_ispd.xml
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# Parse info and how to parse
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parse_file=vpr_ispd.txt
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# How to parse QoR info
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qor_parse_file=qor_vpr_ispd.txt
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# Pass requirements
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pass_requirements_file=pass_requirements_vpr_ispd.txt
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#The ISPD architecture is missing a detailed rouing architecture model and
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#timing model, so we only do wirelength-driven packing and placement
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script_params=-starting_stage vpr --pack --place --timing_analysis off
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‎vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vpr_ispd/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error num_IO num_CLB num_DSP num_BRAM vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time
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ultrascale_ispd.xml FPGA-example1.blif common 62.36 72 220 2 2 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example1.blif/common 4696036 51 20 3417 3407 1 3287 296 168 480 80640 -1 ultrascale_ispd 4.61 29531 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml FPGA-example2.blif common 5665.13 456 39262 200 400 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example2.blif/common 7117412 303 150 545542 542692 1 539559 40318 168 480 80640 -1 ultrascale_ispd 712.51 5830359 4853.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml FPGA-example3.blif common 5157.95 606 30856 200 500 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example3.blif/common 6647732 403 200 431203 428403 1 429172 32162 168 480 80640 -1 ultrascale_ispd 539.91 16335580 4528.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml FPGA-example4.blif common 5383.65 -1 -1 -1 -1 v8.0.0-rc1-1301-g9c76833f6 exited with return code 1 pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/FPGA-example4.blif/common 5722520 403 200 850587 844787 1 -1 -1 168 480 -1 -1 -1 5368.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml clk_design1.blif common 71.03 109 592 2 2 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design1.blif/common 4720436 57 20 9969 9959 30 9711 705 168 480 80640 -1 ultrascale_ispd 8.47 63424 5.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml clk_design2.blif common 387.99 244 5837 10 10 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design2.blif/common 5114708 137 60 100115 100025 45 97978 6101 168 480 80640 -1 ultrascale_ispd 83.13 924709 241.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml clk_design3.blif common 2467.90 374 22993 50 96 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design3.blif/common 6314720 217 120 400080 399454 35 390926 23513 168 480 80640 -1 ultrascale_ispd 223.80 4772904 2160.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml clk_design4.blif common 5289.21 484 39151 150 366 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design4.blif/common 7472784 292 150 685438 683387 40 669318 40151 168 480 80640 -1 ultrascale_ispd 376.84 8539380 4810.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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ultrascale_ispd.xml clk_design5.blif common 8688.37 515 51693 420 885 v8.0.0-rc1-1301-g9c76833f6 success pckevin /project/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_weekly/vpr_ispd/run003/ultrascale_ispd.xml/clk_design5.blif/common 8448644 307 150 948147 942073 56 928185 53513 168 480 80640 -1 ultrascale_ispd 545.08 12115275 8024.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

‎vtr_flow/tasks/regression_tests/vtr_reg_weekly_no_he/vtr_reg_fpu_hard_block_arch/config/config.txt

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#
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############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/fpu/hardlogic
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# Path to directory of architectures to use
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archs_dir=arch/timing
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# Add circuits to list to sweep
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circuit_list_add=bfly.v
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circuit_list_add=bgm.v
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circuit_list_add=dscg.v
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circuit_list_add=fir.v
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circuit_list_add=mm3.v
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circuit_list_add=ode.v
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circuit_list_add=syn2.v
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circuit_list_add=syn7.v
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# Add architectures to list to sweep
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arch_list_add=hard_fpu_arch_timing.xml
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# Parse info and how to parse
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parse_file=vpr_hard_fpu.txt
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# Pass requirements
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pass_requirements_file=pass_requirements_fixed_chan_width.txt
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# How to parse QoR info
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qor_parse_file=qor_fixed_chan_width.txt
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# Parameters for vtr flow
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script_params=--route_chan_width 72 --cluster_seed_type max_inputs -track_memory_usage

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