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coding style changes
1 parent 850a0e6 commit 4f34f40

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7 files changed

+24
-17
lines changed

7 files changed

+24
-17
lines changed

vpr/src/draw/draw_basic.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -615,7 +615,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
615615
// Draw RR Nodes
616616
for (size_t i = 1; i < rr_nodes_to_draw.size(); ++i) {
617617
RRNodeId inode = rr_nodes_to_draw[i];
618-
auto rr_type = rr_graph.node_type(inode);
618+
e_rr_type rr_type = rr_graph.node_type(inode);
619619
bool is_inode_inter_cluster = is_inter_cluster_node(rr_graph, inode);
620620
int node_layer = rr_graph.node_layer(inode);
621621

@@ -707,14 +707,14 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
707707
continue;
708708
}
709709

710-
draw_inter_cluster_rr_edge(inode, prev_node, rr_type, prev_type, rr_graph, g);
710+
draw_inter_cluster_rr_edge(inode, prev_node, rr_type, prev_type, g);
711711
}
712712
}
713713

714-
void draw_inter_cluster_rr_edge(RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, const RRGraphView& rr_graph, ezgl::renderer* g) {
715-
716-
auto iedge = find_edge(prev_node, inode);
717-
auto switch_type = rr_graph.edge_switch(RRNodeId(prev_node), iedge);
714+
void draw_inter_cluster_rr_edge(RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, ezgl::renderer* g) {
715+
const RRGraphView& rr_graph = g_vpr_ctx.device().rr_graph;
716+
t_edge_size iedge = find_edge(prev_node, inode);
717+
short switch_type = rr_graph.edge_switch(RRNodeId(prev_node), iedge);
718718

719719
switch (rr_type) {
720720
case e_rr_type::IPIN: {

vpr/src/draw/draw_basic.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,8 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw,
6262
* @param prev_node The previous rr_node id
6363
* @param g The ezgl renderer
6464
*/
65-
void draw_inter_cluster_rr_edge(RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, const RRGraphView& rr_graph, ezgl::renderer* g);
65+
void draw_inter_cluster_rr_edge(RRNodeId inode, RRNodeId prev_node, e_rr_type rr_type, e_rr_type prev_type, ezgl::renderer* g);
66+
6667
/**
6768
* @brief Returns the layer number of a timing path node
6869
* @param node

vpr/src/draw/draw_rr.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -521,9 +521,9 @@ void draw_rr_intra_cluster_pin(RRNodeId inode, const ezgl::color& color, ezgl::r
521521
return;
522522
}
523523

524-
auto blk_id_pin_id = get_rr_node_cluster_blk_id_pb_graph_pin(inode);
524+
auto [blk_id, pin_id] = get_rr_node_cluster_blk_id_pb_graph_pin(inode);
525525

526-
ezgl::point2d p = draw_coords->get_absolute_pin_location(blk_id_pin_id.first, blk_id_pin_id.second);
526+
ezgl::point2d p = draw_coords->get_absolute_pin_location(blk_id, pin_id);
527527

528528
int transparency_factor = get_rr_node_transparency(inode);
529529

@@ -717,8 +717,8 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) {
717717
continue;
718718
}
719719

720-
auto blk_id_pin_id = get_rr_node_cluster_blk_id_pb_graph_pin(inode);
721-
ezgl::point2d p = draw_coords->get_absolute_pin_location(blk_id_pin_id.first, blk_id_pin_id.second);
720+
auto [blk_id, pin_id] = get_rr_node_cluster_blk_id_pb_graph_pin(inode);
721+
ezgl::point2d p = draw_coords->get_absolute_pin_location(blk_id, pin_id);
722722

723723
if (click_x >= p.x - draw_coords->pin_size && click_x <= p.x + draw_coords->pin_size && click_y >= p.y - draw_coords->pin_size && click_y <= p.y + draw_coords->pin_size) {
724724
hit_node = inode;

vpr/src/draw/draw_rr.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,18 +31,21 @@ void draw_rr_chan(RRNodeId inode, const ezgl::color color, ezgl::renderer* g);
3131
* @brief Draws the intra-cluster pin for a given RRNodeId when flat routing is enabled.
3232
*/
3333
void draw_rr_intra_cluster_pin(RRNodeId inode, const ezgl::color& color, ezgl::renderer* g);
34+
3435
/* Draws an IPIN or OPIN rr_node. Note that the pin can appear on more
3536
* than one side of a clb. Also note that this routine can change the
3637
* current color to BLACK. */
3738
void draw_cluster_pin(RRNodeId inode, const ezgl::color& color, ezgl::renderer* g);
3839

3940
void draw_rr_src_sink(RRNodeId inode, ezgl::color color, ezgl::renderer* g);
41+
4042
void draw_get_rr_src_sink_coords(const t_rr_node& node, float* xcen, float* ycen);
4143

4244
/* Draws a buffer (triangle) or pass transistor (circle) on the edge
4345
* connecting from to to, depending on the status of buffered. The drawing
4446
* is closest to the from_node, since it reflects the switch type of from. */
4547
void draw_rr_switch(float from_x, float from_y, float to_x, float to_y, bool buffered, bool switch_configurable, ezgl::renderer* g);
48+
4649
void draw_expand_non_configurable_rr_nodes_recurr(RRNodeId from_node,
4750
std::set<RRNodeId>& expanded_nodes);
4851

vpr/src/draw/draw_rr_edges.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ void draw_chanx_to_chany_edge(RRNodeId chanx_node, RRNodeId chany_node, enum e_c
4646
* @param g The ezgl renderer
4747
*/
4848
void draw_intra_cluster_pin_to_pin(RRNodeId intra_cluster_node, RRNodeId inter_cluster_node, e_pin_edge_dir pin_edge_dir, e_side pin_side, ezgl::renderer* g);
49+
4950
/**
5051
* @brief Draws the edge between two intra-cluster pins when flat routing is enabled.
5152
* @param inode The current node to draw to
@@ -61,6 +62,7 @@ void draw_pin_to_pin(RRNodeId opin, RRNodeId ipin, ezgl::renderer* g);
6162

6263
//TODO: These two functions currently do not draw correctly after rearranging the block locations. They need an update.
6364
void draw_pin_to_sink(RRNodeId ipin_node, RRNodeId sink_node, ezgl::renderer* g);
65+
6466
void draw_source_to_pin(RRNodeId source_node, RRNodeId opin_node, ezgl::renderer* g);
6567

6668
/**
@@ -70,6 +72,7 @@ void draw_source_to_pin(RRNodeId source_node, RRNodeId opin_node, ezgl::renderer
7072
* @return The side of the clb that the pin is located on (e.g. TOP, RIGHT, BOTTOM, LEFT)
7173
*/
7274
e_side get_pin_side(RRNodeId pin_node, RRNodeId chan_node);
75+
7376
/**
7477
* @brief Draws an edge from a inter-cluster pin node to a channel node (CHANX or CHANY).
7578
*/

vpr/src/draw/draw_searchbar.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -136,17 +136,17 @@ void highlight_nets(char* message, RRNodeId hit_node) {
136136
auto& atom_ctx = g_vpr_ctx.atom();
137137
auto& route_ctx = g_vpr_ctx.routing();
138138

139-
/* Don't crash if there's no routing */
139+
// Don't crash if there's no routing
140140
if (route_ctx.route_trees.empty())
141141
return;
142142

143143
if (route_ctx.is_flat) {
144-
for (auto net_id : atom_ctx.netlist().nets()) {
144+
for (AtomNetId net_id : atom_ctx.netlist().nets()) {
145145
check_node_highlight_net(message, net_id, hit_node);
146146
}
147147

148148
} else {
149-
for (auto net_id : cluster_ctx.clb_nlist.nets()) {
149+
for (ClusterNetId net_id : cluster_ctx.clb_nlist.nets()) {
150150
check_node_highlight_net(message, net_id, hit_node);
151151
}
152152
}
@@ -169,7 +169,7 @@ void check_node_highlight_net(char* message, ParentNetId parent_net_id, RRNodeId
169169
if (!route_ctx.route_trees[parent_net_id])
170170
return;
171171

172-
for (auto& rt_node : route_ctx.route_trees[parent_net_id].value().all_nodes()) {
172+
for (RouteTreeNode& rt_node : route_ctx.route_trees[parent_net_id].value().all_nodes()) {
173173
RRNodeId inode = rt_node.inode;
174174
if (draw_state->draw_rr_node[inode].color == ezgl::MAGENTA) {
175175
draw_state->net_color[parent_net_id] = draw_state->draw_rr_node[inode].color;
@@ -179,8 +179,7 @@ void check_node_highlight_net(char* message, ParentNetId parent_net_id, RRNodeId
179179
size_t(parent_net_id),
180180
draw_get_net_name(parent_net_id).c_str());
181181
}
182-
} else if (draw_state->draw_rr_node[inode].color
183-
== ezgl::WHITE) {
182+
} else if (draw_state->draw_rr_node[inode].color == ezgl::WHITE) {
184183
// If node is de-selected.
185184
draw_state->net_color[parent_net_id] = ezgl::BLACK;
186185
break;

vpr/src/draw/draw_types.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,7 @@ enum e_draw_net_type {
109109
ALL_NETS,
110110
HIGHLIGHTED
111111
};
112+
112113
/// Chanx to chany or vice versa?
113114
enum e_chan_edge_dir {
114115
FROM_X_TO_Y,

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