make format

Author: amin1377

libs/libarchfpga/src/physical_types.h

@@ -2284,7 +2284,7 @@ struct t_arch {
     char* architecture_id;
 
     // Options for tileable routing architectures
-    // These are used for an alternative, tilable, rr-graph generator that can produce 
+    // These are used for an alternative, tilable, rr-graph generator that can produce
     // OpenFPGA-compatible FPGAs that can be implemented to silicon via the OpenFPGA flow
 
     /// Whether the routing architecture is tileable

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -2937,7 +2937,7 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
     }
 
     process_tileable_device_parameters(arch, loc_data);
-    
+
     ReqOpt custom_switchblock_reqd = BoolToReqOpt(!custom_switch_block);
     arch->Fs = get_attribute(Cur, "fs", loc_data, custom_switchblock_reqd).as_int(3);
 
@@ -2954,11 +2954,11 @@ static void process_device(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
 static void process_tileable_device_parameters(t_arch* arch, const pugiutil::loc_data& loc_data) {
     pugi::xml_node cur;
 
-    // Parse attribute 'sub_type', representing the minor connectivity pattern for switch blocks 
+    // Parse attribute 'sub_type', representing the minor connectivity pattern for switch blocks
     // If not specified, the 'sub_type' is the same as major type
     // This option is only valid for tileable routing resource graph builder
     // Note that sub_type does not support custom switch block pattern!!!
-    // If 'sub_type' is specified, the custom switch block for 'type' is not allowed! 
+    // If 'sub_type' is specified, the custom switch block for 'type' is not allowed!
     std::string sub_type_str = get_attribute(cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string("");
     if (!sub_type_str.empty()) {
         if (sub_type_str == "wilton") {

libs/libarchfpga/src/vib_inf.h

@@ -151,10 +151,10 @@ class VibInf {
     size_t mux_index_by_name(const std::string& name) const;
 
   private:
-    /// The name of the VIB type, "vib0" in the example. 
+    /// The name of the VIB type, "vib0" in the example.
     std::string name_;
 
-    /// The pbtype of the VIB, "clb" in the example. 
+    /// The pbtype of the VIB, "clb" in the example.
     std::string pbtype_name_;
 
     /// The number of segment groups.

libs/librrgraph/src/base/rr_graph_view.cpp

@@ -79,7 +79,7 @@ RRSegmentId RRGraphView::node_segment(RRNodeId node) const {
 
 size_t RRGraphView::in_edges_count() const {
     size_t edge_count = 0;
-    for (const std::vector<RRwEdgeId>& edge_list : node_in_edges_) {
+    for (const std::vector<RREdgeId>& edge_list : node_in_edges_) {
         edge_count += edge_list.size();
     }
     return edge_count;

vpr/src/base/place_and_route.cpp

@@ -287,9 +287,9 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list,
 
     // The binary search above occasionally does not find the minimum routeable channel width.
     // Sometimes a circuit that will not route in 19 channels will route in 18, due to router flukiness.
-    // If verify_binary_search is set, the code below will ensure that FPGAs with channel widths of 
+    // If verify_binary_search is set, the code below will ensure that FPGAs with channel widths of
     // final-2 and final-3 wil not route successfully.
-    // If one does route successfully, the router keeps trying smaller channel widths until two in a 
+    // If one does route successfully, the router keeps trying smaller channel widths until two in a
     // row (e.g. 8 and 9) fail.
 
     if (verify_binary_search) {