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Convert t_rr_node to a fly-weight object.
This should have a negliable performance impact, but this enables future changes to modify how rr nodes and rr edges are storaged. Signed-off-by: Keith Rothman <[email protected]>
1 parent d7a9c0a commit 3c19d3d

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12 files changed

+459
-266
lines changed

12 files changed

+459
-266
lines changed

‎vpr/src/base/read_route.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
231231
} else if (tokens[0] == "Node:") {
232232
/*An actual line, go through each node and add it to the route tree*/
233233
inode = atoi(tokens[1].c_str());
234-
auto& node = device_ctx.rr_nodes[inode];
234+
auto node = device_ctx.rr_nodes[inode];
235235

236236
/*First node needs to be source. It is isolated to correctly set heap head.*/
237237
if (node_count == 0 && tokens[2] != "SOURCE") {

‎vpr/src/draw/draw.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2042,24 +2042,24 @@ static void draw_rr_pin(int inode, const ezgl::color& color, ezgl::renderer* g)
20422042
* the physical pin is on. */
20432043
void draw_get_rr_pin_coords(int inode, float* xcen, float* ycen) {
20442044
auto& device_ctx = g_vpr_ctx.device();
2045-
draw_get_rr_pin_coords(&device_ctx.rr_nodes[inode], xcen, ycen);
2045+
draw_get_rr_pin_coords(device_ctx.rr_nodes[inode], xcen, ycen);
20462046
}
20472047

2048-
void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
2048+
void draw_get_rr_pin_coords(const t_rr_node node, float* xcen, float* ycen) {
20492049
t_draw_coords* draw_coords = get_draw_coords_vars();
20502050

20512051
int i, j, k, ipin, pins_per_sub_tile;
20522052
float offset, xc, yc, step;
20532053
t_physical_tile_type_ptr type;
20542054
auto& device_ctx = g_vpr_ctx.device();
20552055

2056-
i = node->xlow();
2057-
j = node->ylow();
2056+
i = node.xlow();
2057+
j = node.ylow();
20582058

20592059
xc = draw_coords->tile_x[i];
20602060
yc = draw_coords->tile_y[j];
20612061

2062-
ipin = node->ptc_num();
2062+
ipin = node.ptc_num();
20632063
type = device_ctx.grid[i][j].type;
20642064
pins_per_sub_tile = type->num_pins / type->capacity;
20652065
k = ipin / pins_per_sub_tile;
@@ -2071,7 +2071,7 @@ void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
20712071
step = (float)(draw_coords->get_tile_width()) / (float)(type->num_pins + type->capacity);
20722072
offset = (ipin + k + 1) * step;
20732073

2074-
switch (node->side()) {
2074+
switch (node.side()) {
20752075
case LEFT:
20762076
yc += offset;
20772077
break;
@@ -2092,7 +2092,7 @@ void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen) {
20922092

20932093
default:
20942094
vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__,
2095-
"in draw_get_rr_pin_coords: Unexpected side %s.\n", node->side_string());
2095+
"in draw_get_rr_pin_coords: Unexpected side %s.\n", node.side_string());
20962096
break;
20972097
}
20982098

‎vpr/src/draw/draw.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ void free_draw_structs();
3232
#ifndef NO_GRAPHICS
3333

3434
void draw_get_rr_pin_coords(int inode, float* xcen, float* ycen);
35-
void draw_get_rr_pin_coords(const t_rr_node* node, float* xcen, float* ycen);
35+
void draw_get_rr_pin_coords(const t_rr_node node, float* xcen, float* ycen);
3636

3737
void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d start, ezgl::point2d end, float relative_position = 1., float arrow_size = DEFAULT_ARROW_SIZE);
3838
void draw_triangle_along_line(ezgl::renderer* g, ezgl::point2d loc, ezgl::point2d start, ezgl::point2d end, float arrow_size = DEFAULT_ARROW_SIZE);

‎vpr/src/power/power.cpp

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -815,19 +815,19 @@ static void power_usage_routing(t_power_usage* power_usage,
815815
t_trace* trace;
816816

817817
for (trace = route_ctx.trace[net_id].head; trace != nullptr; trace = trace->next) {
818-
auto node = &device_ctx.rr_nodes[trace->index];
818+
auto node = device_ctx.rr_nodes[trace->index];
819819
t_rr_node_power* node_power = &rr_node_power[trace->index];
820820

821821
if (node_power->visited) {
822822
continue;
823823
}
824824

825-
for (t_edge_size edge_idx = 0; edge_idx < node->num_edges(); edge_idx++) {
826-
if (node->edge_sink_node(edge_idx) != OPEN) {
827-
auto next_node = &device_ctx.rr_nodes[node->edge_sink_node(edge_idx)];
828-
t_rr_node_power* next_node_power = &rr_node_power[node->edge_sink_node(edge_idx)];
825+
for (t_edge_size edge_idx = 0; edge_idx < node.num_edges(); edge_idx++) {
826+
if (node.edge_sink_node(edge_idx) != OPEN) {
827+
auto next_node = device_ctx.rr_nodes[node.edge_sink_node(edge_idx)];
828+
t_rr_node_power* next_node_power = &rr_node_power[node.edge_sink_node(edge_idx)];
829829

830-
switch (next_node->type()) {
830+
switch (next_node.type()) {
831831
case CHANX:
832832
case CHANY:
833833
case IPIN:
@@ -837,9 +837,9 @@ static void power_usage_routing(t_power_usage* power_usage,
837837
next_node_power->in_dens[next_node_power->num_inputs] = clb_net_density(node_power->net_num);
838838
next_node_power->in_prob[next_node_power->num_inputs] = clb_net_prob(node_power->net_num);
839839
next_node_power->num_inputs++;
840-
if (next_node_power->num_inputs > next_node->fan_in()) {
840+
if (next_node_power->num_inputs > next_node.fan_in()) {
841841
VTR_LOG("%d %d\n", next_node_power->num_inputs,
842-
next_node->fan_in());
842+
next_node.fan_in());
843843
fflush(nullptr);
844844
VTR_ASSERT(0);
845845
}
@@ -857,7 +857,7 @@ static void power_usage_routing(t_power_usage* power_usage,
857857
/* Calculate power of all routing entities */
858858
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
859859
t_power_usage sub_power_usage;
860-
auto node = &device_ctx.rr_nodes[rr_node_idx];
860+
auto node = device_ctx.rr_nodes[rr_node_idx];
861861
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
862862
float C_wire;
863863
float buffer_size;
@@ -866,7 +866,7 @@ static void power_usage_routing(t_power_usage* power_usage,
866866
//float C_per_seg_split;
867867
int wire_length;
868868

869-
switch (node->type()) {
869+
switch (node.type()) {
870870
case SOURCE:
871871
case SINK:
872872
case OPIN:
@@ -877,13 +877,13 @@ static void power_usage_routing(t_power_usage* power_usage,
877877
* - Driver (accounted for at end of CHANX/Y - see below)
878878
* - Multiplexor */
879879

880-
if (node->fan_in()) {
880+
if (node.fan_in()) {
881881
VTR_ASSERT(node_power->in_dens);
882882
VTR_ASSERT(node_power->in_prob);
883883

884884
/* Multiplexor */
885885
power_usage_mux_multilevel(&sub_power_usage,
886-
power_get_mux_arch(node->fan_in(),
886+
power_get_mux_arch(node.fan_in(),
887887
power_ctx.arch->mux_transistor_size),
888888
node_power->in_prob, node_power->in_dens,
889889
node_power->selected_input, true,
@@ -904,19 +904,19 @@ static void power_usage_routing(t_power_usage* power_usage,
904904
VTR_ASSERT(node_power->in_prob);
905905

906906
wire_length = 0;
907-
if (node->type() == CHANX) {
908-
wire_length = node->xhigh() - node->xlow() + 1;
909-
} else if (node->type() == CHANY) {
910-
wire_length = node->yhigh() - node->ylow() + 1;
907+
if (node.type() == CHANX) {
908+
wire_length = node.xhigh() - node.xlow() + 1;
909+
} else if (node.type() == CHANY) {
910+
wire_length = node.yhigh() - node.ylow() + 1;
911911
}
912912
C_wire = wire_length
913-
* segment_inf[device_ctx.rr_indexed_data[node->cost_index()].seg_index].Cmetal;
913+
* segment_inf[device_ctx.rr_indexed_data[node.cost_index()].seg_index].Cmetal;
914914
//(double)power_ctx.commonly_used->tile_length);
915-
VTR_ASSERT(node_power->selected_input < node->fan_in());
915+
VTR_ASSERT(node_power->selected_input < node.fan_in());
916916

917917
/* Multiplexor */
918918
power_usage_mux_multilevel(&sub_power_usage,
919-
power_get_mux_arch(node->fan_in(),
919+
power_get_mux_arch(node.fan_in(),
920920
power_ctx.arch->mux_transistor_size),
921921
node_power->in_prob, node_power->in_dens,
922922
node_power->selected_input, true, power_ctx.solution_inf.T_crit);
@@ -979,10 +979,10 @@ static void power_usage_routing(t_power_usage* power_usage,
979979
/* Determine types of switches that this wire drives */
980980
connectionbox_fanout = 0;
981981
switchbox_fanout = 0;
982-
for (t_edge_size iedge = 0; iedge < node->num_edges(); iedge++) {
983-
if (node->edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
982+
for (t_edge_size iedge = 0; iedge < node.num_edges(); iedge++) {
983+
if (node.edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
984984
connectionbox_fanout++;
985-
} else if (node->edge_switch(iedge) == routing_arch->delayless_switch) {
985+
} else if (node.edge_switch(iedge) == routing_arch->delayless_switch) {
986986
/* Do nothing */
987987
} else {
988988
switchbox_fanout++;
@@ -1205,37 +1205,37 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
12051205
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
12061206
int fanout_to_IPIN = 0;
12071207
int fanout_to_seg = 0;
1208-
auto node = &device_ctx.rr_nodes[rr_node_idx];
1208+
auto node = device_ctx.rr_nodes[rr_node_idx];
12091209
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
12101210

1211-
switch (node->type()) {
1211+
switch (node.type()) {
12121212
case IPIN:
12131213
max_IPIN_fanin = std::max(max_IPIN_fanin,
1214-
static_cast<int>(node->fan_in()));
1215-
max_fanin = std::max(max_fanin, static_cast<int>(node->fan_in()));
1214+
static_cast<int>(node.fan_in()));
1215+
max_fanin = std::max(max_fanin, static_cast<int>(node.fan_in()));
12161216

1217-
node_power->in_dens = (float*)vtr::calloc(node->fan_in(),
1217+
node_power->in_dens = (float*)vtr::calloc(node.fan_in(),
12181218
sizeof(float));
1219-
node_power->in_prob = (float*)vtr::calloc(node->fan_in(),
1219+
node_power->in_prob = (float*)vtr::calloc(node.fan_in(),
12201220
sizeof(float));
12211221
break;
12221222
case CHANX:
12231223
case CHANY:
1224-
for (t_edge_size iedge = 0; iedge < node->num_edges(); iedge++) {
1225-
if (node->edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
1224+
for (t_edge_size iedge = 0; iedge < node.num_edges(); iedge++) {
1225+
if (node.edge_switch(iedge) == routing_arch->wire_to_rr_ipin_switch) {
12261226
fanout_to_IPIN++;
1227-
} else if (node->edge_switch(iedge) != routing_arch->delayless_switch) {
1227+
} else if (node.edge_switch(iedge) != routing_arch->delayless_switch) {
12281228
fanout_to_seg++;
12291229
}
12301230
}
12311231
max_seg_to_IPIN_fanout = std::max(max_seg_to_IPIN_fanout,
12321232
fanout_to_IPIN);
12331233
max_seg_to_seg_fanout = std::max(max_seg_to_seg_fanout, fanout_to_seg);
1234-
max_fanin = std::max(max_fanin, static_cast<int>(node->fan_in()));
1234+
max_fanin = std::max(max_fanin, static_cast<int>(node.fan_in()));
12351235

1236-
node_power->in_dens = (float*)vtr::calloc(node->fan_in(),
1236+
node_power->in_dens = (float*)vtr::calloc(node.fan_in(),
12371237
sizeof(float));
1238-
node_power->in_prob = (float*)vtr::calloc(node->fan_in(),
1238+
node_power->in_prob = (float*)vtr::calloc(node.fan_in(),
12391239
sizeof(float));
12401240
break;
12411241
default:
@@ -1254,14 +1254,14 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
12541254

12551255
/* Populate driver switch type */
12561256
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
1257-
auto node = &device_ctx.rr_nodes[rr_node_idx];
1257+
auto node = device_ctx.rr_nodes[rr_node_idx];
12581258

1259-
for (t_edge_size edge_idx = 0; edge_idx < node->num_edges(); edge_idx++) {
1260-
if (node->edge_sink_node(edge_idx) != OPEN) {
1261-
if (rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
1262-
rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type = node->edge_switch(edge_idx);
1259+
for (t_edge_size edge_idx = 0; edge_idx < node.num_edges(); edge_idx++) {
1260+
if (node.edge_sink_node(edge_idx) != OPEN) {
1261+
if (rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type == OPEN) {
1262+
rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type = node.edge_switch(edge_idx);
12631263
} else {
1264-
VTR_ASSERT(rr_node_power[node->edge_sink_node(edge_idx)].driver_switch_type == node->edge_switch(edge_idx));
1264+
VTR_ASSERT(rr_node_power[node.edge_sink_node(edge_idx)].driver_switch_type == node.edge_switch(edge_idx));
12651265
}
12661266
}
12671267
}
@@ -1270,13 +1270,13 @@ void power_routing_init(const t_det_routing_arch* routing_arch) {
12701270
/* Find Max Fanout of Routing Buffer */
12711271
t_edge_size max_seg_fanout = 0;
12721272
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
1273-
auto node = &device_ctx.rr_nodes[rr_node_idx];
1273+
auto node = device_ctx.rr_nodes[rr_node_idx];
12741274

1275-
switch (node->type()) {
1275+
switch (node.type()) {
12761276
case CHANX:
12771277
case CHANY:
1278-
if (node->num_edges() > max_seg_fanout) {
1279-
max_seg_fanout = node->num_edges();
1278+
if (node.num_edges() > max_seg_fanout) {
1279+
max_seg_fanout = node.num_edges();
12801280
}
12811281
break;
12821282
default:
@@ -1358,14 +1358,14 @@ bool power_uninit() {
13581358
bool error = false;
13591359

13601360
for (size_t rr_node_idx = 0; rr_node_idx < device_ctx.rr_nodes.size(); rr_node_idx++) {
1361-
auto node = &device_ctx.rr_nodes[rr_node_idx];
1361+
auto node = device_ctx.rr_nodes[rr_node_idx];
13621362
t_rr_node_power* node_power = &rr_node_power[rr_node_idx];
13631363

1364-
switch (node->type()) {
1364+
switch (node.type()) {
13651365
case CHANX:
13661366
case CHANY:
13671367
case IPIN:
1368-
if (node->fan_in()) {
1368+
if (node.fan_in()) {
13691369
free(node_power->in_dens);
13701370
free(node_power->in_prob);
13711371
}

‎vpr/src/route/clock_network_builders.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -310,7 +310,7 @@ int ClockRib::create_chanx_wire(int x_start,
310310
t_rr_node_storage* rr_nodes) {
311311
rr_nodes->emplace_back();
312312
auto node_index = rr_nodes->size() - 1;
313-
auto& node = rr_nodes->back();
313+
auto node = rr_nodes->back();
314314

315315
node.set_coordinates(x_start, y, x_end, y);
316316
node.set_type(CHANX);
@@ -600,7 +600,7 @@ int ClockSpine::create_chany_wire(int y_start,
600600
int num_segments) {
601601
rr_nodes->emplace_back();
602602
auto node_index = rr_nodes->size() - 1;
603-
auto& node = rr_nodes->back();
603+
auto node = rr_nodes->back();
604604

605605
node.set_coordinates(x, y_start, x, y_end);
606606
node.set_type(CHANY);

‎vpr/src/route/rr_graph.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -931,7 +931,7 @@ static void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin
931931
auto& device_ctx = g_vpr_ctx.mutable_device();
932932

933933
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
934-
auto& from_node = device_ctx.rr_nodes[inode];
934+
auto from_node = device_ctx.rr_nodes[inode];
935935
int num_edges = from_node.num_edges();
936936
for (int iedge = 0; iedge < num_edges; iedge++) {
937937
const t_rr_node& to_node = device_ctx.rr_nodes[from_node.edge_sink_node(iedge)];

‎vpr/src/route/rr_graph_reader.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -262,7 +262,7 @@ void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
262262

263263
while (rr_node) {
264264
id = get_attribute(rr_node, "id", loc_data).as_int();
265-
auto& node = device_ctx.rr_nodes[id];
265+
auto node = device_ctx.rr_nodes[id];
266266

267267
segmentSubnode = get_single_child(rr_node, "segment", loc_data, pugiutil::OPTIONAL);
268268
if (segmentSubnode) {
@@ -289,7 +289,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
289289

290290
while (rr_node) {
291291
int inode = get_attribute(rr_node, "id", loc_data).as_int();
292-
auto& node = device_ctx.rr_nodes[inode];
292+
auto node = device_ctx.rr_nodes[inode];
293293

294294
const char* node_type = get_attribute(rr_node, "type", loc_data).as_string();
295295
if (strcmp(node_type, "CHANX") == 0) {
@@ -726,7 +726,7 @@ void process_rr_node_indices(const DeviceGrid& grid) {
726726
* Note that CHANX and CHANY 's x and y are swapped due to the chan and seg convention.
727727
*/
728728
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
729-
auto& node = device_ctx.rr_nodes[inode];
729+
auto node = device_ctx.rr_nodes[inode];
730730
if (node.type() == SOURCE || node.type() == SINK) {
731731
for (int ix = node.xlow(); ix <= node.xhigh(); ix++) {
732732
for (int iy = node.ylow(); iy <= node.yhigh(); iy++) {
@@ -788,7 +788,7 @@ void process_rr_node_indices(const DeviceGrid& grid) {
788788
int count;
789789
/* CHANX and CHANY need to reevaluated with its ptc num as the correct index*/
790790
for (size_t inode = 0; inode < device_ctx.rr_nodes.size(); inode++) {
791-
auto& node = device_ctx.rr_nodes[inode];
791+
auto node = device_ctx.rr_nodes[inode];
792792
if (node.type() == CHANX) {
793793
for (int iy = node.ylow(); iy <= node.yhigh(); iy++) {
794794
for (int ix = node.xlow(); ix <= node.xhigh(); ix++) {
@@ -863,7 +863,7 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data,
863863

864864
while (rr_node) {
865865
int inode = get_attribute(rr_node, "id", loc_data).as_int();
866-
auto& node = device_ctx.rr_nodes[inode];
866+
auto node = device_ctx.rr_nodes[inode];
867867

868868
/*CHANX and CHANY cost index is dependent on the segment id*/
869869

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