Move call location of ClockRRGraphBuilder and use alloc_and_load_edges.

By moving ClockRRGraphBuilder earlier in the rr graph flow, several
parts of ClockRRGraphBuilder::create_and_append_clock_rr_graph can be
avoided, as they were duplicating work that the original build_rr_graph
flow was already doing (init_fan, mapping arch switch to rr switch,
partition_edges).

This new code should also fully preallocate the rr_node array, though
this is not required by the code.

Signed-off-by: Keith Rothman <[email protected]>

Author: litghost

vpr/src/route/clock_connection_builders.cpp

@@ -39,18 +39,24 @@ void RoutingToClockConnection::set_fc_val(float fc_val) {
  * RoutingToClockConnection (member functions)
  */
 
-void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_graph) {
+size_t RoutingToClockConnection::estimate_additional_nodes() {
+    return 1;
+}
+
+void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) {
     // Initialize random seed
     // Must be done durring every call inorder for restored rr_graphs after a binary
     // search to be consistant
     std::srand(seed);
 
-    auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
+    auto& device_ctx = g_vpr_ctx.device();
     auto& rr_node_indices = device_ctx.rr_node_indices;
 
     int virtual_clock_network_root_idx = create_virtual_clock_network_sink_node(switch_location.x, switch_location.y);
-    device_ctx.virtual_clock_network_root_idx = virtual_clock_network_root_idx;
+    {
+        auto& mut_device_ctx = g_vpr_ctx.mutable_device();
+        mut_device_ctx.virtual_clock_network_root_idx = virtual_clock_network_root_idx;
+    }
 
     // rr_node indices for x and y channel routing wires and clock wires to connect to
     auto x_wire_indices = get_rr_node_chan_wires_at_location(
@@ -68,18 +74,18 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
         // Connect to x-channel wires
         unsigned num_wires_x = x_wire_indices.size() * fc;
         for (size_t i = 0; i < num_wires_x; i++) {
-            rr_nodes[x_wire_indices[i]].add_edge(clock_index, rr_switch_idx);
+            rr_edges_to_create->emplace_back(x_wire_indices[i], clock_index, rr_switch_idx);
         }
 
         // Connect to y-channel wires
         unsigned num_wires_y = y_wire_indices.size() * fc;
         for (size_t i = 0; i < num_wires_y; i++) {
-            rr_nodes[y_wire_indices[i]].add_edge(clock_index, rr_switch_idx);
+            rr_edges_to_create->emplace_back(y_wire_indices[i], clock_index, rr_switch_idx);
         }
 
         // Connect to virtual clock sink node
         // used by the two stage router
-        rr_nodes[clock_index].add_edge(virtual_clock_network_root_idx, rr_switch_idx);
+        rr_edges_to_create->emplace_back(clock_index, virtual_clock_network_root_idx, rr_switch_idx);
     }
 }
 
@@ -134,10 +140,13 @@ void ClockToClockConneciton::set_fc_val(float fc_val) {
  * ClockToClockConneciton (member functions)
  */
 
-void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_graph) {
-    auto& device_ctx = g_vpr_ctx.mutable_device();
+size_t ClockToClockConneciton::estimate_additional_nodes() {
+    return 0;
+}
+
+void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) {
+    auto& device_ctx = g_vpr_ctx.device();
     auto& grid = device_ctx.grid;
-    auto& rr_nodes = device_ctx.rr_nodes;
 
     auto to_locations = clock_graph.get_switch_locations(to_clock, to_switch);
 
@@ -179,7 +188,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr
                 if (from_itter == from_rr_node_indices.end()) {
                     from_itter = from_rr_node_indices.begin();
                 }
-                rr_nodes[*from_itter].add_edge(to_index, rr_switch_idx);
+                rr_edges_to_create->emplace_back(*from_itter, to_index, rr_switch_idx);
                 from_itter++;
             }
         }
@@ -211,9 +220,12 @@ void ClockToPinsConnection::set_fc_val(float fc_val) {
  * ClockToPinsConnection (member functions)
  */
 
-void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_graph) {
-    auto& device_ctx = g_vpr_ctx.mutable_device();
-    auto& rr_nodes = device_ctx.rr_nodes;
+size_t ClockToPinsConnection::estimate_additional_nodes() {
+    return 0;
+}
+
+void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) {
+    auto& device_ctx = g_vpr_ctx.device();
     auto& rr_node_indices = device_ctx.rr_node_indices;
     auto& grid = device_ctx.grid;
 
@@ -290,7 +302,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
 
                     //Create edges depending on Fc
                     for (size_t i = 0; i < clock_network_indices.size() * fc; i++) {
-                        rr_nodes[clock_network_indices[i]].add_edge(clock_pin_node_idx, rr_switch_idx);
+                        rr_edges_to_create->emplace_back(clock_network_indices[i], clock_pin_node_idx, rr_switch_idx);
                     }
                 }
             }

vpr/src/route/clock_connection_builders.h

@@ -5,6 +5,7 @@
 
 #include "clock_fwd.h"
 
+#include "rr_graph2.h"
 #include "rr_graph_clock.h"
 
 class ClockRRGraphBuilder;
@@ -26,7 +27,8 @@ class ClockConnection {
     /*
      * Member functions
      */
-    virtual void create_switches(const ClockRRGraphBuilder& clock_graph) = 0;
+    virtual void create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) = 0;
+    virtual size_t estimate_additional_nodes() = 0;
 };
 
 class RoutingToClockConnection : public ClockConnection {
@@ -53,7 +55,8 @@ class RoutingToClockConnection : public ClockConnection {
      * Member functions
      */
     /* Connects the inter-block routing to the clock source at the specified coordinates */
-    void create_switches(const ClockRRGraphBuilder& clock_graph);
+    void create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) override;
+    size_t estimate_additional_nodes() override;
     int create_virtual_clock_network_sink_node(int x, int y);
 };
 
@@ -81,7 +84,8 @@ class ClockToClockConneciton : public ClockConnection {
      * Member functions
      */
     /* Connects a clock tap to a clock source */
-    void create_switches(const ClockRRGraphBuilder& clock_graph);
+    void create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) override;
+    size_t estimate_additional_nodes() override;
 };
 
 /* This class currently only supports Clock Network to clock pin connection.
@@ -106,7 +110,8 @@ class ClockToPinsConnection : public ClockConnection {
      * Member functions
      */
     /* Connects the clock tap to block pins */
-    void create_switches(const ClockRRGraphBuilder& clock_graph);
+    void create_switches(const ClockRRGraphBuilder& clock_graph, t_rr_edge_info_set* rr_edges_to_create) override;
+    size_t estimate_additional_nodes() override;
 };
 
 #endif