[test] now use L1 and L4 in the tileable arch

Author: tangxifan

vtr_flow/arch/timing/k4_N4_tileable_90nm.xml

@@ -73,11 +73,16 @@
     <switch type="mux" name="ipin_cblock" R="1055.232544" Cout="0." Cin="0.000000e+00" Tdel="8.045000e-11" mux_trans_size="0.983352" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <segment freq="1.000000" length="1" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
+    <segment freq="0.500000" length="1" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
       <mux name="0"/>
       <sb type="pattern">1 1</sb>
       <cb type="pattern">1</cb>
     </segment>
+    <segment freq="0.500000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
   </segmentlist>
   <complexblocklist>
     <!-- Define I/O pads begin -->