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SamuelHo10SamuelHo10
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replaced most of the callocs with news
1 parent 2f679a7 commit 0bdb49f

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3 files changed

+49
-62
lines changed

3 files changed

+49
-62
lines changed

‎libs/libarchfpga/src/arch_util.cpp‎

Lines changed: 28 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ void free_arch(t_arch* arch) {
163163
vtr::free(arch->architecture_id);
164164

165165
if (arch->clocks) {
166-
vtr::free(arch->clocks->clock_inf);
166+
delete[] arch->clocks->clock_inf;
167167
}
168168

169169
delete (arch->noc);
@@ -336,16 +336,16 @@ static void free_pb_type(t_pb_type* pb_type) {
336336
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value[m]);
337337
}
338338
delete[] pb_type->modes[i].interconnect[j].annotations[k].prop;
339-
vtr::free(pb_type->modes[i].interconnect[j].annotations[k].value);
339+
delete[] pb_type->modes[i].interconnect[j].annotations[k].value;
340340
}
341-
vtr::free(pb_type->modes[i].interconnect[j].annotations);
341+
delete[] pb_type->modes[i].interconnect[j].annotations;
342342
if (pb_type->modes[i].interconnect[j].interconnect_power)
343-
vtr::free(pb_type->modes[i].interconnect[j].interconnect_power);
343+
delete pb_type->modes[i].interconnect[j].interconnect_power;
344344
}
345345
if (pb_type->modes[i].interconnect)
346346
delete[] pb_type->modes[i].interconnect;
347347
if (pb_type->modes[i].mode_power)
348-
vtr::free(pb_type->modes[i].mode_power);
348+
delete (pb_type->modes[i].mode_power);
349349
}
350350
if (pb_type->modes)
351351
delete[] pb_type->modes;
@@ -354,7 +354,7 @@ static void free_pb_type(t_pb_type* pb_type) {
354354
for (int j = 0; j < pb_type->annotations[i].num_value_prop_pairs; ++j) {
355355
vtr::free(pb_type->annotations[i].value[j]);
356356
}
357-
vtr::free(pb_type->annotations[i].value);
357+
delete[] pb_type->annotations[i].value;
358358
delete[] pb_type->annotations[i].prop;
359359
if (pb_type->annotations[i].input_pins) {
360360
vtr::free(pb_type->annotations[i].input_pins);
@@ -371,7 +371,7 @@ static void free_pb_type(t_pb_type* pb_type) {
371371
}
372372

373373
if (pb_type->pb_type_power) {
374-
vtr::free(pb_type->pb_type_power);
374+
delete pb_type->pb_type_power;
375375
}
376376

377377
for (int i = 0; i < pb_type->num_ports; ++i) {
@@ -380,10 +380,10 @@ static void free_pb_type(t_pb_type* pb_type) {
380380
vtr::free(pb_type->ports[i].port_class);
381381
}
382382
if (pb_type->ports[i].port_power) {
383-
vtr::free(pb_type->ports[i].port_power);
383+
delete pb_type->ports[i].port_power;
384384
}
385385
}
386-
vtr::free(pb_type->ports);
386+
delete[] pb_type->ports;
387387
}
388388

389389
t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, int* low_index) {
@@ -495,13 +495,12 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
495495
copy->num_pb = 1;
496496

497497
/* Power */
498-
copy->pb_type_power = (t_pb_type_power*)vtr::calloc(1,
499-
sizeof(t_pb_type_power));
498+
copy->pb_type_power = new t_pb_type_power();
500499
copy->pb_type_power->estimation_method = power_method_inherited(pb_type->pb_type_power->estimation_method);
501500

502501
/* Ports */
503502
copy->num_ports = pb_type->num_ports;
504-
copy->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port));
503+
copy->ports = new t_port[pb_type->num_ports]();
505504
for (i = 0; i < pb_type->num_ports; i++) {
506505
copy->ports[i].is_clock = pb_type->ports[i].is_clock;
507506
copy->ports[i].model_port = pb_type->ports[i].model_port;
@@ -514,8 +513,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
514513
copy->ports[i].index = pb_type->ports[i].index;
515514
copy->ports[i].absolute_first_pin_index = pb_type->ports[i].absolute_first_pin_index;
516515

517-
copy->ports[i].port_power = (t_port_power*)vtr::calloc(1,
518-
sizeof(t_port_power));
516+
copy->ports[i].port_power = new t_port_power();
519517
//Defaults
520518
if (copy->pb_type_power->estimation_method == POWER_METHOD_AUTO_SIZES) {
521519
copy->ports[i].port_power->wire_type = POWER_WIRE_TYPE_AUTO;
@@ -550,7 +548,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
550548
copy->annotations[i].type = pb_type->annotations[i].type;
551549
copy->annotations[i].num_value_prop_pairs = pb_type->annotations[i].num_value_prop_pairs;
552550
copy->annotations[i].prop = new int[pb_type->annotations[i].num_value_prop_pairs];
553-
copy->annotations[i].value = (char**)vtr::malloc(sizeof(char*) * pb_type->annotations[i].num_value_prop_pairs);
551+
copy->annotations[i].value = new char*[pb_type->annotations[i].num_value_prop_pairs];
554552
for (j = 0; j < pb_type->annotations[i].num_value_prop_pairs; j++) {
555553
copy->annotations[i].prop[j] = pb_type->annotations[i].prop[j];
556554
copy->annotations[i].value[j] = vtr::strdup(pb_type->annotations[i].value[j]);
@@ -580,8 +578,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
580578
lut_pb_type->modes[0].parent_pb_type = lut_pb_type;
581579
lut_pb_type->modes[0].index = 0;
582580
lut_pb_type->modes[0].num_pb_type_children = 0;
583-
lut_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1,
584-
sizeof(t_mode_power));
581+
lut_pb_type->modes[0].mode_power = new t_mode_power();
585582

586583
/* Process interconnect */
587584
/* TODO: add timing annotations to route-through */
@@ -613,10 +610,9 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
613610

614611
lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0;
615612
lut_pb_type->modes[0].interconnect[0].parent_mode = &lut_pb_type->modes[0];
616-
lut_pb_type->modes[0].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
613+
lut_pb_type->modes[0].interconnect[0].interconnect_power = new t_interconnect_power();
617614

618-
lut_pb_type->modes[0].interconnect[0].annotations = (t_pin_to_pin_annotation*)vtr::calloc(lut_pb_type->num_annotations,
619-
sizeof(t_pin_to_pin_annotation));
615+
lut_pb_type->modes[0].interconnect[0].annotations = new t_pin_to_pin_annotation[lut_pb_type->num_annotations]();
620616
lut_pb_type->modes[0].interconnect[0].num_annotations = lut_pb_type->num_annotations;
621617
for (i = 0; i < lut_pb_type->modes[0].interconnect[0].num_annotations;
622618
i++) {
@@ -628,8 +624,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
628624
lut_pb_type->modes[0].interconnect[0].annotations[i].type = lut_pb_type->annotations[i].type;
629625
lut_pb_type->modes[0].interconnect[0].annotations[i].num_value_prop_pairs = lut_pb_type->annotations[i].num_value_prop_pairs;
630626
lut_pb_type->modes[0].interconnect[0].annotations[i].prop = new int[lut_pb_type->annotations[i].num_value_prop_pairs];
631-
lut_pb_type->modes[0].interconnect[0].annotations[i].value = (char**)vtr::malloc(sizeof(char*)
632-
* lut_pb_type->annotations[i].num_value_prop_pairs);
627+
lut_pb_type->modes[0].interconnect[0].annotations[i].value = new char*[lut_pb_type->annotations[i].num_value_prop_pairs];
633628
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
634629
lut_pb_type->modes[0].interconnect[0].annotations[i].prop[j] = lut_pb_type->annotations[i].prop[j];
635630
lut_pb_type->modes[0].interconnect[0].annotations[i].value[j] = vtr::strdup(lut_pb_type->annotations[i].value[j]);
@@ -642,26 +637,25 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
642637
lut_pb_type->modes[1].parent_pb_type = lut_pb_type;
643638
lut_pb_type->modes[1].index = 1;
644639
lut_pb_type->modes[1].num_pb_type_children = 1;
645-
lut_pb_type->modes[1].mode_power = (t_mode_power*)vtr::calloc(1,
646-
sizeof(t_mode_power));
640+
lut_pb_type->modes[1].mode_power = new t_mode_power();
647641
lut_pb_type->modes[1].pb_type_children = new t_pb_type[1];
648642
alloc_and_load_default_child_for_pb_type(lut_pb_type, default_name,
649643
lut_pb_type->modes[1].pb_type_children);
650644
/* moved annotations to child so delete old annotations */
651645
for (i = 0; i < lut_pb_type->num_annotations; i++) {
652646
for (j = 0; j < lut_pb_type->annotations[i].num_value_prop_pairs; j++) {
653-
free(lut_pb_type->annotations[i].value[j]);
647+
vtr::free(lut_pb_type->annotations[i].value[j]);
654648
}
655-
free(lut_pb_type->annotations[i].value);
649+
delete[] lut_pb_type->annotations[i].value;
656650
delete[] lut_pb_type->annotations[i].prop;
657651
if (lut_pb_type->annotations[i].input_pins) {
658-
free(lut_pb_type->annotations[i].input_pins);
652+
vtr::free(lut_pb_type->annotations[i].input_pins);
659653
}
660654
if (lut_pb_type->annotations[i].output_pins) {
661-
free(lut_pb_type->annotations[i].output_pins);
655+
vtr::free(lut_pb_type->annotations[i].output_pins);
662656
}
663657
if (lut_pb_type->annotations[i].clock) {
664-
free(lut_pb_type->annotations[i].clock);
658+
vtr::free(lut_pb_type->annotations[i].clock);
665659
}
666660
}
667661
lut_pb_type->num_annotations = 0;
@@ -693,7 +687,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
693687

694688
lut_pb_type->modes[1].interconnect[0].parent_mode_index = 1;
695689
lut_pb_type->modes[1].interconnect[0].parent_mode = &lut_pb_type->modes[1];
696-
lut_pb_type->modes[1].interconnect[0].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
690+
lut_pb_type->modes[1].interconnect[0].interconnect_power = new t_interconnect_power();
697691

698692
lut_pb_type->modes[1].interconnect[1].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 11, sizeof(char));
699693
sprintf(lut_pb_type->modes[1].interconnect[1].name, "direct:%s",
@@ -712,7 +706,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
712706

713707
lut_pb_type->modes[1].interconnect[1].parent_mode_index = 1;
714708
lut_pb_type->modes[1].interconnect[1].parent_mode = &lut_pb_type->modes[1];
715-
lut_pb_type->modes[1].interconnect[1].interconnect_power = (t_interconnect_power*)vtr::calloc(1, sizeof(t_interconnect_power));
709+
lut_pb_type->modes[1].interconnect[1].interconnect_power = new t_interconnect_power();
716710

717711
free(default_name);
718712

@@ -737,8 +731,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
737731
mem_pb_type->modes[0].name = vtr::strdup(default_name);
738732
mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
739733
mem_pb_type->modes[0].index = 0;
740-
mem_pb_type->modes[0].mode_power = (t_mode_power*)vtr::calloc(1,
741-
sizeof(t_mode_power));
734+
mem_pb_type->modes[0].mode_power = new t_mode_power();
742735
num_pb = OPEN;
743736
for (i = 0; i < mem_pb_type->num_ports; i++) {
744737
if (mem_pb_type->ports[i].port_class != nullptr
@@ -834,8 +827,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
834827
}
835828

836829
/* Allocate interconnect power structures */
837-
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
838-
sizeof(t_interconnect_power));
830+
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
839831
i_inter++;
840832
} else {
841833
for (j = 0; j < num_pb; j++) {
@@ -875,8 +867,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
875867
}
876868

877869
/* Allocate interconnect power structures */
878-
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
879-
sizeof(t_interconnect_power));
870+
mem_pb_type->modes[0].interconnect[i_inter].interconnect_power = new t_interconnect_power();
880871
i_inter++;
881872
}
882873
}

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,7 @@ static t_port get_generic_port(t_arch* arch,
219219
port.is_non_clock_global = false;
220220
port.model_port = nullptr;
221221
port.port_class = vtr::strdup(nullptr);
222-
port.port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power));
222+
port.port_power = new t_port_power();
223223

224224
if (!model.empty())
225225
port.model_port = get_model_port(arch, model, name);
@@ -243,8 +243,8 @@ static bool block_port_exists(t_pb_type* pb_type, std::string port_name) {
243243
static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string input, std::string output) {
244244
t_pin_to_pin_annotation pp;
245245

246-
pp.prop = (int*)vtr::calloc(1, sizeof(int));
247-
pp.value = (char**)vtr::calloc(1, sizeof(char*));
246+
pp.prop = new int();
247+
pp.value = new char*();
248248

249249
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
250250
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
@@ -1293,7 +1293,7 @@ struct ArchReader {
12931293
lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES);
12941294

12951295
lut->num_ports = 2;
1296-
lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port));
1296+
lut->ports = new t_port[lut->num_ports]();
12971297
lut->ports[0] = get_generic_port(arch_, lut, IN_PORT, "in", LogicalModels::MODEL_NAMES, width);
12981298
lut->ports[1] = get_generic_port(arch_, lut, OUT_PORT, "out", LogicalModels::MODEL_NAMES);
12991299

@@ -1377,7 +1377,7 @@ struct ArchReader {
13771377
port->name = is_input ? vtr::strdup(ipin.c_str()) : vtr::strdup(opin.c_str());
13781378
port->model_port = nullptr;
13791379
port->port_class = vtr::strdup(nullptr);
1380-
port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power));
1380+
port->port_power = new t_port_power();
13811381
}
13821382

13831383
// OPAD mode
@@ -1395,7 +1395,7 @@ struct ArchReader {
13951395

13961396
num_ports = 1;
13971397
opad->num_ports = num_ports;
1398-
opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
1398+
opad->ports = new t_port[num_ports]();
13991399
opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT);
14001400
opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT);
14011401

@@ -1417,7 +1417,7 @@ struct ArchReader {
14171417

14181418
num_ports = 1;
14191419
ipad->num_ports = num_ports;
1420-
ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
1420+
ipad->ports = new t_port[num_ports]();
14211421
ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT);
14221422
ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT);
14231423

@@ -1544,7 +1544,7 @@ struct ArchReader {
15441544

15451545
int num_ports = ic_count;
15461546
leaf->num_ports = num_ports;
1547-
leaf->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
1547+
leaf->ports = new t_port[num_ports]();
15481548
leaf->blif_model = vtr::strdup((std::string(".subckt ") + name).c_str());
15491549
leaf->model_id = get_model(arch_, name);
15501550

@@ -2082,7 +2082,7 @@ struct ArchReader {
20822082
pb_type->modes = new t_mode[pb_type->num_modes];
20832083

20842084
pb_type->num_ports = 2;
2085-
pb_type->ports = (t_port*)vtr::calloc(pb_type->num_ports, sizeof(t_port));
2085+
pb_type->ports = new t_port[pb_type->num_ports]();
20862086

20872087
pb_type->num_output_pins = 2;
20882088
pb_type->num_input_pins = 0;
@@ -2118,7 +2118,7 @@ struct ArchReader {
21182118

21192119
int num_ports = 1;
21202120
leaf_pb_type->num_ports = num_ports;
2121-
leaf_pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
2121+
leaf_pb_type->ports = new t_port[num_ports]();
21222122
leaf_pb_type->blif_model = vtr::strdup(const_cell.first.c_str());
21232123
leaf_pb_type->model_id = get_model(arch_, const_cell.first);
21242124

‎libs/libarchfpga/src/read_xml_arch_file.cpp‎

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -517,10 +517,9 @@ void XmlReadArch(const char* ArchFile,
517517
/* This information still needs to be read, even if it is just
518518
* thrown away.
519519
*/
520-
t_power_arch* power_arch_fake = (t_power_arch*)vtr::calloc(1,
521-
sizeof(t_power_arch));
520+
t_power_arch* power_arch_fake = new t_power_arch();
522521
ProcessPower(Next, power_arch_fake, loc_data);
523-
free(power_arch_fake);
522+
delete power_arch_fake;
524523
}
525524
}
526525

@@ -533,11 +532,10 @@ void XmlReadArch(const char* ArchFile,
533532
/* This information still needs to be read, even if it is just
534533
* thrown away.
535534
*/
536-
t_clock_arch* clocks_fake = (t_clock_arch*)vtr::calloc(1,
537-
sizeof(t_clock_arch));
535+
t_clock_arch* clocks_fake = new t_clock_arch();
538536
ProcessClocks(Next, clocks_fake, loc_data);
539537
delete[] clocks_fake->clock_inf;
540-
free(clocks_fake);
538+
delete clocks_fake;
541539
}
542540
}
543541

@@ -888,7 +886,7 @@ static void ProcessPinToPinAnnotations(pugi::xml_node Parent,
888886

889887
annotation->num_value_prop_pairs = i;
890888
annotation->prop = new int[i]();
891-
annotation->value = (char**)vtr::calloc(i, sizeof(char*));
889+
annotation->value = new char*[i]();
892890
annotation->line_num = loc_data.line(Parent);
893891
/* Todo: This is slow, I should use a case lookup */
894892
i = 0;
@@ -1285,7 +1283,7 @@ static void ProcessPb_Type(pugi::xml_node Parent,
12851283
const int num_out_ports = count_children(Parent, "output", loc_data, ReqOpt::OPTIONAL);
12861284
const int num_clock_ports = count_children(Parent, "clock", loc_data, ReqOpt::OPTIONAL);
12871285
const int num_ports = num_in_ports + num_out_ports + num_clock_ports;
1288-
pb_type->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
1286+
pb_type->ports = new t_port[num_ports]();
12891287
pb_type->num_ports = num_ports;
12901288

12911289
/* Enforce VPR's definition of LUT/FF by checking number of ports */
@@ -1300,7 +1298,7 @@ static void ProcessPb_Type(pugi::xml_node Parent,
13001298
}
13011299

13021300
/* Initialize Power Structure */
1303-
pb_type->pb_type_power = (t_pb_type_power*)vtr::calloc(1, sizeof(t_pb_type_power));
1301+
pb_type->pb_type_power = new t_pb_type_power();
13041302
ProcessPb_TypePowerEstMethod(Parent, pb_type, loc_data);
13051303

13061304
/* process ports */
@@ -1461,7 +1459,7 @@ static void ProcessPb_TypePort_Power(pugi::xml_node Parent, t_port* port, e_powe
14611459
const char* prop;
14621460
bool wire_defined = false;
14631461

1464-
port->port_power = (t_port_power*)vtr::calloc(1, sizeof(t_port_power));
1462+
port->port_power = new t_port_power();
14651463

14661464
//Defaults
14671465
if (power_method == POWER_METHOD_AUTO_SIZES) {
@@ -1747,8 +1745,7 @@ static void ProcessInterconnect(vtr::string_internment& strings,
17471745
num_annotations += count_children(Cur, annot_child_name, loc_data, ReqOpt::OPTIONAL);
17481746
}
17491747

1750-
mode->interconnect[interconnect_idx].annotations = (t_pin_to_pin_annotation*)vtr::calloc(num_annotations,
1751-
sizeof(t_pin_to_pin_annotation));
1748+
mode->interconnect[interconnect_idx].annotations = new t_pin_to_pin_annotation[num_annotations]();
17521749
mode->interconnect[interconnect_idx].num_annotations = num_annotations;
17531750

17541751
int annotation_idx = 0;
@@ -1767,8 +1764,7 @@ static void ProcessInterconnect(vtr::string_internment& strings,
17671764
VTR_ASSERT(annotation_idx == num_annotations);
17681765

17691766
/* Power */
1770-
mode->interconnect[interconnect_idx].interconnect_power = (t_interconnect_power*)vtr::calloc(1,
1771-
sizeof(t_interconnect_power));
1767+
mode->interconnect[interconnect_idx].interconnect_power = new t_interconnect_power();
17721768
mode->interconnect[interconnect_idx].interconnect_power->port_info_initialized = false;
17731769

17741770
/* get next iteration */
@@ -1848,7 +1844,7 @@ static void ProcessMode(pugi::xml_node Parent,
18481844
}
18491845

18501846
/* Allocate power structure */
1851-
mode->mode_power = (t_mode_power*)vtr::calloc(1, sizeof(t_mode_power));
1847+
mode->mode_power = new t_mode_power();
18521848

18531849
if (!implied_mode) {
18541850
// Implied mode metadata is attached to the pb_type, rather than

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