Skip to content

Commit 05af555

Browse files
w0lekw0lek
authored
Merge branch 'master' into vpr_viewer_and_flat_routing_on
2 parents 26118a9 + 6f4290b commit 05af555

21 files changed

+155
-157
lines changed

‎.github/workflows/test.yml

Lines changed: 89 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ jobs:
9999
run: ./dev/${{ matrix.script }}
100100

101101

102-
UniTests:
102+
UnitTests:
103103
name: 'U: C++ Unit Tests'
104104
runs-on: ubuntu-24.04
105105
steps:
@@ -125,6 +125,92 @@ jobs:
125125
run: ./.github/scripts/unittest.sh
126126

127127

128+
# This test builds different variations of VTR (with different CMake Params)
129+
# and ensures that they can run the basic regression tests. This also ensures
130+
# that these build variations are warning clean.
131+
BuildVariations:
132+
runs-on: ubuntu-24.04
133+
name: 'B: Build Variations'
134+
env:
135+
# For the CI, we want all build variations to be warning clean.
136+
# NOTE: Need to turn IPO off due to false warnings being produced.
137+
COMMON_CMAKE_PARAMS: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off'
138+
steps:
139+
140+
- uses: actions/setup-python@v5
141+
with:
142+
python-version: 3.12.3
143+
144+
- uses: actions/checkout@v4
145+
with:
146+
submodules: 'true'
147+
148+
- name: 'Get number of CPU cores'
149+
uses: SimenB/github-actions-cpu-cores@v2
150+
id: cpu-cores
151+
152+
- name: 'Install dependencies'
153+
run: ./.github/scripts/install_dependencies.sh
154+
155+
- name: 'ccache'
156+
uses: hendrikmuhs/[email protected]
157+
158+
- name: 'Test with VTR_ASSERT_LEVEL 4'
159+
if: success() || failure()
160+
env:
161+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ASSERT_LEVEL=4"
162+
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
163+
run: |
164+
rm -f build/CMakeCache.txt
165+
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
166+
make -j${{ steps.cpu-cores.outputs.count}}
167+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
168+
169+
- name: 'Test with NO_GRAPHICS'
170+
if: success() || failure()
171+
env:
172+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_EZGL=off"
173+
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
174+
run: |
175+
rm -f build/CMakeCache.txt
176+
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
177+
make -j${{ steps.cpu-cores.outputs.count}}
178+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
179+
180+
- name: 'Test with NO_SERVER'
181+
if: success() || failure()
182+
env:
183+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_USE_SERVER=off"
184+
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
185+
run: |
186+
rm -f build/CMakeCache.txt
187+
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
188+
make -j${{ steps.cpu-cores.outputs.count}}
189+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
190+
191+
- name: 'Test with CAPNPROTO disabled'
192+
if: success() || failure()
193+
env:
194+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVTR_ENABLE_CAPNPROTO=off"
195+
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
196+
run: |
197+
rm -f build/CMakeCache.txt
198+
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
199+
make -j${{ steps.cpu-cores.outputs.count}}
200+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
201+
202+
- name: 'Test with serial VPR_EXECUTION_ENGINE'
203+
if: success() || failure()
204+
env:
205+
CMAKE_PARAMS: "${{ env.COMMON_CMAKE_PARAMS }} -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial"
206+
NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
207+
run: |
208+
rm -f build/CMakeCache.txt
209+
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
210+
make -j${{ steps.cpu-cores.outputs.count}}
211+
./run_reg_test.py vtr_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count}}
212+
213+
128214
Regression:
129215
runs-on: ubuntu-24.04
130216
strategy:
@@ -137,42 +223,12 @@ jobs:
137223
suite: 'vtr_reg_basic',
138224
extra_pkgs: ""
139225
},
140-
{
141-
name: 'Basic with highest assertion level',
142-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=4 -DWITH_BLIFEXPLORER=on',
143-
suite: 'vtr_reg_basic',
144-
extra_pkgs: ""
145-
},
146226
{
147227
name: 'Basic_odin',
148228
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DWITH_PARMYS=OFF -DWITH_ODIN=on',
149229
suite: 'vtr_reg_basic_odin',
150230
extra_pkgs: ""
151231
},
152-
{
153-
name: 'Basic with NO_GRAPHICS',
154-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=off',
155-
suite: 'vtr_reg_basic',
156-
extra_pkgs: ""
157-
},
158-
{
159-
name: 'Basic with NO_SERVER',
160-
params: '-DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_USE_EZGL=on -DVPR_USE_SERVER=off',
161-
suite: 'vtr_reg_basic',
162-
extra_pkgs: ""
163-
},
164-
{
165-
name: 'Basic with CAPNPROTO disabled',
166-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_CAPNPROTO=off',
167-
suite: 'vtr_reg_basic',
168-
extra_pkgs: ""
169-
},
170-
{
171-
name: 'Basic with serial VPR_EXECUTION_ENGINE',
172-
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVPR_EXECUTION_ENGINE=serial -DTATUM_EXECUTION_ENGINE=serial',
173-
suite: 'vtr_reg_basic',
174-
extra_pkgs: ""
175-
},
176232
{
177233
name: 'Basic with VTR_ENABLE_DEBUG_LOGGING',
178234
params: '-DCMAKE_COMPILE_WARNING_AS_ERROR=on -DVTR_IPO_BUILD=off -DVTR_ASSERT_LEVEL=3 -DWITH_BLIFEXPLORER=on -DVTR_ENABLE_DEBUG_LOGGING=on',
@@ -484,7 +540,8 @@ jobs:
484540
needs:
485541
- Build
486542
- Format
487-
- UniTests
543+
- UnitTests
544+
- BuildVariations
488545
- Regression
489546
- Sanitized
490547
- Parmys

‎libs/libarchfpga/src/logic_types.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ LogicalModels::LogicalModels() {
2828
//INPAD
2929
{
3030
LogicalModelId inpad_model_id = create_logical_model(MODEL_INPUT);
31+
VTR_ASSERT_OPT(inpad_model_id == MODEL_INPUT_ID);
3132
t_model& inpad_model = get_model(inpad_model_id);
3233

3334
inpad_model.inputs = nullptr;
@@ -47,6 +48,7 @@ LogicalModels::LogicalModels() {
4748
//OUTPAD
4849
{
4950
LogicalModelId outpad_model_id = create_logical_model(MODEL_OUTPUT);
51+
VTR_ASSERT_OPT(outpad_model_id == MODEL_OUTPUT_ID);
5052
t_model& outpad_model = get_model(outpad_model_id);
5153

5254
outpad_model.inputs = new t_model_ports;
@@ -66,6 +68,7 @@ LogicalModels::LogicalModels() {
6668
//LATCH
6769
{
6870
LogicalModelId latch_model_id = create_logical_model(MODEL_LATCH);
71+
VTR_ASSERT_OPT(latch_model_id == MODEL_LATCH_ID);
6972
t_model& latch_model = get_model(latch_model_id);
7073
t_model_ports* latch_model_input_port_1 = new t_model_ports;
7174
t_model_ports* latch_model_input_port_2 = new t_model_ports;
@@ -104,6 +107,7 @@ LogicalModels::LogicalModels() {
104107
//NAMES
105108
{
106109
LogicalModelId names_model_id = create_logical_model(MODEL_NAMES);
110+
VTR_ASSERT_OPT(names_model_id == MODEL_NAMES_ID);
107111
t_model& names_model = get_model(names_model_id);
108112

109113
names_model.inputs = new t_model_ports;

‎libs/libarchfpga/src/logic_types.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,13 @@ class LogicalModels {
9797
static constexpr const char* MODEL_INPUT = ".input";
9898
static constexpr const char* MODEL_OUTPUT = ".output";
9999

100+
// The IDs of each of the library models. These are known ahead of time,
101+
// and making these constexpr can save having to look them up in this class.
102+
static constexpr LogicalModelId MODEL_INPUT_ID = LogicalModelId(0);
103+
static constexpr LogicalModelId MODEL_OUTPUT_ID = LogicalModelId(1);
104+
static constexpr LogicalModelId MODEL_LATCH_ID = LogicalModelId(2);
105+
static constexpr LogicalModelId MODEL_NAMES_ID = LogicalModelId(3);
106+
100107
// Iterator for the logical model IDs array.
101108
typedef typename vtr::vector_map<LogicalModelId, LogicalModelId>::const_iterator model_iterator;
102109

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1290,7 +1290,7 @@ struct ArchReader {
12901290
lut->parent_mode = mode;
12911291

12921292
lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES);
1293-
lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES);
1293+
lut->model_id = LogicalModels::MODEL_NAMES_ID;
12941294

12951295
lut->num_ports = 2;
12961296
lut->ports = (t_port*)vtr::calloc(lut->num_ports, sizeof(t_port));
@@ -1397,7 +1397,7 @@ struct ArchReader {
13971397
opad->num_ports = num_ports;
13981398
opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
13991399
opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT);
1400-
opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT);
1400+
opad->model_id = LogicalModels::MODEL_OUTPUT_ID;
14011401

14021402
opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT);
14031403
omode->pb_type_children[0] = *opad;
@@ -1419,7 +1419,7 @@ struct ArchReader {
14191419
ipad->num_ports = num_ports;
14201420
ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
14211421
ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT);
1422-
ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT);
1422+
ipad->model_id = LogicalModels::MODEL_INPUT_ID;
14231423

14241424
ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT);
14251425
imode->pb_type_children[0] = *ipad;

‎vpr/src/base/atom_netlist.cpp

Lines changed: 3 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,33 +14,20 @@
1414
*
1515
*/
1616
AtomNetlist::AtomNetlist(std::string name, std::string id)
17-
: Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId>(name, id)
18-
, inpad_model_(LogicalModelId::INVALID())
19-
, outpad_model_(LogicalModelId::INVALID()) {}
17+
: Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId>(name, id) {}
2018

2119
/*
2220
*
2321
* Blocks
2422
*
2523
*/
26-
void AtomNetlist::set_block_types(LogicalModelId inpad, LogicalModelId outpad) {
27-
VTR_ASSERT(inpad.is_valid());
28-
VTR_ASSERT(outpad.is_valid());
29-
30-
inpad_model_ = inpad;
31-
outpad_model_ = outpad;
32-
}
33-
3424
AtomBlockType AtomNetlist::block_type(const AtomBlockId id) const {
35-
VTR_ASSERT(inpad_model_.is_valid());
36-
VTR_ASSERT(outpad_model_.is_valid());
37-
3825
LogicalModelId blk_model = block_model(id);
3926

4027
AtomBlockType type = AtomBlockType::BLOCK;
41-
if (blk_model == inpad_model_) {
28+
if (blk_model == LogicalModels::MODEL_INPUT_ID) {
4229
type = AtomBlockType::INPAD;
43-
} else if (blk_model == outpad_model_) {
30+
} else if (blk_model == LogicalModels::MODEL_OUTPUT_ID) {
4431
type = AtomBlockType::OUTPAD;
4532
} else {
4633
type = AtomBlockType::BLOCK;

‎vpr/src/base/atom_netlist.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -93,11 +93,6 @@ class AtomNetlist : public Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId
9393
typedef std::vector<std::vector<vtr::LogicValue>> TruthTable;
9494

9595
public: //Public Accessors
96-
/*
97-
* Blocks
98-
*/
99-
void set_block_types(LogicalModelId inpad, LogicalModelId outpad);
100-
10196
///@brief Returns the type of the specified block
10297
AtomBlockType block_type(const AtomBlockId id) const;
10398

@@ -264,14 +259,6 @@ class AtomNetlist : public Netlist<AtomBlockId, AtomPortId, AtomPinId, AtomNetId
264259
vtr::vector_map<AtomBlockId, LogicalModelId> block_models_; //Architecture model of each block
265260
vtr::vector_map<AtomBlockId, TruthTable> block_truth_tables_; //Truth tables of each block
266261

267-
// Input IOs and output IOs always exist and have their own architecture
268-
// models. While their models are already included in block_models_, we
269-
// also store direct pointers to them to make checks of whether a block is
270-
// an INPAD or OUTPAD fast, as such checks are common in some netlist
271-
// operations (e.g. clean-up of an input netlist).
272-
LogicalModelId inpad_model_;
273-
LogicalModelId outpad_model_;
274-
275262
//Port data
276263
vtr::vector_map<AtomPortId, const t_model_ports*> port_models_; //Architecture port models of each port
277264

‎vpr/src/base/atom_netlist_utils.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ std::vector<AtomPortId> find_combinationally_connected_input_ports(const AtomNet
3434
///@brief Returns the set of clock ports which are combinationally connected to output_port
3535
std::vector<AtomPortId> find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port);
3636

37-
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models);
37+
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk);
3838
bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr);
3939
bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models, std::string* reason = nullptr);
4040
bool is_removable_output(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr);
@@ -137,7 +137,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
137137
}
138138

139139
//Latch
140-
LogicalModelId latch_model = models.get_model_by_name(LogicalModels::MODEL_LATCH);
140+
LogicalModelId latch_model = LogicalModels::MODEL_LATCH_ID;
141141
for (auto blk_id : netlist.blocks()) {
142142
if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) {
143143
LogicalModelId blk_model = netlist.block_model(blk_id);
@@ -225,7 +225,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
225225
}
226226

227227
//Names
228-
LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES);
228+
LogicalModelId names_model = LogicalModels::MODEL_NAMES_ID;
229229
for (auto blk_id : netlist.blocks()) {
230230
if (netlist.block_type(blk_id) == AtomBlockType::BLOCK) {
231231
LogicalModelId blk_model = netlist.block_model(blk_id);
@@ -292,8 +292,8 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist, const LogicalMod
292292
}
293293

294294
//Subckt
295-
LogicalModelId input_model = models.get_model_by_name(LogicalModels::MODEL_INPUT);
296-
LogicalModelId output_model = models.get_model_by_name(LogicalModels::MODEL_OUTPUT);
295+
LogicalModelId input_model = LogicalModels::MODEL_INPUT_ID;
296+
LogicalModelId output_model = LogicalModels::MODEL_OUTPUT_ID;
297297
std::set<LogicalModelId> subckt_models;
298298
for (auto blk_id : netlist.blocks()) {
299299
LogicalModelId blk_model = netlist.block_model(blk_id);
@@ -690,7 +690,7 @@ void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int v
690690

691691
//Remove the buffer luts
692692
for (auto blk : netlist.blocks()) {
693-
if (is_buffer_lut(netlist, blk, models)) {
693+
if (is_buffer_lut(netlist, blk)) {
694694
if (remove_buffer_lut(netlist, blk, models, verbosity)) {
695695
++removed_buffer_count;
696696
}
@@ -701,9 +701,9 @@ void absorb_buffer_luts(AtomNetlist& netlist, const LogicalModels& models, int v
701701
//TODO: absorb inverter LUTs?
702702
}
703703

704-
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk, const LogicalModels& models) {
704+
bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk) {
705705
if (netlist.block_type(blk) == AtomBlockType::BLOCK) {
706-
const LogicalModelId names_model = models.get_model_by_name(LogicalModels::MODEL_NAMES);
706+
const LogicalModelId names_model = LogicalModels::MODEL_NAMES_ID;
707707
if (netlist.block_model(blk) != names_model) return false;
708708

709709
auto input_ports = netlist.block_input_ports(blk);
@@ -1412,7 +1412,7 @@ std::set<AtomPinId> find_netlist_logical_clock_drivers(const AtomNetlist& netlis
14121412
//to find the true source
14131413
size_t assumed_buffer_count = 0;
14141414
std::set<AtomNetId> prev_clock_nets;
1415-
LogicalModelId names_model_id = models.get_model_by_name(LogicalModels::MODEL_NAMES);
1415+
LogicalModelId names_model_id = LogicalModels::MODEL_NAMES_ID;
14161416
while (prev_clock_nets != clock_nets) { //Still tracing back
14171417
prev_clock_nets = clock_nets;
14181418
clock_nets.clear();

‎vpr/src/base/check_netlist.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,6 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
128128
static int check_clb_conn(ClusterBlockId iblk, int num_conn) {
129129
auto& cluster_ctx = g_vpr_ctx.clustering();
130130
auto& clb_nlist = cluster_ctx.clb_nlist;
131-
const LogicalModels& models = g_vpr_ctx.device().arch->models;
132131

133132
int error = 0;
134133
t_logical_block_type_ptr type = clb_nlist.block_type(iblk);
@@ -137,15 +136,15 @@ static int check_clb_conn(ClusterBlockId iblk, int num_conn) {
137136
for (auto pin_id : clb_nlist.block_pins(iblk)) {
138137
auto pin_type = clb_nlist.pin_type(pin_id);
139138

140-
if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk, models)) {
139+
if (pin_type == PinType::SINK && !clb_nlist.block_contains_primary_output(iblk)) {
141140
//Input only and not a Primary-Output block
142141
VTR_LOG_WARN(
143142
"Logic block #%d (%s) has only 1 input pin '%s'"
144143
" -- the whole block is hanging logic that should be swept.\n",
145144
iblk, clb_nlist.block_name(iblk).c_str(),
146145
clb_nlist.pin_name(pin_id).c_str());
147146
}
148-
if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk, models)) {
147+
if (pin_type == PinType::DRIVER && !clb_nlist.block_contains_primary_input(iblk)) {
149148
//Output only and not a Primary-Input block
150149
VTR_LOG_WARN(
151150
"Logic block #%d (%s) has only 1 output pin '%s'."

0 commit comments

Comments
 (0)