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1 | 1 | package espflasher |
2 | 2 |
|
| 3 | +import ( |
| 4 | + "fmt" |
| 5 | + "net" |
| 6 | +) |
| 7 | + |
| 8 | +// ESP32 (classic) register addresses used for MAC/revision/feature |
| 9 | +// decoding. Unlike every later chip, the classic ESP32's efuse layout has |
| 10 | +// no BLOCK1; words are read directly off EFUSE_RD_REG_BASE, and the major |
| 11 | +// chip revision isn't a bitfield — it's a 3-bit value assembled from two |
| 12 | +// efuse bits plus one bit from an entirely separate SYSCON register, |
| 13 | +// looked up in a table. |
| 14 | +// Reference: esptool/targets/esp32.py (EFUSE_RD_REG_BASE, read_efuse(), |
| 15 | +// APB_CTL_DATE_ADDR, get_major_chip_version/get_minor_chip_version/ |
| 16 | +// get_pkg_version/get_chip_features). |
| 17 | +const ( |
| 18 | + esp32EfuseWord1 uint32 = 0x3FF5A004 // read_efuse(1) |
| 19 | + esp32EfuseWord2 uint32 = 0x3FF5A008 // read_efuse(2) |
| 20 | + esp32EfuseWord3 uint32 = 0x3FF5A00C // read_efuse(3) |
| 21 | + esp32EfuseWord4 uint32 = 0x3FF5A010 // read_efuse(4) |
| 22 | + esp32EfuseWord5 uint32 = 0x3FF5A014 // read_efuse(5) |
| 23 | + esp32EfuseWord6 uint32 = 0x3FF5A018 // read_efuse(6) |
| 24 | + |
| 25 | + // APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE (0x3FF66000) + 0x7C. Bit 31 |
| 26 | + // supplies the top bit of the 3-bit major-revision lookup index; it |
| 27 | + // lives outside the eFuse block entirely. |
| 28 | + esp32APBCtlDateReg uint32 = 0x3FF6607C |
| 29 | +) |
| 30 | + |
3 | 31 | // ESP32 target definition. |
4 | 32 | // Reference: https://github.com/espressif/esptool/blob/master/esptool/targets/esp32.py |
5 | 33 |
|
@@ -37,4 +65,134 @@ var defESP32 = &chipDef{ |
37 | 65 | }, |
38 | 66 |
|
39 | 67 | FlashSizes: defaultFlashSizes(), |
| 68 | + |
| 69 | + ReadMAC: esp32ReadMAC, |
| 70 | + ReadChipRevision: esp32ReadChipRevision, |
| 71 | + ReadChipFeatures: esp32ReadChipFeatures, |
| 72 | +} |
| 73 | + |
| 74 | +// esp32ReadMAC reads the factory-programmed base MAC from eFuse. |
| 75 | +// Reference: esptool/targets/esp32.py read_mac(). |
| 76 | +func esp32ReadMAC(f *Flasher) (net.HardwareAddr, error) { |
| 77 | + word1, err := f.ReadRegister(esp32EfuseWord1) |
| 78 | + if err != nil { |
| 79 | + return nil, err |
| 80 | + } |
| 81 | + word2, err := f.ReadRegister(esp32EfuseWord2) |
| 82 | + if err != nil { |
| 83 | + return nil, err |
| 84 | + } |
| 85 | + return decodeEfuseMAC(word1, word2), nil |
| 86 | +} |
| 87 | + |
| 88 | +// esp32MajorChipVersionTable is esptool's lookup table mapping the 3-bit |
| 89 | +// combined revision-bit value (from two eFuse bits plus one SYSCON bit) to |
| 90 | +// the major chip revision. Combine values not present here (2, 4, 5, 6) |
| 91 | +// map to major revision 0. |
| 92 | +// Reference: esptool/targets/esp32.py get_major_chip_version(). |
| 93 | +var esp32MajorChipVersionTable = map[uint32]int{ |
| 94 | + 0: 0, |
| 95 | + 1: 1, |
| 96 | + 3: 2, |
| 97 | + 7: 3, |
| 98 | +} |
| 99 | + |
| 100 | +// esp32ReadChipRevision reads the eFuse-encoded silicon revision. Unlike |
| 101 | +// every later chip, the major version isn't a bitfield: it's a lookup-table |
| 102 | +// index assembled from two eFuse bits plus one bit read from a SYSCON |
| 103 | +// register outside the eFuse block. |
| 104 | +// Reference: esptool/targets/esp32.py get_major_chip_version()/ |
| 105 | +// get_minor_chip_version(). |
| 106 | +func esp32ReadChipRevision(f *Flasher) (ChipRevision, error) { |
| 107 | + word3, err := f.ReadRegister(esp32EfuseWord3) |
| 108 | + if err != nil { |
| 109 | + return ChipRevision{}, err |
| 110 | + } |
| 111 | + word5, err := f.ReadRegister(esp32EfuseWord5) |
| 112 | + if err != nil { |
| 113 | + return ChipRevision{}, err |
| 114 | + } |
| 115 | + apbCtlDate, err := f.ReadRegister(esp32APBCtlDateReg) |
| 116 | + if err != nil { |
| 117 | + return ChipRevision{}, err |
| 118 | + } |
| 119 | + |
| 120 | + revBit0 := (word3 >> 15) & 0x1 |
| 121 | + revBit1 := (word5 >> 20) & 0x1 |
| 122 | + revBit2 := (apbCtlDate >> 31) & 0x1 |
| 123 | + combine := (revBit2 << 2) | (revBit1 << 1) | revBit0 |
| 124 | + |
| 125 | + major := esp32MajorChipVersionTable[combine] // default (unlisted) is 0 |
| 126 | + minor := (word5 >> 24) & 0x3 |
| 127 | + |
| 128 | + return ChipRevision{Major: major, Minor: int(minor)}, nil |
| 129 | +} |
| 130 | + |
| 131 | +// esp32CodingSchemeNames is esptool's literal mapping for the flash |
| 132 | +// encoding-coding-scheme feature string. |
| 133 | +// Reference: esptool/targets/esp32.py get_chip_features(). |
| 134 | +var esp32CodingSchemeNames = map[uint32]string{ |
| 135 | + 0: "None", |
| 136 | + 1: "3/4", |
| 137 | + 2: "Repeat (UNSUPPORTED)", |
| 138 | + 3: "None (may contain encoding data)", |
| 139 | +} |
| 140 | + |
| 141 | +// esp32ReadChipFeatures returns the chip feature list. |
| 142 | +// Reference: esptool/targets/esp32.py get_chip_features(). |
| 143 | +func esp32ReadChipFeatures(f *Flasher) ([]string, error) { |
| 144 | + word3, err := f.ReadRegister(esp32EfuseWord3) |
| 145 | + if err != nil { |
| 146 | + return nil, err |
| 147 | + } |
| 148 | + word4, err := f.ReadRegister(esp32EfuseWord4) |
| 149 | + if err != nil { |
| 150 | + return nil, err |
| 151 | + } |
| 152 | + word6, err := f.ReadRegister(esp32EfuseWord6) |
| 153 | + if err != nil { |
| 154 | + return nil, err |
| 155 | + } |
| 156 | + |
| 157 | + features := []string{"Wi-Fi"} |
| 158 | + |
| 159 | + if word3&(1<<1) == 0 { |
| 160 | + features = append(features, "BT") |
| 161 | + } |
| 162 | + |
| 163 | + if word3&(1<<0) != 0 { |
| 164 | + features = append(features, "Single Core + LP Core") |
| 165 | + } else { |
| 166 | + features = append(features, "Dual Core + LP Core") |
| 167 | + } |
| 168 | + |
| 169 | + if word3&(1<<13) != 0 { |
| 170 | + if word3&(1<<12) != 0 { |
| 171 | + features = append(features, "160MHz") |
| 172 | + } else { |
| 173 | + features = append(features, "240MHz") |
| 174 | + } |
| 175 | + } |
| 176 | + |
| 177 | + pkgVersion := ((word3 >> 9) & 0x7) | (((word3 >> 2) & 0x1) << 3) |
| 178 | + switch pkgVersion { |
| 179 | + case 2, 4, 5, 6: |
| 180 | + features = append(features, "Embedded Flash") |
| 181 | + } |
| 182 | + if pkgVersion == 6 { |
| 183 | + features = append(features, "Embedded PSRAM") |
| 184 | + } |
| 185 | + |
| 186 | + if adcVref := (word4 >> 8) & 0x1F; adcVref != 0 { |
| 187 | + features = append(features, "Vref calibration in eFuse") |
| 188 | + } |
| 189 | + |
| 190 | + if word3>>14&0x1 != 0 { |
| 191 | + features = append(features, "BLK3 partially reserved") |
| 192 | + } |
| 193 | + |
| 194 | + codingScheme := word6 & 0x3 |
| 195 | + features = append(features, fmt.Sprintf("Coding Scheme %s", esp32CodingSchemeNames[codingScheme])) |
| 196 | + |
| 197 | + return features, nil |
40 | 198 | } |
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