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Merge pull request #156 from stnolting/dependabot/submodules/neorv32-b540c1a
[Dependabot]: Bump neorv32 from `3359f5f` to `b540c1a`
2 parents f16850e + 3a923e1 commit 40e8d53

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neorv32

Submodule neorv32 updated 47 files

src/neorv32_verilog_wrapper.vhd

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -78,19 +78,16 @@ begin
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
81-
-- Internal Instruction Cache (iCACHE) --
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ICACHE_EN => true, -- implement instruction cache
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-- CPU Caches --
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ICACHE_EN => true, -- implement instruction cache (i-cache)
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ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
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-- Internal Data Cache (dCACHE) --
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DCACHE_EN => true, -- implement data cache
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DCACHE_EN => true, -- implement data cache (d-cache)
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DCACHE_NUM_BLOCKS => 4, -- d-cache: number of blocks (min 1), has to be a power of 2
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DCACHE_BLOCK_SIZE => 64, -- d-cache: block size in bytes (min 4), has to be a power of 2
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CACHE_BLOCK_SIZE => 64, -- i-cache/d-cache: block size in bytes (min 4), has to be a power of 2
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-- External bus interface (XBUS) --
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XBUS_EN => true, -- implement external memory bus interface?
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XBUS_TIMEOUT => 256, -- cycles after a pending bus access auto-terminates (0 = disabled)
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XBUS_REGSTAGE_EN => true, -- add XBUS register stage
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XBUS_CACHE_EN => false, -- enable external bus cache (x-cache)
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-- Processor peripherals --
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IO_CLINT_EN => true, -- implement core local interruptor (CLINT)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?

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