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[New Variant] STM32WB55VGY #2653

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@federica-ven

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@federica-ven

I can see there's a folder in the stm32 core WB55V(C-E-G)(Q-Y)_WB55VYY but it doesn't show as an in the IDE?

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federica-ven

federica-ven commented on Feb 10, 2025

@federica-ven
Author

I think I was able to answer everything myself, using the existing information on the wiki.

federica-ven

federica-ven commented on Feb 11, 2025

@federica-ven
Author

I've tried to add support for the STM32WB55VGYx MCUs, generating the ldscript and using a custom clock. I don't believe it's correct but it does compile, but my arduino sketch (Blink.ino) with a GPIO for an LED isn't behaving appropriately.

In my ldscript.ld I've modified the memory area like this

/* Specify the memory areas */
MEMORY
{
FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
RAM1 (xrw)                 : ORIGIN = 0x20000008, LENGTH = LD_MAX_DATA_SIZE - 8
RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
}

and for the SystemClock, I've imported it from cube, according to all the peripherals I intended to use.

WB55V(C-E-G)(Q-Y)_WB55VYY.zip

fpistm

fpistm commented on Feb 12, 2025

@fpistm
Member

Hi @federicaventriglia
did you try to debug to see if clock config is correct.

federica-ven

federica-ven commented on Feb 12, 2025

@federica-ven
Author

Hi @fpistm I've used the same clock config in Cube IDE and it seems to work, I used a simple LED Blink example but it seemed to run.

fpistm

fpistm commented on Feb 12, 2025

@fpistm
Member

One issue in the ldscript.ld:

- FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+ FLASH (rx)                 : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET

In the generic clock, pay attention to the lock ressource management, see other WB variant:

#include "lock_resource.h"
  /* This prevents concurrent access to RCC registers by CPU2 (M0+) */
  hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
  /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
  hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);

As said if you try to debug, you will see if you end in an Error_Handler() during the clock config.

federica-ven

federica-ven commented on Feb 12, 2025

@federica-ven
Author

Thanks for catching the issue in the ldscript, I've modified it now:

/* Specify the memory areas */
MEMORY
{
FLASH (rx)                 : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
RAM1 (xrw)                 : ORIGIN = 0x20000008, LENGTH = LD_MAX_DATA_SIZE - 8
RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
}

As for the Clock config, I have also tried adding the lock/unlock, as you said I've noticed it from the P-NUCLEO implementation and I see the same behaviour. Not sure if I've used it properly but I'll attach the code as well.

(I've also tried removing the custom clock configuration and using the default one (leaving the systemclock_config method empty) and I still see the same issue happening, which is strange)

Custom Clock with Locks

#if defined(ARDUINO_GENERIC_WB55VCQX) || defined(ARDUINO_GENERIC_WB55VCYX) ||\
    defined(ARDUINO_GENERIC_WB55VEQX) || defined(ARDUINO_GENERIC_WB55VEYX) ||\
    defined(ARDUINO_GENERIC_WB55VGQX) || defined(ARDUINO_GENERIC_WB55VGYX) ||\
    defined(ARDUINO_GENERIC_WB55VYYX)
#include "pins_arduino.h"
#include "lock_resource.h"


/**
  * @brief  System Clock Configuration
  * @param  None
  * @retval None
  */
WEAK void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};

 /* This prevents concurrent access to RCC registers by CPU2 (M0+) */
  hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
  /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
  hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);

  /** Configure the main internal regulator output voltage
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI
                              |RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV8;
  RCC_OscInitStruct.PLL.PLLN = 32;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
    #error "Clock Error Handler 1!"
  }

  /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
                              |RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
  RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
  {
    Error_Handler();
    #error "Clock Error Handler 2!"
  }

  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};

  /** Initializes the peripherals clock
  */
  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
  PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
  PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;

  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
  {
    Error_Handler();
    #error "Clock Error Handler 3!"
  }

  hsem_unlock(CFG_HW_RCC_SEMID);
  hsem_unlock(CFG_HW_CLK48_CONFIG_SEMID);

}

#endif /* ARDUINO_GENERIC_* */

I'm not too familiar with the debugging process so forgive me I'm not doing it properly. I've added some error statements in the Error_Handler() calls, would that work?

Edit: I've replaced #error with#warning and I do see all 3 of them being printed in the compiled output.

federica-ven

federica-ven commented on Feb 12, 2025

@federica-ven
Author

Thanks for catching the issue in the ldscript, I've modified it now:

/* Specify the memory areas */
MEMORY
{
FLASH (rx)                 : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
RAM1 (xrw)                 : ORIGIN = 0x20000008, LENGTH = LD_MAX_DATA_SIZE - 8
RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
}

As for the Clock config, I have also tried adding the lock/unlock, as you said I've noticed it from the P-NUCLEO implementation and I see the same behaviour. Not sure if I've used it properly but I'll attach the code as well.

(I've also tried removing the custom clock configuration and using the default one (leaving the systemclock_config method empty) and I still see the same issue happening, which is strange)

Seems like the same thing is happening with default clock config.

I've also tried modifying the ldscript to

- RAM1 (xrw)                 : ORIGIN = 0x20000008, LENGTH = LD_MAX_DATA_SIZE - 8
+ RAM1 (xrw)                 : ORIGIN = 0x20000008, LENGTH = LD_MAX_DATA_SIZE - 4

No changes

fpistm

fpistm commented on Feb 12, 2025

@fpistm
Member

Should be 0x20000004 not 0x20000008 with -4.

federica-ven

federica-ven commented on Feb 12, 2025

@federica-ven
Author

Yeah, apologies for the typo, looks like this

/* Specify the memory areas */
MEMORY
{
FLASH (rx)                 : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
RAM (xrw)                 : ORIGIN = 0x20000004, LENGTH = LD_MAX_DATA_SIZE - 4
RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
}
federica-ven

federica-ven commented on Feb 12, 2025

@federica-ven
Author

Do you think the problem is in the clock configuration? Running the default one could also not work?

added a commit that references this issue on Feb 12, 2025
9cde29c
added a commit that references this issue on Feb 12, 2025
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fpistm

fpistm commented on Feb 12, 2025

@fpistm
Member

@federicaventriglia
I've made the PR to support the generic.
It is untested as I do not have hardware with those mcu.

Some notes:

  • Generic clock used only internal clock, so by default you can't use RF as it required an HSE.
  • the value of FLASH and RAM have to be carefully reviewed as not all the FLASH nor RAM available (Flash/2 and RAM -64k)
  • about the blink, the generic does not defined LED by default as it is a generic and so don't know which pin can be used. So defined like this:
#ifndef LED_BUILTIN
  #define LED_BUILTIN           PNUM_NOT_DEFINED
#endif

To redefine it to the proper value, create a build_opt.h file with for example a LED connected to PA5:
-DLED_BUILTIN=PA5

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      [New Variant] STM32WB55VGY · Issue #2653 · stm32duino/Arduino_Core_STM32