@@ -45,99 +45,99 @@ extern "C" {
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typedef enum {
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#ifdef DMA1_Channel1
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- DMA1_CHANNEL1_INDEX ,
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+ DMA1_CHANNEL1_INDEX ,
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#endif
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#ifdef DMA1_Channel2
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- DMA1_CHANNEL2_INDEX ,
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+ DMA1_CHANNEL2_INDEX ,
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#endif
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#ifdef DMA1_Channel3
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- DMA1_CHANNEL3_INDEX ,
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+ DMA1_CHANNEL3_INDEX ,
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#endif
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#ifdef DMA1_Channel4
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- DMA1_CHANNEL4_INDEX ,
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+ DMA1_CHANNEL4_INDEX ,
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#endif
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#ifdef DMA1_Channel5
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- DMA1_CHANNEL5_INDEX ,
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+ DMA1_CHANNEL5_INDEX ,
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#endif
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#ifdef DMA1_Channel6
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- DMA1_CHANNEL6_INDEX ,
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+ DMA1_CHANNEL6_INDEX ,
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#endif
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#ifdef DMA1_Channel7
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- DMA1_CHANNEL7_INDEX ,
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+ DMA1_CHANNEL7_INDEX ,
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#endif
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#ifdef DMA2_Channel1
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- DMA2_CHANNEL1_INDEX ,
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+ DMA2_CHANNEL1_INDEX ,
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#endif
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#ifdef DMA2_Channel2
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- DMA2_CHANNEL2_INDEX ,
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+ DMA2_CHANNEL2_INDEX ,
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#endif
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#ifdef DMA2_Channel3
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- DMA2_CHANNEL3_INDEX ,
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+ DMA2_CHANNEL3_INDEX ,
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#endif
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#ifdef DMA2_Channel4
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- DMA2_CHANNEL4_INDEX ,
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+ DMA2_CHANNEL4_INDEX ,
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#endif
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#ifdef DMA2_Channel5
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- DMA2_CHANNEL5_INDEX ,
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+ DMA2_CHANNEL5_INDEX ,
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#endif
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#ifdef DMA2_Channel6
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- DMA2_CHANNEL6_INDEX ,
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+ DMA2_CHANNEL6_INDEX ,
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#endif
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#ifdef DMA2_Channel7
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- DMA2_CHANNEL7_INDEX ,
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+ DMA2_CHANNEL7_INDEX ,
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#endif
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#ifdef DMA2_Channel8
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- DMA2_CHANNEL8_INDEX ,
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+ DMA2_CHANNEL8_INDEX ,
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#endif
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#ifdef DMA1_Stream0
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- DMA1_STREAM0_INDEX ,
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+ DMA1_STREAM0_INDEX ,
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#endif
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#ifdef DMA1_Stream1
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- DMA1_STREAM1_INDEX ,
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+ DMA1_STREAM1_INDEX ,
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#endif
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#ifdef DMA1_Stream2
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- DMA1_STREAM2_INDEX ,
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+ DMA1_STREAM2_INDEX ,
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#endif
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#ifdef DMA1_Stream3
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- DMA1_STREAM3_INDEX ,
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+ DMA1_STREAM3_INDEX ,
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#endif
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#ifdef DMA1_Stream4
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- DMA1_STREAM4_INDEX ,
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+ DMA1_STREAM4_INDEX ,
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#endif
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#ifdef DMA1_Stream5
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- DMA1_STREAM5_INDEX ,
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+ DMA1_STREAM5_INDEX ,
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#endif
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#ifdef DMA1_Stream6
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- DMA1_STREAM6_INDEX ,
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+ DMA1_STREAM6_INDEX ,
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#endif
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#ifdef DMA1_Stream7
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- DMA1_STREAM7_INDEX ,
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+ DMA1_STREAM7_INDEX ,
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#endif
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#ifdef DMA2_Stream0
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- DMA2_STREAM0_INDEX ,
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+ DMA2_STREAM0_INDEX ,
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#endif
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#ifdef DMA2_Stream1
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- DMA2_STREAM1_INDEX ,
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+ DMA2_STREAM1_INDEX ,
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#endif
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#ifdef DMA2_Stream2
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- DMA2_STREAM2_INDEX ,
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+ DMA2_STREAM2_INDEX ,
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#endif
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#ifdef DMA2_Stream3
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- DMA2_STREAM3_INDEX ,
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+ DMA2_STREAM3_INDEX ,
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#endif
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#ifdef DMA2_Stream4
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- DMA2_STREAM4_INDEX ,
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+ DMA2_STREAM4_INDEX ,
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#endif
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#ifdef DMA2_Stream5
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- DMA2_STREAM5_INDEX ,
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+ DMA2_STREAM5_INDEX ,
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#endif
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#ifdef DMA2_Stream6
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- DMA2_STREAM6_INDEX ,
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+ DMA2_STREAM6_INDEX ,
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#endif
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#ifdef DMA2_Stream7
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- DMA2_STREAM7_INDEX ,
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+ DMA2_STREAM7_INDEX ,
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#endif
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- DMA_CHANNEL_NUM
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+ DMA_CHANNEL_NUM
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} dma_index_t ;
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#define NC (dma_index_t)-1
@@ -151,140 +151,140 @@ static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL};
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*/
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static dma_index_t get_dma_index (
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#if defined(STM32F2xx ) || defined(STM32F4xx ) || defined(STM32F7xx )
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- DMA_Stream_TypeDef
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+ DMA_Stream_TypeDef
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#else
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- DMA_Channel_TypeDef
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+ DMA_Channel_TypeDef
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#endif
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- * instance )
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+ * instance )
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{
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- switch ((uint32_t )instance ) {
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+ switch ((uint32_t )instance ) {
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#ifdef DMA1_Channel1
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case (uint32_t )DMA1_Channel1 :
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- return DMA1_CHANNEL1_INDEX ;
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+ return DMA1_CHANNEL1_INDEX ;
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#endif
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#ifdef DMA1_Channel2
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case (uint32_t )DMA1_Channel2 :
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- return DMA1_CHANNEL2_INDEX ;
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+ return DMA1_CHANNEL2_INDEX ;
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#endif
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#ifdef DMA1_Channel3
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case (uint32_t )DMA1_Channel3 :
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- return DMA1_CHANNEL3_INDEX ;
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+ return DMA1_CHANNEL3_INDEX ;
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#endif
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#ifdef DMA1_Channel4
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case (uint32_t )DMA1_Channel4 :
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- return DMA1_CHANNEL4_INDEX ;
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+ return DMA1_CHANNEL4_INDEX ;
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#endif
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#ifdef DMA1_Channel5
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case (uint32_t )DMA1_Channel5 :
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- return DMA1_CHANNEL5_INDEX ;
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+ return DMA1_CHANNEL5_INDEX ;
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#endif
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#ifdef DMA1_Channel6
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case (uint32_t )DMA1_Channel6 :
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- return DMA1_CHANNEL6_INDEX ;
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+ return DMA1_CHANNEL6_INDEX ;
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#endif
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#ifdef DMA1_Channel7
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case (uint32_t )DMA1_Channel7 :
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- return DMA1_CHANNEL7_INDEX ;
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+ return DMA1_CHANNEL7_INDEX ;
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#endif
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#ifdef DMA2_Channel1
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case (uint32_t )DMA2_Channel1 :
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- return DMA2_CHANNEL1_INDEX ;
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+ return DMA2_CHANNEL1_INDEX ;
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#endif
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#ifdef DMA2_Channel2
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case (uint32_t )DMA2_Channel2 :
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- return DMA2_CHANNEL2_INDEX ;
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+ return DMA2_CHANNEL2_INDEX ;
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#endif
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#ifdef DMA2_Channel3
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case (uint32_t )DMA2_Channel3 :
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- return DMA2_CHANNEL3_INDEX ;
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+ return DMA2_CHANNEL3_INDEX ;
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#endif
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#ifdef DMA2_Channel4
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case (uint32_t )DMA2_Channel4 :
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- return DMA2_CHANNEL4_INDEX ;
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+ return DMA2_CHANNEL4_INDEX ;
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#endif
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#ifdef DMA2_Channel5
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case (uint32_t )DMA2_Channel5 :
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- return DMA2_CHANNEL5_INDEX ;
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+ return DMA2_CHANNEL5_INDEX ;
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#endif
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#ifdef DMA2_Channel6
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case (uint32_t )DMA2_Channel6 :
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- return DMA2_CHANNEL6_INDEX ;
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+ return DMA2_CHANNEL6_INDEX ;
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#endif
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#ifdef DMA2_Channel7
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case (uint32_t )DMA2_Channel7 :
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- return DMA2_CHANNEL7_INDEX ;
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+ return DMA2_CHANNEL7_INDEX ;
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#endif
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#ifdef DMA2_Channel8
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case (uint32_t )DMA2_Channel8 :
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- return DMA2_CHANNEL8_INDEX ;
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+ return DMA2_CHANNEL8_INDEX ;
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#endif
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#ifdef DMA1_Stream0
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case (uint32_t )DMA1_Stream0 :
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- return DMA1_STREAM0_INDEX ;
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+ return DMA1_STREAM0_INDEX ;
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#endif
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#ifdef DMA1_Stream1
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case (uint32_t )DMA1_Stream1 :
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- return DMA1_STREAM1_INDEX ;
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+ return DMA1_STREAM1_INDEX ;
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#endif
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#ifdef DMA1_Stream2
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case (uint32_t )DMA1_Stream2 :
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- return DMA1_STREAM2_INDEX ;
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+ return DMA1_STREAM2_INDEX ;
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#endif
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#ifdef DMA1_Stream3
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case (uint32_t )DMA1_Stream3 :
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- return DMA1_STREAM3_INDEX ;
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+ return DMA1_STREAM3_INDEX ;
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#endif
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#ifdef DMA1_Stream4
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case (uint32_t )DMA1_Stream4 :
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- return DMA1_STREAM4_INDEX ;
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+ return DMA1_STREAM4_INDEX ;
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#endif
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#ifdef DMA1_Stream5
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case (uint32_t )DMA1_Stream5 :
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- return DMA1_STREAM5_INDEX ;
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+ return DMA1_STREAM5_INDEX ;
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#endif
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#ifdef DMA1_Stream6
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case (uint32_t )DMA1_Stream6 :
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- return DMA1_STREAM6_INDEX ;
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+ return DMA1_STREAM6_INDEX ;
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#endif
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#ifdef DMA1_Stream7
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case (uint32_t )DMA1_Stream7 :
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- return DMA1_STREAM7_INDEX ;
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+ return DMA1_STREAM7_INDEX ;
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#endif
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#ifdef DMA2_Stream0
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case (uint32_t )DMA2_Stream0 :
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- return DMA2_STREAM0_INDEX ;
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+ return DMA2_STREAM0_INDEX ;
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#endif
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#ifdef DMA2_Stream1
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case (uint32_t )DMA2_Stream1 :
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- return DMA2_STREAM1_INDEX ;
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+ return DMA2_STREAM1_INDEX ;
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#endif
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#ifdef DMA2_Stream2
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case (uint32_t )DMA2_Stream2 :
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- return DMA2_STREAM2_INDEX ;
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+ return DMA2_STREAM2_INDEX ;
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#endif
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#ifdef DMA2_Stream3
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case (uint32_t )DMA2_Stream3 :
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- return DMA2_STREAM3_INDEX ;
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+ return DMA2_STREAM3_INDEX ;
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#endif
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#ifdef DMA2_Stream4
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case (uint32_t )DMA2_Stream4 :
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- return DMA2_STREAM4_INDEX ;
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+ return DMA2_STREAM4_INDEX ;
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#endif
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#ifdef DMA2_Stream5
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case (uint32_t )DMA2_Stream5 :
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- return DMA2_STREAM5_INDEX ;
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+ return DMA2_STREAM5_INDEX ;
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#endif
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#ifdef DMA2_Stream6
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case (uint32_t )DMA2_Stream6 :
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- return DMA2_STREAM6_INDEX ;
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+ return DMA2_STREAM6_INDEX ;
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#endif
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#ifdef DMA2_Stream7
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case (uint32_t )DMA2_Stream7 :
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- return DMA2_STREAM7_INDEX ;
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+ return DMA2_STREAM7_INDEX ;
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#endif
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default :
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- return NC ;
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- }
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+ return NC ;
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+ }
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}
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/**
@@ -294,140 +294,140 @@ static dma_index_t get_dma_index(
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*/
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IRQn_Type get_dma_interrupt (
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#if defined(STM32F2xx ) || defined(STM32F4xx ) || defined(STM32F7xx )
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- DMA_Stream_TypeDef
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+ DMA_Stream_TypeDef
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#else
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- DMA_Channel_TypeDef
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+ DMA_Channel_TypeDef
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#endif
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- * instance )
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+ * instance )
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{
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- switch ((uint32_t )instance ) {
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+ switch ((uint32_t )instance ) {
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#ifdef DMA1_Channel1
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case (uint32_t )DMA1_Channel1 :
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- return DMA1_Channel1_IRQn ;
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+ return DMA1_Channel1_IRQn ;
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#endif
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#ifdef DMA1_Channel2
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case (uint32_t )DMA1_Channel2 :
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- return DMA1_Channel2_IRQn ;
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+ return DMA1_Channel2_IRQn ;
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#endif
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#ifdef DMA1_Channel3
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case (uint32_t )DMA1_Channel3 :
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- return DMA1_Channel3_IRQn ;
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+ return DMA1_Channel3_IRQn ;
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#endif
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#ifdef DMA1_Channel4
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317
case (uint32_t )DMA1_Channel4 :
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- return DMA1_Channel4_IRQn ;
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+ return DMA1_Channel4_IRQn ;
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319
#endif
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#ifdef DMA1_Channel5
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case (uint32_t )DMA1_Channel5 :
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- return DMA1_Channel5_IRQn ;
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+ return DMA1_Channel5_IRQn ;
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323
#endif
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#ifdef DMA1_Channel6
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case (uint32_t )DMA1_Channel6 :
326
- return DMA1_Channel6_IRQn ;
326
+ return DMA1_Channel6_IRQn ;
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327
#endif
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#ifdef DMA1_Channel7
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case (uint32_t )DMA1_Channel7 :
330
- return DMA1_Channel7_IRQn ;
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+ return DMA1_Channel7_IRQn ;
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#endif
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#ifdef DMA2_Channel1
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case (uint32_t )DMA2_Channel1 :
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- return DMA2_Channel1_IRQn ;
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+ return DMA2_Channel1_IRQn ;
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#endif
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#ifdef DMA2_Channel2
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case (uint32_t )DMA2_Channel2 :
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- return DMA2_Channel2_IRQn ;
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+ return DMA2_Channel2_IRQn ;
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339
#endif
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#ifdef DMA2_Channel3
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341
case (uint32_t )DMA2_Channel3 :
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- return DMA2_Channel3_IRQn ;
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+ return DMA2_Channel3_IRQn ;
343
343
#endif
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#ifdef DMA2_Channel4
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345
case (uint32_t )DMA2_Channel4 :
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- return DMA2_Channel4_IRQn ;
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+ return DMA2_Channel4_IRQn ;
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347
#endif
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#ifdef DMA2_Channel5
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349
case (uint32_t )DMA2_Channel5 :
350
- return DMA2_Channel5_IRQn ;
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+ return DMA2_Channel5_IRQn ;
351
351
#endif
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352
#ifdef DMA2_Channel6
353
353
case (uint32_t )DMA2_Channel6 :
354
- return DMA2_Channel6_IRQn ;
354
+ return DMA2_Channel6_IRQn ;
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355
#endif
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#ifdef DMA2_Channel7
357
357
case (uint32_t )DMA2_Channel7 :
358
- return DMA2_Channel7_IRQn ;
358
+ return DMA2_Channel7_IRQn ;
359
359
#endif
360
360
#ifdef DMA2_Channel8
361
361
case (uint32_t )DMA2_Channel8 :
362
- return DMA2_Channel8_IRQn ;
362
+ return DMA2_Channel8_IRQn ;
363
363
#endif
364
364
#ifdef DMA1_Stream0
365
365
case (uint32_t )DMA1_Stream0 :
366
- return DMA1_Stream0_IRQn ;
366
+ return DMA1_Stream0_IRQn ;
367
367
#endif
368
368
#ifdef DMA1_Stream1
369
369
case (uint32_t )DMA1_Stream1 :
370
- return DMA1_Stream1_IRQn ;
370
+ return DMA1_Stream1_IRQn ;
371
371
#endif
372
372
#ifdef DMA1_Stream2
373
373
case (uint32_t )DMA1_Stream2 :
374
- return DMA1_Stream2_IRQn ;
374
+ return DMA1_Stream2_IRQn ;
375
375
#endif
376
376
#ifdef DMA1_Stream3
377
377
case (uint32_t )DMA1_Stream3 :
378
- return DMA1_Stream3_IRQn ;
378
+ return DMA1_Stream3_IRQn ;
379
379
#endif
380
380
#ifdef DMA1_Stream4
381
381
case (uint32_t )DMA1_Stream4 :
382
- return DMA1_Stream4_IRQn ;
382
+ return DMA1_Stream4_IRQn ;
383
383
#endif
384
384
#ifdef DMA1_Stream5
385
385
case (uint32_t )DMA1_Stream5 :
386
- return DMA1_Stream5_IRQn ;
386
+ return DMA1_Stream5_IRQn ;
387
387
#endif
388
388
#ifdef DMA1_Stream6
389
389
case (uint32_t )DMA1_Stream6 :
390
- return DMA1_Stream6_IRQn ;
390
+ return DMA1_Stream6_IRQn ;
391
391
#endif
392
392
#ifdef DMA1_Stream7
393
393
case (uint32_t )DMA1_Stream7 :
394
- return DMA1_Stream7_IRQn ;
394
+ return DMA1_Stream7_IRQn ;
395
395
#endif
396
396
#ifdef DMA2_Stream0
397
397
case (uint32_t )DMA2_Stream0 :
398
- return DMA2_Stream0_IRQn ;
398
+ return DMA2_Stream0_IRQn ;
399
399
#endif
400
400
#ifdef DMA2_Stream1
401
401
case (uint32_t )DMA2_Stream1 :
402
- return DMA2_Stream1_IRQn ;
402
+ return DMA2_Stream1_IRQn ;
403
403
#endif
404
404
#ifdef DMA2_Stream2
405
405
case (uint32_t )DMA2_Stream2 :
406
- return DMA2_Stream2_IRQn ;
406
+ return DMA2_Stream2_IRQn ;
407
407
#endif
408
408
#ifdef DMA2_Stream3
409
409
case (uint32_t )DMA2_Stream3 :
410
- return DMA2_Stream3_IRQn ;
410
+ return DMA2_Stream3_IRQn ;
411
411
#endif
412
412
#ifdef DMA2_Stream4
413
413
case (uint32_t )DMA2_Stream4 :
414
- return DMA2_Stream4_IRQn ;
414
+ return DMA2_Stream4_IRQn ;
415
415
#endif
416
416
#ifdef DMA2_Stream5
417
417
case (uint32_t )DMA2_Stream5 :
418
- return DMA2_Stream5_IRQn ;
418
+ return DMA2_Stream5_IRQn ;
419
419
#endif
420
420
#ifdef DMA2_Stream6
421
421
case (uint32_t )DMA2_Stream6 :
422
- return DMA2_Stream6_IRQn ;
422
+ return DMA2_Stream6_IRQn ;
423
423
#endif
424
424
#ifdef DMA2_Stream7
425
425
case (uint32_t )DMA2_Stream7 :
426
- return DMA2_Stream7_IRQn ;
426
+ return DMA2_Stream7_IRQn ;
427
427
#endif
428
428
default :
429
- return NC ;
430
- }
429
+ return NC ;
430
+ }
431
431
}
432
432
433
433
/**
@@ -437,11 +437,11 @@ IRQn_Type get_dma_interrupt(
437
437
*/
438
438
void prepare_dma (DMA_HandleTypeDef * dma_handle )
439
439
{
440
- dma_index_t dma_index = get_dma_index (dma_handle -> Instance );
441
- if (dma_index == NC ) {
442
- return ;
443
- }
444
- dma_handles [dma_index ] = dma_handle ;
440
+ dma_index_t dma_index = get_dma_index (dma_handle -> Instance );
441
+ if (dma_index == NC ) {
442
+ return ;
443
+ }
444
+ dma_handles [dma_index ] = dma_handle ;
445
445
}
446
446
447
447
/**
@@ -451,11 +451,11 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle)
451
451
*/
452
452
void end_dma (DMA_HandleTypeDef * dma_handle )
453
453
{
454
- dma_index_t dma_index = get_dma_index (dma_handle -> Instance );
455
- if (dma_index == NC ) {
456
- return ;
457
- }
458
- dma_handles [dma_index ] = NULL ;
454
+ dma_index_t dma_index = get_dma_index (dma_handle -> Instance );
455
+ if (dma_index == NC ) {
456
+ return ;
457
+ }
458
+ dma_handles [dma_index ] = NULL ;
459
459
}
460
460
461
461
#ifdef DMA1_Channel1
@@ -466,9 +466,9 @@ void end_dma(DMA_HandleTypeDef *dma_handle)
466
466
*/
467
467
void DMA1_Channel1_IRQHandler ()
468
468
{
469
- if (dma_handles [DMA1_CHANNEL1_INDEX ] != NULL ) {
470
- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL1_INDEX ]);
471
- }
469
+ if (dma_handles [DMA1_CHANNEL1_INDEX ] != NULL ) {
470
+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL1_INDEX ]);
471
+ }
472
472
}
473
473
#endif
474
474
@@ -480,9 +480,9 @@ void DMA1_Channel1_IRQHandler()
480
480
*/
481
481
void DMA1_Channel2_IRQHandler ()
482
482
{
483
- if (dma_handles [DMA1_CHANNEL2_INDEX ] != NULL ) {
484
- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL2_INDEX ]);
485
- }
483
+ if (dma_handles [DMA1_CHANNEL2_INDEX ] != NULL ) {
484
+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL2_INDEX ]);
485
+ }
486
486
}
487
487
#endif
488
488
@@ -494,9 +494,9 @@ void DMA1_Channel2_IRQHandler()
494
494
*/
495
495
void DMA1_Channel3_IRQHandler ()
496
496
{
497
- if (dma_handles [DMA1_CHANNEL3_INDEX ] != NULL ) {
498
- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL3_INDEX ]);
499
- }
497
+ if (dma_handles [DMA1_CHANNEL3_INDEX ] != NULL ) {
498
+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL3_INDEX ]);
499
+ }
500
500
}
501
501
#endif
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@@ -508,9 +508,9 @@ void DMA1_Channel3_IRQHandler()
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*/
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void DMA1_Channel4_IRQHandler ()
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{
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- if (dma_handles [DMA1_CHANNEL4_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL4_INDEX ]);
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- }
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+ if (dma_handles [DMA1_CHANNEL4_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL4_INDEX ]);
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+ }
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}
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#endif
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@@ -522,9 +522,9 @@ void DMA1_Channel4_IRQHandler()
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*/
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void DMA1_Channel5_IRQHandler ()
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{
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- if (dma_handles [DMA1_CHANNEL5_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL5_INDEX ]);
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- }
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+ if (dma_handles [DMA1_CHANNEL5_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL5_INDEX ]);
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+ }
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}
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#endif
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@@ -535,9 +535,9 @@ void DMA1_Channel5_IRQHandler()
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*/
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void DMA1_Channel6_IRQHandler ()
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{
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- if (dma_handles [DMA1_CHANNEL6_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL6_INDEX ]);
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- }
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+ if (dma_handles [DMA1_CHANNEL6_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL6_INDEX ]);
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+ }
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}
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#endif
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@@ -549,9 +549,9 @@ void DMA1_Channel6_IRQHandler()
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*/
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void DMA1_Channel7_IRQHandler ()
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{
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- if (dma_handles [DMA1_CHANNEL7_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL7_INDEX ]);
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- }
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+ if (dma_handles [DMA1_CHANNEL7_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_CHANNEL7_INDEX ]);
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+ }
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}
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#endif
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@@ -563,9 +563,9 @@ void DMA1_Channel7_IRQHandler()
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*/
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void DMA2_Channel1_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL1_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL1_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL1_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL1_INDEX ]);
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+ }
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}
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#endif
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@@ -577,9 +577,9 @@ void DMA2_Channel1_IRQHandler()
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*/
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void DMA2_Channel2_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL2_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL2_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL2_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL2_INDEX ]);
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+ }
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}
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#endif
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@@ -591,9 +591,9 @@ void DMA2_Channel2_IRQHandler()
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*/
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void DMA2_Channel3_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL3_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL3_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL3_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL3_INDEX ]);
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+ }
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}
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#endif
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@@ -605,9 +605,9 @@ void DMA2_Channel3_IRQHandler()
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*/
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void DMA2_Channel4_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL4_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL4_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL4_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL4_INDEX ]);
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+ }
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}
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#endif
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@@ -619,9 +619,9 @@ void DMA2_Channel4_IRQHandler()
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*/
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void DMA2_Channel5_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL5_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL5_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL5_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL5_INDEX ]);
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+ }
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}
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#endif
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@@ -633,9 +633,9 @@ void DMA2_Channel5_IRQHandler()
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*/
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void DMA2_Channel6_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL6_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL6_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL6_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL6_INDEX ]);
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+ }
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}
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#endif
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@@ -647,9 +647,9 @@ void DMA2_Channel6_IRQHandler()
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*/
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void DMA2_Channel7_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL7_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL7_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL7_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL7_INDEX ]);
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+ }
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}
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#endif
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@@ -661,153 +661,153 @@ void DMA2_Channel7_IRQHandler()
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*/
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void DMA2_Channel8_IRQHandler ()
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{
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- if (dma_handles [DMA2_CHANNEL8_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL8_INDEX ]);
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- }
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+ if (dma_handles [DMA2_CHANNEL8_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_CHANNEL8_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream0
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void DMA1_Stream0_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM0_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM0_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM0_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM0_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream1
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void DMA1_Stream1_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM1_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM1_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM1_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM1_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream2
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void DMA1_Stream2_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM2_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM2_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM2_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM2_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream3
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void DMA1_Stream3_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM3_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM3_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM3_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM3_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream4
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void DMA1_Stream4_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM4_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM4_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM4_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM4_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream5
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void DMA1_Stream5_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM5_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM5_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM5_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM5_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream6
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void DMA1_Stream6_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM6_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM6_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM6_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM6_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA1_Stream7
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void DMA1_Stream7_IRQHandler ()
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{
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- if (dma_handles [DMA1_STREAM7_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM7_INDEX ]);
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- }
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+ if (dma_handles [DMA1_STREAM7_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA1_STREAM7_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream0
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void DMA2_Stream0_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM0_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM0_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM0_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM0_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream1
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void DMA2_Stream1_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM1_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM1_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM1_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM1_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream2
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void DMA2_Stream2_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM2_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM2_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM2_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM2_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream3
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void DMA2_Stream3_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM3_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM3_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM3_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM3_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream4
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void DMA2_Stream4_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM4_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM4_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM4_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM4_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream5
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void DMA2_Stream5_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM5_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM5_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM5_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM5_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream6
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void DMA2_Stream6_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM6_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM6_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM6_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM6_INDEX ]);
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+ }
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}
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#endif
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#ifdef DMA2_Stream7
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void DMA2_Stream7_IRQHandler ()
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{
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- if (dma_handles [DMA2_STREAM7_INDEX ] != NULL ) {
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- HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM7_INDEX ]);
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- }
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+ if (dma_handles [DMA2_STREAM7_INDEX ] != NULL ) {
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+ HAL_DMA_IRQHandler (dma_handles [DMA2_STREAM7_INDEX ]);
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+ }
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}
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#endif
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