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committedDec 10, 2019
Ran astyle.py.
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2 files changed

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‎cores/arduino/stm32/dma.c

Lines changed: 209 additions & 209 deletions
Original file line numberDiff line numberDiff line change
@@ -45,99 +45,99 @@ extern "C" {
4545

4646
typedef enum {
4747
#ifdef DMA1_Channel1
48-
DMA1_CHANNEL1_INDEX,
48+
DMA1_CHANNEL1_INDEX,
4949
#endif
5050
#ifdef DMA1_Channel2
51-
DMA1_CHANNEL2_INDEX,
51+
DMA1_CHANNEL2_INDEX,
5252
#endif
5353
#ifdef DMA1_Channel3
54-
DMA1_CHANNEL3_INDEX,
54+
DMA1_CHANNEL3_INDEX,
5555
#endif
5656
#ifdef DMA1_Channel4
57-
DMA1_CHANNEL4_INDEX,
57+
DMA1_CHANNEL4_INDEX,
5858
#endif
5959
#ifdef DMA1_Channel5
60-
DMA1_CHANNEL5_INDEX,
60+
DMA1_CHANNEL5_INDEX,
6161
#endif
6262
#ifdef DMA1_Channel6
63-
DMA1_CHANNEL6_INDEX,
63+
DMA1_CHANNEL6_INDEX,
6464
#endif
6565
#ifdef DMA1_Channel7
66-
DMA1_CHANNEL7_INDEX,
66+
DMA1_CHANNEL7_INDEX,
6767
#endif
6868
#ifdef DMA2_Channel1
69-
DMA2_CHANNEL1_INDEX,
69+
DMA2_CHANNEL1_INDEX,
7070
#endif
7171
#ifdef DMA2_Channel2
72-
DMA2_CHANNEL2_INDEX,
72+
DMA2_CHANNEL2_INDEX,
7373
#endif
7474
#ifdef DMA2_Channel3
75-
DMA2_CHANNEL3_INDEX,
75+
DMA2_CHANNEL3_INDEX,
7676
#endif
7777
#ifdef DMA2_Channel4
78-
DMA2_CHANNEL4_INDEX,
78+
DMA2_CHANNEL4_INDEX,
7979
#endif
8080
#ifdef DMA2_Channel5
81-
DMA2_CHANNEL5_INDEX,
81+
DMA2_CHANNEL5_INDEX,
8282
#endif
8383
#ifdef DMA2_Channel6
84-
DMA2_CHANNEL6_INDEX,
84+
DMA2_CHANNEL6_INDEX,
8585
#endif
8686
#ifdef DMA2_Channel7
87-
DMA2_CHANNEL7_INDEX,
87+
DMA2_CHANNEL7_INDEX,
8888
#endif
8989
#ifdef DMA2_Channel8
90-
DMA2_CHANNEL8_INDEX,
90+
DMA2_CHANNEL8_INDEX,
9191
#endif
9292
#ifdef DMA1_Stream0
93-
DMA1_STREAM0_INDEX,
93+
DMA1_STREAM0_INDEX,
9494
#endif
9595
#ifdef DMA1_Stream1
96-
DMA1_STREAM1_INDEX,
96+
DMA1_STREAM1_INDEX,
9797
#endif
9898
#ifdef DMA1_Stream2
99-
DMA1_STREAM2_INDEX,
99+
DMA1_STREAM2_INDEX,
100100
#endif
101101
#ifdef DMA1_Stream3
102-
DMA1_STREAM3_INDEX,
102+
DMA1_STREAM3_INDEX,
103103
#endif
104104
#ifdef DMA1_Stream4
105-
DMA1_STREAM4_INDEX,
105+
DMA1_STREAM4_INDEX,
106106
#endif
107107
#ifdef DMA1_Stream5
108-
DMA1_STREAM5_INDEX,
108+
DMA1_STREAM5_INDEX,
109109
#endif
110110
#ifdef DMA1_Stream6
111-
DMA1_STREAM6_INDEX,
111+
DMA1_STREAM6_INDEX,
112112
#endif
113113
#ifdef DMA1_Stream7
114-
DMA1_STREAM7_INDEX,
114+
DMA1_STREAM7_INDEX,
115115
#endif
116116
#ifdef DMA2_Stream0
117-
DMA2_STREAM0_INDEX,
117+
DMA2_STREAM0_INDEX,
118118
#endif
119119
#ifdef DMA2_Stream1
120-
DMA2_STREAM1_INDEX,
120+
DMA2_STREAM1_INDEX,
121121
#endif
122122
#ifdef DMA2_Stream2
123-
DMA2_STREAM2_INDEX,
123+
DMA2_STREAM2_INDEX,
124124
#endif
125125
#ifdef DMA2_Stream3
126-
DMA2_STREAM3_INDEX,
126+
DMA2_STREAM3_INDEX,
127127
#endif
128128
#ifdef DMA2_Stream4
129-
DMA2_STREAM4_INDEX,
129+
DMA2_STREAM4_INDEX,
130130
#endif
131131
#ifdef DMA2_Stream5
132-
DMA2_STREAM5_INDEX,
132+
DMA2_STREAM5_INDEX,
133133
#endif
134134
#ifdef DMA2_Stream6
135-
DMA2_STREAM6_INDEX,
135+
DMA2_STREAM6_INDEX,
136136
#endif
137137
#ifdef DMA2_Stream7
138-
DMA2_STREAM7_INDEX,
138+
DMA2_STREAM7_INDEX,
139139
#endif
140-
DMA_CHANNEL_NUM
140+
DMA_CHANNEL_NUM
141141
} dma_index_t;
142142

143143
#define NC (dma_index_t)-1
@@ -151,140 +151,140 @@ static DMA_HandleTypeDef *dma_handles[DMA_CHANNEL_NUM] = {NULL};
151151
*/
152152
static dma_index_t get_dma_index(
153153
#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx)
154-
DMA_Stream_TypeDef
154+
DMA_Stream_TypeDef
155155
#else
156-
DMA_Channel_TypeDef
156+
DMA_Channel_TypeDef
157157
#endif
158-
*instance)
158+
*instance)
159159
{
160-
switch ((uint32_t)instance) {
160+
switch ((uint32_t)instance) {
161161
#ifdef DMA1_Channel1
162162
case (uint32_t)DMA1_Channel1:
163-
return DMA1_CHANNEL1_INDEX;
163+
return DMA1_CHANNEL1_INDEX;
164164
#endif
165165
#ifdef DMA1_Channel2
166166
case (uint32_t)DMA1_Channel2:
167-
return DMA1_CHANNEL2_INDEX;
167+
return DMA1_CHANNEL2_INDEX;
168168
#endif
169169
#ifdef DMA1_Channel3
170170
case (uint32_t)DMA1_Channel3:
171-
return DMA1_CHANNEL3_INDEX;
171+
return DMA1_CHANNEL3_INDEX;
172172
#endif
173173
#ifdef DMA1_Channel4
174174
case (uint32_t)DMA1_Channel4:
175-
return DMA1_CHANNEL4_INDEX;
175+
return DMA1_CHANNEL4_INDEX;
176176
#endif
177177
#ifdef DMA1_Channel5
178178
case (uint32_t)DMA1_Channel5:
179-
return DMA1_CHANNEL5_INDEX;
179+
return DMA1_CHANNEL5_INDEX;
180180
#endif
181181
#ifdef DMA1_Channel6
182182
case (uint32_t)DMA1_Channel6:
183-
return DMA1_CHANNEL6_INDEX;
183+
return DMA1_CHANNEL6_INDEX;
184184
#endif
185185
#ifdef DMA1_Channel7
186186
case (uint32_t)DMA1_Channel7:
187-
return DMA1_CHANNEL7_INDEX;
187+
return DMA1_CHANNEL7_INDEX;
188188
#endif
189189
#ifdef DMA2_Channel1
190190
case (uint32_t)DMA2_Channel1:
191-
return DMA2_CHANNEL1_INDEX;
191+
return DMA2_CHANNEL1_INDEX;
192192
#endif
193193
#ifdef DMA2_Channel2
194194
case (uint32_t)DMA2_Channel2:
195-
return DMA2_CHANNEL2_INDEX;
195+
return DMA2_CHANNEL2_INDEX;
196196
#endif
197197
#ifdef DMA2_Channel3
198198
case (uint32_t)DMA2_Channel3:
199-
return DMA2_CHANNEL3_INDEX;
199+
return DMA2_CHANNEL3_INDEX;
200200
#endif
201201
#ifdef DMA2_Channel4
202202
case (uint32_t)DMA2_Channel4:
203-
return DMA2_CHANNEL4_INDEX;
203+
return DMA2_CHANNEL4_INDEX;
204204
#endif
205205
#ifdef DMA2_Channel5
206206
case (uint32_t)DMA2_Channel5:
207-
return DMA2_CHANNEL5_INDEX;
207+
return DMA2_CHANNEL5_INDEX;
208208
#endif
209209
#ifdef DMA2_Channel6
210210
case (uint32_t)DMA2_Channel6:
211-
return DMA2_CHANNEL6_INDEX;
211+
return DMA2_CHANNEL6_INDEX;
212212
#endif
213213
#ifdef DMA2_Channel7
214214
case (uint32_t)DMA2_Channel7:
215-
return DMA2_CHANNEL7_INDEX;
215+
return DMA2_CHANNEL7_INDEX;
216216
#endif
217217
#ifdef DMA2_Channel8
218218
case (uint32_t)DMA2_Channel8:
219-
return DMA2_CHANNEL8_INDEX;
219+
return DMA2_CHANNEL8_INDEX;
220220
#endif
221221
#ifdef DMA1_Stream0
222222
case (uint32_t)DMA1_Stream0:
223-
return DMA1_STREAM0_INDEX;
223+
return DMA1_STREAM0_INDEX;
224224
#endif
225225
#ifdef DMA1_Stream1
226226
case (uint32_t)DMA1_Stream1:
227-
return DMA1_STREAM1_INDEX;
227+
return DMA1_STREAM1_INDEX;
228228
#endif
229229
#ifdef DMA1_Stream2
230230
case (uint32_t)DMA1_Stream2:
231-
return DMA1_STREAM2_INDEX;
231+
return DMA1_STREAM2_INDEX;
232232
#endif
233233
#ifdef DMA1_Stream3
234234
case (uint32_t)DMA1_Stream3:
235-
return DMA1_STREAM3_INDEX;
235+
return DMA1_STREAM3_INDEX;
236236
#endif
237237
#ifdef DMA1_Stream4
238238
case (uint32_t)DMA1_Stream4:
239-
return DMA1_STREAM4_INDEX;
239+
return DMA1_STREAM4_INDEX;
240240
#endif
241241
#ifdef DMA1_Stream5
242242
case (uint32_t)DMA1_Stream5:
243-
return DMA1_STREAM5_INDEX;
243+
return DMA1_STREAM5_INDEX;
244244
#endif
245245
#ifdef DMA1_Stream6
246246
case (uint32_t)DMA1_Stream6:
247-
return DMA1_STREAM6_INDEX;
247+
return DMA1_STREAM6_INDEX;
248248
#endif
249249
#ifdef DMA1_Stream7
250250
case (uint32_t)DMA1_Stream7:
251-
return DMA1_STREAM7_INDEX;
251+
return DMA1_STREAM7_INDEX;
252252
#endif
253253
#ifdef DMA2_Stream0
254254
case (uint32_t)DMA2_Stream0:
255-
return DMA2_STREAM0_INDEX;
255+
return DMA2_STREAM0_INDEX;
256256
#endif
257257
#ifdef DMA2_Stream1
258258
case (uint32_t)DMA2_Stream1:
259-
return DMA2_STREAM1_INDEX;
259+
return DMA2_STREAM1_INDEX;
260260
#endif
261261
#ifdef DMA2_Stream2
262262
case (uint32_t)DMA2_Stream2:
263-
return DMA2_STREAM2_INDEX;
263+
return DMA2_STREAM2_INDEX;
264264
#endif
265265
#ifdef DMA2_Stream3
266266
case (uint32_t)DMA2_Stream3:
267-
return DMA2_STREAM3_INDEX;
267+
return DMA2_STREAM3_INDEX;
268268
#endif
269269
#ifdef DMA2_Stream4
270270
case (uint32_t)DMA2_Stream4:
271-
return DMA2_STREAM4_INDEX;
271+
return DMA2_STREAM4_INDEX;
272272
#endif
273273
#ifdef DMA2_Stream5
274274
case (uint32_t)DMA2_Stream5:
275-
return DMA2_STREAM5_INDEX;
275+
return DMA2_STREAM5_INDEX;
276276
#endif
277277
#ifdef DMA2_Stream6
278278
case (uint32_t)DMA2_Stream6:
279-
return DMA2_STREAM6_INDEX;
279+
return DMA2_STREAM6_INDEX;
280280
#endif
281281
#ifdef DMA2_Stream7
282282
case (uint32_t)DMA2_Stream7:
283-
return DMA2_STREAM7_INDEX;
283+
return DMA2_STREAM7_INDEX;
284284
#endif
285285
default:
286-
return NC;
287-
}
286+
return NC;
287+
}
288288
}
289289

290290
/**
@@ -294,140 +294,140 @@ static dma_index_t get_dma_index(
294294
*/
295295
IRQn_Type get_dma_interrupt(
296296
#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx)
297-
DMA_Stream_TypeDef
297+
DMA_Stream_TypeDef
298298
#else
299-
DMA_Channel_TypeDef
299+
DMA_Channel_TypeDef
300300
#endif
301-
*instance)
301+
*instance)
302302
{
303-
switch ((uint32_t)instance) {
303+
switch ((uint32_t)instance) {
304304
#ifdef DMA1_Channel1
305305
case (uint32_t)DMA1_Channel1:
306-
return DMA1_Channel1_IRQn;
306+
return DMA1_Channel1_IRQn;
307307
#endif
308308
#ifdef DMA1_Channel2
309309
case (uint32_t)DMA1_Channel2:
310-
return DMA1_Channel2_IRQn;
310+
return DMA1_Channel2_IRQn;
311311
#endif
312312
#ifdef DMA1_Channel3
313313
case (uint32_t)DMA1_Channel3:
314-
return DMA1_Channel3_IRQn;
314+
return DMA1_Channel3_IRQn;
315315
#endif
316316
#ifdef DMA1_Channel4
317317
case (uint32_t)DMA1_Channel4:
318-
return DMA1_Channel4_IRQn;
318+
return DMA1_Channel4_IRQn;
319319
#endif
320320
#ifdef DMA1_Channel5
321321
case (uint32_t)DMA1_Channel5:
322-
return DMA1_Channel5_IRQn;
322+
return DMA1_Channel5_IRQn;
323323
#endif
324324
#ifdef DMA1_Channel6
325325
case (uint32_t)DMA1_Channel6:
326-
return DMA1_Channel6_IRQn;
326+
return DMA1_Channel6_IRQn;
327327
#endif
328328
#ifdef DMA1_Channel7
329329
case (uint32_t)DMA1_Channel7:
330-
return DMA1_Channel7_IRQn;
330+
return DMA1_Channel7_IRQn;
331331
#endif
332332
#ifdef DMA2_Channel1
333333
case (uint32_t)DMA2_Channel1:
334-
return DMA2_Channel1_IRQn;
334+
return DMA2_Channel1_IRQn;
335335
#endif
336336
#ifdef DMA2_Channel2
337337
case (uint32_t)DMA2_Channel2:
338-
return DMA2_Channel2_IRQn;
338+
return DMA2_Channel2_IRQn;
339339
#endif
340340
#ifdef DMA2_Channel3
341341
case (uint32_t)DMA2_Channel3:
342-
return DMA2_Channel3_IRQn;
342+
return DMA2_Channel3_IRQn;
343343
#endif
344344
#ifdef DMA2_Channel4
345345
case (uint32_t)DMA2_Channel4:
346-
return DMA2_Channel4_IRQn;
346+
return DMA2_Channel4_IRQn;
347347
#endif
348348
#ifdef DMA2_Channel5
349349
case (uint32_t)DMA2_Channel5:
350-
return DMA2_Channel5_IRQn;
350+
return DMA2_Channel5_IRQn;
351351
#endif
352352
#ifdef DMA2_Channel6
353353
case (uint32_t)DMA2_Channel6:
354-
return DMA2_Channel6_IRQn;
354+
return DMA2_Channel6_IRQn;
355355
#endif
356356
#ifdef DMA2_Channel7
357357
case (uint32_t)DMA2_Channel7:
358-
return DMA2_Channel7_IRQn;
358+
return DMA2_Channel7_IRQn;
359359
#endif
360360
#ifdef DMA2_Channel8
361361
case (uint32_t)DMA2_Channel8:
362-
return DMA2_Channel8_IRQn;
362+
return DMA2_Channel8_IRQn;
363363
#endif
364364
#ifdef DMA1_Stream0
365365
case (uint32_t)DMA1_Stream0:
366-
return DMA1_Stream0_IRQn;
366+
return DMA1_Stream0_IRQn;
367367
#endif
368368
#ifdef DMA1_Stream1
369369
case (uint32_t)DMA1_Stream1:
370-
return DMA1_Stream1_IRQn;
370+
return DMA1_Stream1_IRQn;
371371
#endif
372372
#ifdef DMA1_Stream2
373373
case (uint32_t)DMA1_Stream2:
374-
return DMA1_Stream2_IRQn;
374+
return DMA1_Stream2_IRQn;
375375
#endif
376376
#ifdef DMA1_Stream3
377377
case (uint32_t)DMA1_Stream3:
378-
return DMA1_Stream3_IRQn;
378+
return DMA1_Stream3_IRQn;
379379
#endif
380380
#ifdef DMA1_Stream4
381381
case (uint32_t)DMA1_Stream4:
382-
return DMA1_Stream4_IRQn;
382+
return DMA1_Stream4_IRQn;
383383
#endif
384384
#ifdef DMA1_Stream5
385385
case (uint32_t)DMA1_Stream5:
386-
return DMA1_Stream5_IRQn;
386+
return DMA1_Stream5_IRQn;
387387
#endif
388388
#ifdef DMA1_Stream6
389389
case (uint32_t)DMA1_Stream6:
390-
return DMA1_Stream6_IRQn;
390+
return DMA1_Stream6_IRQn;
391391
#endif
392392
#ifdef DMA1_Stream7
393393
case (uint32_t)DMA1_Stream7:
394-
return DMA1_Stream7_IRQn;
394+
return DMA1_Stream7_IRQn;
395395
#endif
396396
#ifdef DMA2_Stream0
397397
case (uint32_t)DMA2_Stream0:
398-
return DMA2_Stream0_IRQn;
398+
return DMA2_Stream0_IRQn;
399399
#endif
400400
#ifdef DMA2_Stream1
401401
case (uint32_t)DMA2_Stream1:
402-
return DMA2_Stream1_IRQn;
402+
return DMA2_Stream1_IRQn;
403403
#endif
404404
#ifdef DMA2_Stream2
405405
case (uint32_t)DMA2_Stream2:
406-
return DMA2_Stream2_IRQn;
406+
return DMA2_Stream2_IRQn;
407407
#endif
408408
#ifdef DMA2_Stream3
409409
case (uint32_t)DMA2_Stream3:
410-
return DMA2_Stream3_IRQn;
410+
return DMA2_Stream3_IRQn;
411411
#endif
412412
#ifdef DMA2_Stream4
413413
case (uint32_t)DMA2_Stream4:
414-
return DMA2_Stream4_IRQn;
414+
return DMA2_Stream4_IRQn;
415415
#endif
416416
#ifdef DMA2_Stream5
417417
case (uint32_t)DMA2_Stream5:
418-
return DMA2_Stream5_IRQn;
418+
return DMA2_Stream5_IRQn;
419419
#endif
420420
#ifdef DMA2_Stream6
421421
case (uint32_t)DMA2_Stream6:
422-
return DMA2_Stream6_IRQn;
422+
return DMA2_Stream6_IRQn;
423423
#endif
424424
#ifdef DMA2_Stream7
425425
case (uint32_t)DMA2_Stream7:
426-
return DMA2_Stream7_IRQn;
426+
return DMA2_Stream7_IRQn;
427427
#endif
428428
default:
429-
return NC;
430-
}
429+
return NC;
430+
}
431431
}
432432

433433
/**
@@ -437,11 +437,11 @@ IRQn_Type get_dma_interrupt(
437437
*/
438438
void prepare_dma(DMA_HandleTypeDef *dma_handle)
439439
{
440-
dma_index_t dma_index = get_dma_index(dma_handle->Instance);
441-
if (dma_index == NC) {
442-
return;
443-
}
444-
dma_handles[dma_index] = dma_handle;
440+
dma_index_t dma_index = get_dma_index(dma_handle->Instance);
441+
if (dma_index == NC) {
442+
return;
443+
}
444+
dma_handles[dma_index] = dma_handle;
445445
}
446446

447447
/**
@@ -451,11 +451,11 @@ void prepare_dma(DMA_HandleTypeDef *dma_handle)
451451
*/
452452
void end_dma(DMA_HandleTypeDef *dma_handle)
453453
{
454-
dma_index_t dma_index = get_dma_index(dma_handle->Instance);
455-
if (dma_index == NC) {
456-
return;
457-
}
458-
dma_handles[dma_index] = NULL;
454+
dma_index_t dma_index = get_dma_index(dma_handle->Instance);
455+
if (dma_index == NC) {
456+
return;
457+
}
458+
dma_handles[dma_index] = NULL;
459459
}
460460

461461
#ifdef DMA1_Channel1
@@ -466,9 +466,9 @@ void end_dma(DMA_HandleTypeDef *dma_handle)
466466
*/
467467
void DMA1_Channel1_IRQHandler()
468468
{
469-
if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) {
470-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]);
471-
}
469+
if (dma_handles[DMA1_CHANNEL1_INDEX] != NULL) {
470+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL1_INDEX]);
471+
}
472472
}
473473
#endif
474474

@@ -480,9 +480,9 @@ void DMA1_Channel1_IRQHandler()
480480
*/
481481
void DMA1_Channel2_IRQHandler()
482482
{
483-
if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) {
484-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]);
485-
}
483+
if (dma_handles[DMA1_CHANNEL2_INDEX] != NULL) {
484+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL2_INDEX]);
485+
}
486486
}
487487
#endif
488488

@@ -494,9 +494,9 @@ void DMA1_Channel2_IRQHandler()
494494
*/
495495
void DMA1_Channel3_IRQHandler()
496496
{
497-
if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) {
498-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]);
499-
}
497+
if (dma_handles[DMA1_CHANNEL3_INDEX] != NULL) {
498+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL3_INDEX]);
499+
}
500500
}
501501
#endif
502502

@@ -508,9 +508,9 @@ void DMA1_Channel3_IRQHandler()
508508
*/
509509
void DMA1_Channel4_IRQHandler()
510510
{
511-
if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) {
512-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]);
513-
}
511+
if (dma_handles[DMA1_CHANNEL4_INDEX] != NULL) {
512+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL4_INDEX]);
513+
}
514514
}
515515
#endif
516516

@@ -522,9 +522,9 @@ void DMA1_Channel4_IRQHandler()
522522
*/
523523
void DMA1_Channel5_IRQHandler()
524524
{
525-
if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) {
526-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]);
527-
}
525+
if (dma_handles[DMA1_CHANNEL5_INDEX] != NULL) {
526+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL5_INDEX]);
527+
}
528528
}
529529
#endif
530530

@@ -535,9 +535,9 @@ void DMA1_Channel5_IRQHandler()
535535
*/
536536
void DMA1_Channel6_IRQHandler()
537537
{
538-
if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) {
539-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]);
540-
}
538+
if (dma_handles[DMA1_CHANNEL6_INDEX] != NULL) {
539+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL6_INDEX]);
540+
}
541541
}
542542
#endif
543543

@@ -549,9 +549,9 @@ void DMA1_Channel6_IRQHandler()
549549
*/
550550
void DMA1_Channel7_IRQHandler()
551551
{
552-
if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) {
553-
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]);
554-
}
552+
if (dma_handles[DMA1_CHANNEL7_INDEX] != NULL) {
553+
HAL_DMA_IRQHandler(dma_handles[DMA1_CHANNEL7_INDEX]);
554+
}
555555
}
556556
#endif
557557

@@ -563,9 +563,9 @@ void DMA1_Channel7_IRQHandler()
563563
*/
564564
void DMA2_Channel1_IRQHandler()
565565
{
566-
if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) {
567-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]);
568-
}
566+
if (dma_handles[DMA2_CHANNEL1_INDEX] != NULL) {
567+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL1_INDEX]);
568+
}
569569
}
570570
#endif
571571

@@ -577,9 +577,9 @@ void DMA2_Channel1_IRQHandler()
577577
*/
578578
void DMA2_Channel2_IRQHandler()
579579
{
580-
if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) {
581-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]);
582-
}
580+
if (dma_handles[DMA2_CHANNEL2_INDEX] != NULL) {
581+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL2_INDEX]);
582+
}
583583
}
584584
#endif
585585

@@ -591,9 +591,9 @@ void DMA2_Channel2_IRQHandler()
591591
*/
592592
void DMA2_Channel3_IRQHandler()
593593
{
594-
if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) {
595-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]);
596-
}
594+
if (dma_handles[DMA2_CHANNEL3_INDEX] != NULL) {
595+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL3_INDEX]);
596+
}
597597
}
598598
#endif
599599

@@ -605,9 +605,9 @@ void DMA2_Channel3_IRQHandler()
605605
*/
606606
void DMA2_Channel4_IRQHandler()
607607
{
608-
if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) {
609-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]);
610-
}
608+
if (dma_handles[DMA2_CHANNEL4_INDEX] != NULL) {
609+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL4_INDEX]);
610+
}
611611
}
612612
#endif
613613

@@ -619,9 +619,9 @@ void DMA2_Channel4_IRQHandler()
619619
*/
620620
void DMA2_Channel5_IRQHandler()
621621
{
622-
if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) {
623-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]);
624-
}
622+
if (dma_handles[DMA2_CHANNEL5_INDEX] != NULL) {
623+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL5_INDEX]);
624+
}
625625
}
626626
#endif
627627

@@ -633,9 +633,9 @@ void DMA2_Channel5_IRQHandler()
633633
*/
634634
void DMA2_Channel6_IRQHandler()
635635
{
636-
if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) {
637-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]);
638-
}
636+
if (dma_handles[DMA2_CHANNEL6_INDEX] != NULL) {
637+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL6_INDEX]);
638+
}
639639
}
640640
#endif
641641

@@ -647,9 +647,9 @@ void DMA2_Channel6_IRQHandler()
647647
*/
648648
void DMA2_Channel7_IRQHandler()
649649
{
650-
if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) {
651-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]);
652-
}
650+
if (dma_handles[DMA2_CHANNEL7_INDEX] != NULL) {
651+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL7_INDEX]);
652+
}
653653
}
654654
#endif
655655

@@ -661,153 +661,153 @@ void DMA2_Channel7_IRQHandler()
661661
*/
662662
void DMA2_Channel8_IRQHandler()
663663
{
664-
if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) {
665-
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]);
666-
}
664+
if (dma_handles[DMA2_CHANNEL8_INDEX] != NULL) {
665+
HAL_DMA_IRQHandler(dma_handles[DMA2_CHANNEL8_INDEX]);
666+
}
667667
}
668668
#endif
669669

670670
#ifdef DMA1_Stream0
671671
void DMA1_Stream0_IRQHandler()
672672
{
673-
if (dma_handles[DMA1_STREAM0_INDEX] != NULL) {
674-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]);
675-
}
673+
if (dma_handles[DMA1_STREAM0_INDEX] != NULL) {
674+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM0_INDEX]);
675+
}
676676
}
677677
#endif
678678

679679
#ifdef DMA1_Stream1
680680
void DMA1_Stream1_IRQHandler()
681681
{
682-
if (dma_handles[DMA1_STREAM1_INDEX] != NULL) {
683-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]);
684-
}
682+
if (dma_handles[DMA1_STREAM1_INDEX] != NULL) {
683+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM1_INDEX]);
684+
}
685685
}
686686
#endif
687687

688688
#ifdef DMA1_Stream2
689689
void DMA1_Stream2_IRQHandler()
690690
{
691-
if (dma_handles[DMA1_STREAM2_INDEX] != NULL) {
692-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]);
693-
}
691+
if (dma_handles[DMA1_STREAM2_INDEX] != NULL) {
692+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM2_INDEX]);
693+
}
694694
}
695695
#endif
696696

697697
#ifdef DMA1_Stream3
698698
void DMA1_Stream3_IRQHandler()
699699
{
700-
if (dma_handles[DMA1_STREAM3_INDEX] != NULL) {
701-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]);
702-
}
700+
if (dma_handles[DMA1_STREAM3_INDEX] != NULL) {
701+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM3_INDEX]);
702+
}
703703
}
704704
#endif
705705

706706
#ifdef DMA1_Stream4
707707
void DMA1_Stream4_IRQHandler()
708708
{
709-
if (dma_handles[DMA1_STREAM4_INDEX] != NULL) {
710-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]);
711-
}
709+
if (dma_handles[DMA1_STREAM4_INDEX] != NULL) {
710+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM4_INDEX]);
711+
}
712712
}
713713
#endif
714714

715715
#ifdef DMA1_Stream5
716716
void DMA1_Stream5_IRQHandler()
717717
{
718-
if (dma_handles[DMA1_STREAM5_INDEX] != NULL) {
719-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]);
720-
}
718+
if (dma_handles[DMA1_STREAM5_INDEX] != NULL) {
719+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM5_INDEX]);
720+
}
721721
}
722722
#endif
723723

724724
#ifdef DMA1_Stream6
725725
void DMA1_Stream6_IRQHandler()
726726
{
727-
if (dma_handles[DMA1_STREAM6_INDEX] != NULL) {
728-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]);
729-
}
727+
if (dma_handles[DMA1_STREAM6_INDEX] != NULL) {
728+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM6_INDEX]);
729+
}
730730
}
731731
#endif
732732

733733
#ifdef DMA1_Stream7
734734
void DMA1_Stream7_IRQHandler()
735735
{
736-
if (dma_handles[DMA1_STREAM7_INDEX] != NULL) {
737-
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]);
738-
}
736+
if (dma_handles[DMA1_STREAM7_INDEX] != NULL) {
737+
HAL_DMA_IRQHandler(dma_handles[DMA1_STREAM7_INDEX]);
738+
}
739739
}
740740
#endif
741741

742742
#ifdef DMA2_Stream0
743743
void DMA2_Stream0_IRQHandler()
744744
{
745-
if (dma_handles[DMA2_STREAM0_INDEX] != NULL) {
746-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]);
747-
}
745+
if (dma_handles[DMA2_STREAM0_INDEX] != NULL) {
746+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM0_INDEX]);
747+
}
748748
}
749749
#endif
750750

751751
#ifdef DMA2_Stream1
752752
void DMA2_Stream1_IRQHandler()
753753
{
754-
if (dma_handles[DMA2_STREAM1_INDEX] != NULL) {
755-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]);
756-
}
754+
if (dma_handles[DMA2_STREAM1_INDEX] != NULL) {
755+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM1_INDEX]);
756+
}
757757
}
758758
#endif
759759

760760
#ifdef DMA2_Stream2
761761
void DMA2_Stream2_IRQHandler()
762762
{
763-
if (dma_handles[DMA2_STREAM2_INDEX] != NULL) {
764-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]);
765-
}
763+
if (dma_handles[DMA2_STREAM2_INDEX] != NULL) {
764+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM2_INDEX]);
765+
}
766766
}
767767
#endif
768768

769769
#ifdef DMA2_Stream3
770770
void DMA2_Stream3_IRQHandler()
771771
{
772-
if (dma_handles[DMA2_STREAM3_INDEX] != NULL) {
773-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]);
774-
}
772+
if (dma_handles[DMA2_STREAM3_INDEX] != NULL) {
773+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM3_INDEX]);
774+
}
775775
}
776776
#endif
777777

778778
#ifdef DMA2_Stream4
779779
void DMA2_Stream4_IRQHandler()
780780
{
781-
if (dma_handles[DMA2_STREAM4_INDEX] != NULL) {
782-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]);
783-
}
781+
if (dma_handles[DMA2_STREAM4_INDEX] != NULL) {
782+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM4_INDEX]);
783+
}
784784
}
785785
#endif
786786

787787
#ifdef DMA2_Stream5
788788
void DMA2_Stream5_IRQHandler()
789789
{
790-
if (dma_handles[DMA2_STREAM5_INDEX] != NULL) {
791-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]);
792-
}
790+
if (dma_handles[DMA2_STREAM5_INDEX] != NULL) {
791+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM5_INDEX]);
792+
}
793793
}
794794
#endif
795795

796796
#ifdef DMA2_Stream6
797797
void DMA2_Stream6_IRQHandler()
798798
{
799-
if (dma_handles[DMA2_STREAM6_INDEX] != NULL) {
800-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]);
801-
}
799+
if (dma_handles[DMA2_STREAM6_INDEX] != NULL) {
800+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM6_INDEX]);
801+
}
802802
}
803803
#endif
804804

805805
#ifdef DMA2_Stream7
806806
void DMA2_Stream7_IRQHandler()
807807
{
808-
if (dma_handles[DMA2_STREAM7_INDEX] != NULL) {
809-
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]);
810-
}
808+
if (dma_handles[DMA2_STREAM7_INDEX] != NULL) {
809+
HAL_DMA_IRQHandler(dma_handles[DMA2_STREAM7_INDEX]);
810+
}
811811
}
812812
#endif
813813

‎cores/arduino/stm32/dma.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,11 +53,11 @@ extern "C" {
5353
*/
5454
IRQn_Type get_dma_interrupt(
5555
#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx)
56-
DMA_Stream_TypeDef
56+
DMA_Stream_TypeDef
5757
#else
58-
DMA_Channel_TypeDef
58+
DMA_Channel_TypeDef
5959
#endif
60-
*instance);
60+
*instance);
6161

6262
/**
6363
* @brief This function will store the DMA handle in the appropriate slot

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