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fpistmfpistm
authoredJan 4, 2025··
Merge pull request #2615 from ALTracer/feature/variant_WeAct_G474CE
variant(g4): Add WeActStudio.STM32G474CoreBoard support
2 parents bb640bf + 59ed28d commit 65677a2

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‎README.md

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -492,6 +492,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
492492

493493
| Status | Device(s) | Name | Release | Notes |
494494
| :----: | :-------: | ---- | :-----: | :---- |
495+
| :yellow_heart: | STM32G474CEU | WeAct G474CE | **2.10.0** | [More info](https://github.com/WeActStudio/WeActStudio.STM32G474CoreBoard) |
495496
| :green_heart: | STM32G431C6<br>STM32G431C8<br>STM32G431CB | Generic Board | *2.4.0* | |
496497
| :green_heart: | STM32G431C6U<br>STM32G431C8U<br>STM32G431CBU | Generic Board | *2.0.0* | |
497498
| :green_heart: | STM32G431M6<br>STM32G431M8<br>STM32G431MB | Generic Board | *2.4.0* | |
@@ -509,25 +510,29 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
509510
| :green_heart: | STM32G471QC<br>STM32G471QE | Generic Board | *2.4.0* | |
510511
| :green_heart: | STM32G471RC<br>STM32G471RE | Generic Board | *2.4.0* | |
511512
| :green_heart: | STM32G471VC<br>STM32G471VE | Generic Board | *2.4.0* | |
512-
| :green_heart: | STM32G473CB<br>STM32G473CC<br>STM32G473CE | Generic Board | *2.4.0* | |
513+
| :green_heart: | STM32G473CBT<br>STM32G473CCT<br>STM32G473CET | Generic Board | *2.4.0* | |
514+
| :yellow_heart: | STM32G473CBU<br>STM32G473CCU<br>STM32G473CEU | Generic Board | **2.10.0** | |
513515
| :green_heart: | STM32G473MB<br>STM32G473MC<br>STM32G473ME | Generic Board | *2.4.0* | |
514516
| :green_heart: | STM32G473PB<br>STM32G473PC<br>STM32G473PE | Generic Board | *2.4.0* | |
515517
| :green_heart: | STM32G473QB<br>STM32G473QC<br>STM32G473QE | Generic Board | *2.4.0* | |
516518
| :green_heart: | STM32G473RB<br>STM32G473RC<br>STM32G473RE | Generic Board | *2.0.0* | |
517519
| :green_heart: | STM32G473VB<br>STM32G473VC<br>STM32G473VE | Generic Board | *2.4.0* | |
518-
| :green_heart: | STM32G474CB<br>STM32G474CC<br>STM32G474CE | Generic Board | *2.4.0* | |
520+
| :green_heart: | STM32G474CBT<br>STM32G474CCT<br>STM32G474CET | Generic Board | *2.4.0* | |
521+
| :yellow_heart: | STM32G474CBU<br>STM32G474CCU<br>STM32G474CEU | Generic Board | **2.10.0** | |
519522
| :green_heart: | STM32G474MB<br>STM32G474MC<br>STM32G474ME | Generic Board | *2.4.0* | |
520523
| :green_heart: | STM32G474PB<br>STM32G474PC<br>STM32G474PE | Generic Board | *2.4.0* | |
521524
| :green_heart: | STM32G474QB<br>STM32G474QC<br>STM32G474QE | Generic Board | *2.4.0* | |
522525
| :green_heart: | STM32G474RB<br>STM32G474RC<br>STM32G474RE | Generic Board | *2.0.0* | |
523526
| :green_heart: | STM32G474VB<br>STM32G474VC<br>STM32G474VE | Generic Board | *2.4.0* | |
524-
| :green_heart: | STM32G483CE | Generic Board | *2.4.0* | |
527+
| :green_heart: | STM32G483CET | Generic Board | *2.4.0* | |
528+
| :yellow_heart: | STM32G483CEU | Generic Board | **2.10.0** | |
525529
| :green_heart: | STM32G483ME | Generic Board | *2.4.0* | |
526530
| :green_heart: | STM32G483PE | Generic Board | *2.4.0* | |
527531
| :green_heart: | STM32G483QE | Generic Board | *2.4.0* | |
528532
| :green_heart: | STM32G483RE | Generic Board | *2.0.0* | |
529533
| :green_heart: | STM32G483VE | Generic Board | *2.4.0* | |
530-
| :green_heart: | STM32G484CE | Generic Board | *2.4.0* | |
534+
| :green_heart: | STM32G484CET | Generic Board | *2.4.0* | |
535+
| :yellow_heart: | STM32G484CEU | Generic Board | **2.10.0** | |
531536
| :green_heart: | STM32G484ME | Generic Board | *2.4.0* | |
532537
| :green_heart: | STM32G484PE | Generic Board | *2.4.0* | |
533538
| :green_heart: | STM32G484QE | Generic Board | *2.4.0* | |

‎boards.txt

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7453,6 +7453,16 @@ GenG4.openocd.target=stm32g4x
74537453
GenG4.vid.0=0x0483
74547454
GenG4.pid.0=0x5740
74557455

7456+
# WEACT_G474CE board
7457+
GenG4.menu.pnum.WEACT_G474CE=WeAct G474CE
7458+
GenG4.menu.pnum.WEACT_G474CE.upload.maximum_size=524288
7459+
GenG4.menu.pnum.WEACT_G474CE.upload.maximum_data_size=131072
7460+
GenG4.menu.pnum.WEACT_G474CE.build.board=WEACT_G474CE
7461+
GenG4.menu.pnum.WEACT_G474CE.build.product_line=STM32G474xx
7462+
GenG4.menu.pnum.WEACT_G474CE.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
7463+
GenG4.menu.pnum.WEACT_G474CE.build.variant_h=variant_{build.board}.h
7464+
GenG4.menu.pnum.WEACT_G474CE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
7465+
74567466
# Generic G431C6Tx
74577467
GenG4.menu.pnum.GENERIC_G431C6TX=Generic G431C6Tx
74587468
GenG4.menu.pnum.GENERIC_G431C6TX.upload.maximum_size=32768
@@ -7885,6 +7895,15 @@ GenG4.menu.pnum.GENERIC_G473CBTX.build.product_line=STM32G473xx
78857895
GenG4.menu.pnum.GENERIC_G473CBTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
78867896
GenG4.menu.pnum.GENERIC_G473CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd
78877897

7898+
# Generic G473CBUx
7899+
GenG4.menu.pnum.GENERIC_G473CBUX=Generic G473CBUx
7900+
GenG4.menu.pnum.GENERIC_G473CBUX.upload.maximum_size=131072
7901+
GenG4.menu.pnum.GENERIC_G473CBUX.upload.maximum_data_size=131072
7902+
GenG4.menu.pnum.GENERIC_G473CBUX.build.board=GENERIC_G473CBUX
7903+
GenG4.menu.pnum.GENERIC_G473CBUX.build.product_line=STM32G473xx
7904+
GenG4.menu.pnum.GENERIC_G473CBUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
7905+
GenG4.menu.pnum.GENERIC_G473CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd
7906+
78887907
# Generic G473CCTx
78897908
GenG4.menu.pnum.GENERIC_G473CCTX=Generic G473CCTx
78907909
GenG4.menu.pnum.GENERIC_G473CCTX.upload.maximum_size=262144
@@ -7894,6 +7913,15 @@ GenG4.menu.pnum.GENERIC_G473CCTX.build.product_line=STM32G473xx
78947913
GenG4.menu.pnum.GENERIC_G473CCTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
78957914
GenG4.menu.pnum.GENERIC_G473CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd
78967915

7916+
# Generic G473CCUx
7917+
GenG4.menu.pnum.GENERIC_G473CCUX=Generic G473CCUx
7918+
GenG4.menu.pnum.GENERIC_G473CCUX.upload.maximum_size=262144
7919+
GenG4.menu.pnum.GENERIC_G473CCUX.upload.maximum_data_size=131072
7920+
GenG4.menu.pnum.GENERIC_G473CCUX.build.board=GENERIC_G473CCUX
7921+
GenG4.menu.pnum.GENERIC_G473CCUX.build.product_line=STM32G473xx
7922+
GenG4.menu.pnum.GENERIC_G473CCUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
7923+
GenG4.menu.pnum.GENERIC_G473CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd
7924+
78977925
# Generic G473CETx
78987926
GenG4.menu.pnum.GENERIC_G473CETX=Generic G473CETx
78997927
GenG4.menu.pnum.GENERIC_G473CETX.upload.maximum_size=524288
@@ -7903,6 +7931,15 @@ GenG4.menu.pnum.GENERIC_G473CETX.build.product_line=STM32G473xx
79037931
GenG4.menu.pnum.GENERIC_G473CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
79047932
GenG4.menu.pnum.GENERIC_G473CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd
79057933

7934+
# Generic G473CEUx
7935+
GenG4.menu.pnum.GENERIC_G473CEUX=Generic G473CEUx
7936+
GenG4.menu.pnum.GENERIC_G473CEUX.upload.maximum_size=524288
7937+
GenG4.menu.pnum.GENERIC_G473CEUX.upload.maximum_data_size=131072
7938+
GenG4.menu.pnum.GENERIC_G473CEUX.build.board=GENERIC_G473CEUX
7939+
GenG4.menu.pnum.GENERIC_G473CEUX.build.product_line=STM32G473xx
7940+
GenG4.menu.pnum.GENERIC_G473CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
7941+
GenG4.menu.pnum.GENERIC_G473CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd
7942+
79067943
# Generic G473MBTx
79077944
GenG4.menu.pnum.GENERIC_G473MBTX=Generic G473MBTx
79087945
GenG4.menu.pnum.GENERIC_G473MBTX.upload.maximum_size=131072
@@ -8083,6 +8120,15 @@ GenG4.menu.pnum.GENERIC_G474CBTX.build.product_line=STM32G474xx
80838120
GenG4.menu.pnum.GENERIC_G474CBTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
80848121
GenG4.menu.pnum.GENERIC_G474CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
80858122

8123+
# Generic G474CBUx
8124+
GenG4.menu.pnum.GENERIC_G474CBUX=Generic G474CBUx
8125+
GenG4.menu.pnum.GENERIC_G474CBUX.upload.maximum_size=131072
8126+
GenG4.menu.pnum.GENERIC_G474CBUX.upload.maximum_data_size=131072
8127+
GenG4.menu.pnum.GENERIC_G474CBUX.build.board=GENERIC_G474CBUX
8128+
GenG4.menu.pnum.GENERIC_G474CBUX.build.product_line=STM32G474xx
8129+
GenG4.menu.pnum.GENERIC_G474CBUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
8130+
GenG4.menu.pnum.GENERIC_G474CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
8131+
80868132
# Generic G474CCTx
80878133
GenG4.menu.pnum.GENERIC_G474CCTX=Generic G474CCTx
80888134
GenG4.menu.pnum.GENERIC_G474CCTX.upload.maximum_size=262144
@@ -8092,6 +8138,15 @@ GenG4.menu.pnum.GENERIC_G474CCTX.build.product_line=STM32G474xx
80928138
GenG4.menu.pnum.GENERIC_G474CCTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
80938139
GenG4.menu.pnum.GENERIC_G474CCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
80948140

8141+
# Generic G474CCUx
8142+
GenG4.menu.pnum.GENERIC_G474CCUX=Generic G474CCUx
8143+
GenG4.menu.pnum.GENERIC_G474CCUX.upload.maximum_size=262144
8144+
GenG4.menu.pnum.GENERIC_G474CCUX.upload.maximum_data_size=131072
8145+
GenG4.menu.pnum.GENERIC_G474CCUX.build.board=GENERIC_G474CCUX
8146+
GenG4.menu.pnum.GENERIC_G474CCUX.build.product_line=STM32G474xx
8147+
GenG4.menu.pnum.GENERIC_G474CCUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
8148+
GenG4.menu.pnum.GENERIC_G474CCUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
8149+
80958150
# Generic G474CETx
80968151
GenG4.menu.pnum.GENERIC_G474CETX=Generic G474CETx
80978152
GenG4.menu.pnum.GENERIC_G474CETX.upload.maximum_size=524288
@@ -8101,6 +8156,15 @@ GenG4.menu.pnum.GENERIC_G474CETX.build.product_line=STM32G474xx
81018156
GenG4.menu.pnum.GENERIC_G474CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
81028157
GenG4.menu.pnum.GENERIC_G474CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
81038158

8159+
# Generic G474CEUx
8160+
GenG4.menu.pnum.GENERIC_G474CEUX=Generic G474CEUx
8161+
GenG4.menu.pnum.GENERIC_G474CEUX.upload.maximum_size=524288
8162+
GenG4.menu.pnum.GENERIC_G474CEUX.upload.maximum_data_size=131072
8163+
GenG4.menu.pnum.GENERIC_G474CEUX.build.board=GENERIC_G474CEUX
8164+
GenG4.menu.pnum.GENERIC_G474CEUX.build.product_line=STM32G474xx
8165+
GenG4.menu.pnum.GENERIC_G474CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
8166+
GenG4.menu.pnum.GENERIC_G474CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
8167+
81048168
# Generic G474MBTx
81058169
GenG4.menu.pnum.GENERIC_G474MBTX=Generic G474MBTx
81068170
GenG4.menu.pnum.GENERIC_G474MBTX.upload.maximum_size=131072
@@ -8281,6 +8345,15 @@ GenG4.menu.pnum.GENERIC_G483CETX.build.product_line=STM32G483xx
82818345
GenG4.menu.pnum.GENERIC_G483CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
82828346
GenG4.menu.pnum.GENERIC_G483CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G483.svd
82838347

8348+
# Generic G483CEUx
8349+
GenG4.menu.pnum.GENERIC_G483CEUX=Generic G483CEUx
8350+
GenG4.menu.pnum.GENERIC_G483CEUX.upload.maximum_size=524288
8351+
GenG4.menu.pnum.GENERIC_G483CEUX.upload.maximum_data_size=131072
8352+
GenG4.menu.pnum.GENERIC_G483CEUX.build.board=GENERIC_G483CEUX
8353+
GenG4.menu.pnum.GENERIC_G483CEUX.build.product_line=STM32G483xx
8354+
GenG4.menu.pnum.GENERIC_G483CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
8355+
GenG4.menu.pnum.GENERIC_G483CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G483.svd
8356+
82848357
# Generic G483METx
82858358
GenG4.menu.pnum.GENERIC_G483METX=Generic G483METx
82868359
GenG4.menu.pnum.GENERIC_G483METX.upload.maximum_size=524288
@@ -8344,6 +8417,15 @@ GenG4.menu.pnum.GENERIC_G484CETX.build.product_line=STM32G484xx
83448417
GenG4.menu.pnum.GENERIC_G484CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
83458418
GenG4.menu.pnum.GENERIC_G484CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd
83468419

8420+
# Generic G484CEUx
8421+
GenG4.menu.pnum.GENERIC_G484CEUX=Generic G484CEUx
8422+
GenG4.menu.pnum.GENERIC_G484CEUX.upload.maximum_size=524288
8423+
GenG4.menu.pnum.GENERIC_G484CEUX.upload.maximum_data_size=131072
8424+
GenG4.menu.pnum.GENERIC_G484CEUX.build.board=GENERIC_G484CEUX
8425+
GenG4.menu.pnum.GENERIC_G484CEUX.build.product_line=STM32G484xx
8426+
GenG4.menu.pnum.GENERIC_G484CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
8427+
GenG4.menu.pnum.GENERIC_G484CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd
8428+
83478429
# Generic G484METx
83488430
GenG4.menu.pnum.GENERIC_G484METX=Generic G484METx
83498431
GenG4.menu.pnum.GENERIC_G484METX.upload.maximum_size=524288

‎cmake/boards_db.cmake

Lines changed: 738 additions & 0 deletions
Large diffs are not rendered by default.

‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2222
generic_clock.c
2323
PeripheralPins.c
2424
variant_generic.cpp
25+
variant_WEACT_G474CE.cpp
2526
)
2627
target_link_libraries(variant_bin PUBLIC variant_usage)
2728

‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/generic_clock.c

Lines changed: 59 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,65 @@
2323
*/
2424
WEAK void SystemClock_Config(void)
2525
{
26-
/* SystemClock_Config can be generated by STM32CubeMX */
27-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
26+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
27+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
28+
#ifdef USBCON
29+
RCC_CRSInitTypeDef pInit = {};
30+
RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
31+
#endif
32+
33+
/* Configure the main internal regulator output voltage */
34+
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
35+
36+
/* Initializes the RCC Oscillators */
37+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
38+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
39+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
40+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
41+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
42+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
43+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
44+
RCC_OscInitStruct.PLL.PLLN = 75;
45+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
46+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
47+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
48+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
49+
Error_Handler();
50+
}
51+
52+
/* Initializes the CPU, AHB and APB buses clocks */
53+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
54+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
55+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
56+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
57+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
58+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
59+
60+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
61+
Error_Handler();
62+
}
63+
64+
#ifdef USBCON
65+
/* Enable the SYSCFG APB clock */
66+
__HAL_RCC_CRS_CLK_ENABLE();
67+
68+
/* Configures CRS */
69+
pInit.Prescaler = RCC_CRS_SYNC_DIV1;
70+
pInit.Source = RCC_CRS_SYNC_SOURCE_USB;
71+
pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
72+
pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
73+
pInit.ErrorLimitValue = 34;
74+
pInit.HSI48CalibrationValue = 32;
75+
76+
HAL_RCCEx_CRSConfig(&pInit);
77+
78+
/* Initializes the peripherals clocks */
79+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
80+
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
81+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
82+
Error_Handler();
83+
}
84+
#endif
2885
}
2986

3087
#endif /* ARDUINO_GENERIC_* */

‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/ldscript.ld

Lines changed: 185 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,185 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32G473CBUx Device from STM32G4 series
9+
** 128Kbytes FLASH
10+
** 128Kbytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2022 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
42+
_Min_Stack_Size = 0x400; /* required amount of stack */
43+
44+
/* Memories definition */
45+
MEMORY
46+
{
47+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
48+
FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
51+
/* Sections */
52+
SECTIONS
53+
{
54+
/* The startup code into "FLASH" Rom type memory */
55+
.isr_vector :
56+
{
57+
. = ALIGN(4);
58+
KEEP(*(.isr_vector)) /* Startup code */
59+
. = ALIGN(4);
60+
} >FLASH
61+
62+
/* The program code and other data into "FLASH" Rom type memory */
63+
.text :
64+
{
65+
. = ALIGN(4);
66+
*(.text) /* .text sections (code) */
67+
*(.text*) /* .text* sections (code) */
68+
*(.glue_7) /* glue arm to thumb code */
69+
*(.glue_7t) /* glue thumb to arm code */
70+
*(.eh_frame)
71+
72+
KEEP (*(.init))
73+
KEEP (*(.fini))
74+
75+
. = ALIGN(4);
76+
_etext = .; /* define a global symbols at end of code */
77+
} >FLASH
78+
79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
84+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
85+
. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab (READONLY) : {
89+
. = ALIGN(4);
90+
*(.ARM.extab* .gnu.linkonce.armextab.*)
91+
. = ALIGN(4);
92+
} >FLASH
93+
94+
.ARM (READONLY) : {
95+
. = ALIGN(4);
96+
__exidx_start = .;
97+
*(.ARM.exidx*)
98+
__exidx_end = .;
99+
. = ALIGN(4);
100+
} >FLASH
101+
102+
.preinit_array (READONLY) :
103+
{
104+
. = ALIGN(4);
105+
PROVIDE_HIDDEN (__preinit_array_start = .);
106+
KEEP (*(.preinit_array*))
107+
PROVIDE_HIDDEN (__preinit_array_end = .);
108+
. = ALIGN(4);
109+
} >FLASH
110+
111+
.init_array (READONLY) :
112+
{
113+
. = ALIGN(4);
114+
PROVIDE_HIDDEN (__init_array_start = .);
115+
KEEP (*(SORT(.init_array.*)))
116+
KEEP (*(.init_array*))
117+
PROVIDE_HIDDEN (__init_array_end = .);
118+
. = ALIGN(4);
119+
} >FLASH
120+
121+
.fini_array (READONLY) :
122+
{
123+
. = ALIGN(4);
124+
PROVIDE_HIDDEN (__fini_array_start = .);
125+
KEEP (*(SORT(.fini_array.*)))
126+
KEEP (*(.fini_array*))
127+
PROVIDE_HIDDEN (__fini_array_end = .);
128+
. = ALIGN(4);
129+
} >FLASH
130+
131+
/* Used by the startup to initialize data */
132+
_sidata = LOADADDR(.data);
133+
134+
/* Initialized data sections into "RAM" Ram type memory */
135+
.data :
136+
{
137+
. = ALIGN(4);
138+
_sdata = .; /* create a global symbol at data start */
139+
*(.data) /* .data sections */
140+
*(.data*) /* .data* sections */
141+
*(.RamFunc) /* .RamFunc sections */
142+
*(.RamFunc*) /* .RamFunc* sections */
143+
144+
. = ALIGN(4);
145+
_edata = .; /* define a global symbol at data end */
146+
147+
} >RAM AT> FLASH
148+
149+
/* Uninitialized data section into "RAM" Ram type memory */
150+
. = ALIGN(4);
151+
.bss :
152+
{
153+
/* This is used by the startup in order to initialize the .bss section */
154+
_sbss = .; /* define a global symbol at bss start */
155+
__bss_start__ = _sbss;
156+
*(.bss)
157+
*(.bss*)
158+
*(COMMON)
159+
160+
. = ALIGN(4);
161+
_ebss = .; /* define a global symbol at bss end */
162+
__bss_end__ = _ebss;
163+
} >RAM
164+
165+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
166+
._user_heap_stack :
167+
{
168+
. = ALIGN(8);
169+
PROVIDE ( end = . );
170+
PROVIDE ( _end = . );
171+
. = . + _Min_Heap_Size;
172+
. = . + _Min_Stack_Size;
173+
. = ALIGN(8);
174+
} >RAM
175+
176+
/* Remove information from the compiler libraries */
177+
/DISCARD/ :
178+
{
179+
libc.a ( * )
180+
libm.a ( * )
181+
libgcc.a ( * )
182+
}
183+
184+
.ARM.attributes 0 : { *(.ARM.attributes) }
185+
}

‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.cpp

Lines changed: 149 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,149 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2024, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#if defined(ARDUINO_WEACT_G474CE)
14+
#include "pins_arduino.h"
15+
16+
// Digital PinName array
17+
const PinName digitalPin[] = {
18+
PA_0, // D0/A0
19+
PA_1, // D1/A1
20+
PA_2, // D2/A2
21+
PA_3, // D3/A3
22+
PA_4, // D4/A4
23+
PA_5, // D5/A5
24+
PA_6, // D6/A6
25+
PA_7, // D7/A7
26+
PA_8, // D8/A8
27+
PA_9, // D9/A9
28+
PA_10, // D10
29+
PA_11, // D11
30+
PA_12, // D12
31+
PA_13, // D13/SWDIO
32+
PA_14, // D14/SWCLK
33+
PA_15, // D15
34+
PB_0, // D16/A10
35+
PB_1, // D17/A11
36+
PB_2, // D18/A12
37+
PB_3, // D19
38+
PB_4, // D20
39+
PB_5, // D21
40+
PB_6, // D22
41+
PB_7, // D23
42+
PB_8, // D24
43+
PB_9, // D25
44+
PB_10, // D26
45+
PB_11, // D27/A13
46+
PB_12, // D28/A14
47+
PB_13, // D29/A15
48+
PB_14, // D30/A16
49+
PB_15, // D31/A17
50+
PC_4, // D32/A18
51+
PC_6, // D33/LED
52+
PC_10, // D34
53+
PC_11, // D35
54+
PC_13, // D36/BTN
55+
PC_14, // D37
56+
PC_15, // D38
57+
PF_0, // D39/A19
58+
PF_1, // D40/A20
59+
PG_10 // D41
60+
};
61+
62+
// Analog (Ax) pin number array
63+
const uint32_t analogInputPin[] = {
64+
0, // A0, PA0
65+
1, // A1, PA1
66+
2, // A2, PA2
67+
3, // A3, PA3
68+
4, // A4, PA4
69+
5, // A5, PA5
70+
6, // A6, PA6
71+
7, // A7, PA7
72+
8, // A8, PA8
73+
9, // A9, PA9
74+
16, // A10, PB0
75+
17, // A11, PB1
76+
18, // A12, PB2
77+
27, // A13, PB11
78+
28, // A14, PB12
79+
29, // A15, PB13
80+
30, // A16, PB14
81+
31, // A17, PB15
82+
32, // A18, PC4
83+
39, // A19, PF0
84+
40 // A20, PF1
85+
};
86+
87+
// ----------------------------------------------------------------------------
88+
89+
#ifdef __cplusplus
90+
extern "C" {
91+
#endif // __cplusplus
92+
93+
/**
94+
* @brief System Clock Configuration
95+
*/
96+
WEAK void SystemClock_Config(void)
97+
{
98+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
99+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
100+
#ifdef USBCON
101+
RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
102+
#endif
103+
104+
/* Configure the main internal regulator output voltage */
105+
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
106+
/* Initializes the CPU, AHB and APB busses clocks */
107+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48
108+
| RCC_OSCILLATORTYPE_HSE;
109+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
110+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
111+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
112+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
113+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
114+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
115+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
116+
RCC_OscInitStruct.PLL.PLLN = 85;
117+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
118+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6;
119+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
120+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
121+
Error_Handler();
122+
}
123+
/* Initializes the CPU, AHB and APB busses clocks */
124+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
125+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
126+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
127+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
128+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
129+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
130+
131+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
132+
Error_Handler();
133+
}
134+
135+
#ifdef USBCON
136+
/* Initializes the peripherals clocks */
137+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
138+
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
139+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
140+
Error_Handler();
141+
}
142+
#endif
143+
}
144+
145+
#ifdef __cplusplus
146+
} // extern "C"
147+
#endif
148+
149+
#endif /* ARDUINO_NUCLEO_G431RB */

‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/variant_WEACT_G474CE.h

Lines changed: 213 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,213 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2024, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#pragma once
14+
15+
/*----------------------------------------------------------------------------
16+
* STM32 pins number
17+
*----------------------------------------------------------------------------*/
18+
#define PA0 PIN_A0
19+
#define PA1 PIN_A1
20+
#define PA2 PIN_A2
21+
#define PA3 PIN_A3
22+
#define PA4 PIN_A4
23+
#define PA5 PIN_A5
24+
#define PA6 PIN_A6
25+
#define PA7 PIN_A7
26+
#define PA8 PIN_A8
27+
#define PA9 PIN_A9
28+
#define PA10 10
29+
#define PA11 11
30+
#define PA12 12
31+
#define PA13 13
32+
#define PA14 14
33+
#define PA15 15
34+
#define PB0 PIN_A10
35+
#define PB1 PIN_A11
36+
#define PB2 PIN_A12
37+
#define PB3 19
38+
#define PB4 20
39+
#define PB5 21
40+
#define PB6 22
41+
#define PB7 23
42+
#define PB8 24
43+
#define PB9 25
44+
#define PB10 26
45+
#define PB11 PIN_A13
46+
#define PB12 PIN_A14
47+
#define PB13 PIN_A15
48+
#define PB14 PIN_A16
49+
#define PB15 PIN_A17
50+
#define PC4 PIN_A18
51+
#define PC6 33 // LED
52+
#define PC10 34
53+
#define PC11 35
54+
#define PC13 36 // BTN
55+
#define PC14 37
56+
#define PC15 38
57+
#define PF0 PIN_A19
58+
#define PF1 PIN_A20
59+
#define PG10 41
60+
61+
// Alternate pins number
62+
#define PA0_ALT1 (PA0 | ALT1)
63+
#define PA1_ALT1 (PA1 | ALT1)
64+
#define PA1_ALT2 (PA1 | ALT2)
65+
#define PA2_ALT1 (PA2 | ALT1)
66+
#define PA2_ALT2 (PA2 | ALT2)
67+
#define PA3_ALT1 (PA3 | ALT1)
68+
#define PA3_ALT2 (PA3 | ALT2)
69+
#define PA4_ALT1 (PA4 | ALT1)
70+
#define PA6_ALT1 (PA6 | ALT1)
71+
#define PA7_ALT1 (PA7 | ALT1)
72+
#define PA7_ALT2 (PA7 | ALT2)
73+
#define PA7_ALT3 (PA7 | ALT3)
74+
#define PA9_ALT1 (PA9 | ALT1)
75+
#define PA10_ALT1 (PA10 | ALT1)
76+
#define PA11_ALT1 (PA11 | ALT1)
77+
#define PA11_ALT2 (PA11 | ALT2)
78+
#define PA12_ALT1 (PA12 | ALT1)
79+
#define PA12_ALT2 (PA12 | ALT2)
80+
#define PA13_ALT1 (PA13 | ALT1)
81+
#define PA15_ALT1 (PA15 | ALT1)
82+
#define PB0_ALT1 (PB0 | ALT1)
83+
#define PB0_ALT2 (PB0 | ALT2)
84+
#define PB1_ALT1 (PB1 | ALT1)
85+
#define PB1_ALT2 (PB1 | ALT2)
86+
#define PB2_ALT1 (PB2 | ALT1)
87+
#define PB3_ALT1 (PB3 | ALT1)
88+
#define PB4_ALT1 (PB4 | ALT1)
89+
#define PB4_ALT2 (PB4 | ALT2)
90+
#define PB5_ALT1 (PB5 | ALT1)
91+
#define PB5_ALT2 (PB5 | ALT2)
92+
#define PB6_ALT1 (PB6 | ALT1)
93+
#define PB6_ALT2 (PB6 | ALT2)
94+
#define PB7_ALT1 (PB7 | ALT1)
95+
#define PB7_ALT2 (PB7 | ALT2)
96+
#define PB8_ALT1 (PB8 | ALT1)
97+
#define PB8_ALT2 (PB8 | ALT2)
98+
#define PB9_ALT1 (PB9 | ALT1)
99+
#define PB9_ALT2 (PB9 | ALT2)
100+
#define PB9_ALT3 (PB9 | ALT3)
101+
#define PB11_ALT1 (PB11 | ALT1)
102+
#define PB12_ALT1 (PB12 | ALT1)
103+
#define PB13_ALT1 (PB13 | ALT1)
104+
#define PB14_ALT1 (PB14 | ALT1)
105+
#define PB15_ALT1 (PB15 | ALT1)
106+
#define PB15_ALT2 (PB15 | ALT2)
107+
#define PC6_ALT1 (PC6 | ALT1)
108+
#define PC10_ALT1 (PC10 | ALT1)
109+
#define PC11_ALT1 (PC11 | ALT1)
110+
#define PC13_ALT1 (PC13 | ALT1)
111+
112+
#define NUM_DIGITAL_PINS 42
113+
#define NUM_ANALOG_INPUTS 21
114+
115+
// On-board LED pin number
116+
#ifndef LED_BUILTIN
117+
#define LED_BUILTIN PC6
118+
#endif
119+
120+
// On-board user button
121+
#ifndef USER_BTN
122+
#define USER_BTN PC13
123+
#endif
124+
125+
// SPI definitions
126+
#ifndef PIN_SPI_SS
127+
#define PIN_SPI_SS PA4
128+
#endif
129+
#ifndef PIN_SPI_SS1
130+
#define PIN_SPI_SS1 PA15
131+
#endif
132+
#ifndef PIN_SPI_SS2
133+
#define PIN_SPI_SS2 PNUM_NOT_DEFINED
134+
#endif
135+
#ifndef PIN_SPI_SS3
136+
#define PIN_SPI_SS3 PNUM_NOT_DEFINED
137+
#endif
138+
#ifndef PIN_SPI_MOSI
139+
#define PIN_SPI_MOSI PA7
140+
#endif
141+
#ifndef PIN_SPI_MISO
142+
#define PIN_SPI_MISO PA6
143+
#endif
144+
#ifndef PIN_SPI_SCK
145+
#define PIN_SPI_SCK PA5
146+
#endif
147+
148+
// I2C definitions
149+
#ifndef PIN_WIRE_SDA
150+
#define PIN_WIRE_SDA PA8
151+
#endif
152+
#ifndef PIN_WIRE_SCL
153+
#define PIN_WIRE_SCL PA9
154+
#endif
155+
156+
// Timer Definitions
157+
// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
158+
#ifndef TIMER_TONE
159+
#define TIMER_TONE TIM6
160+
#endif
161+
#ifndef TIMER_SERVO
162+
#define TIMER_SERVO TIM7
163+
#endif
164+
165+
// UART Definitions
166+
#ifndef SERIAL_UART_INSTANCE
167+
#define SERIAL_UART_INSTANCE 2
168+
#endif
169+
170+
// Default pin used for generic 'Serial' instance
171+
// Mandatory for Firmata
172+
#ifndef PIN_SERIAL_RX
173+
#define PIN_SERIAL_RX PA3
174+
#endif
175+
#ifndef PIN_SERIAL_TX
176+
#define PIN_SERIAL_TX PA2
177+
#endif
178+
179+
// Extra HAL modules
180+
#if !defined(HAL_DAC_MODULE_DISABLED)
181+
#define HAL_DAC_MODULE_ENABLED
182+
#endif
183+
#if !defined(HAL_QSPI_MODULE_DISABLED)
184+
#define HAL_QSPI_MODULE_ENABLED
185+
#endif
186+
187+
/*----------------------------------------------------------------------------
188+
* Arduino objects - C++ only
189+
*----------------------------------------------------------------------------*/
190+
191+
#ifdef __cplusplus
192+
// These serial port names are intended to allow libraries and architecture-neutral
193+
// sketches to automatically default to the correct port name for a particular type
194+
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
195+
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
196+
//
197+
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
198+
//
199+
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
200+
//
201+
// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
202+
//
203+
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
204+
//
205+
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
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// pins are NOT connected to anything by default.
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#ifndef SERIAL_PORT_MONITOR
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#define SERIAL_PORT_MONITOR Serial2
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#endif
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#ifndef SERIAL_PORT_HARDWARE
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#define SERIAL_PORT_HARDWARE Serial2
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#endif
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#endif

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