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fpistmfpistm
authoredSep 23, 2024··
Merge pull request #2522 from fpistm/weact_H562RGT
variant(h5): add WeAct H562RGT support
2 parents c888cf9 + dbde66e commit 40d50d3

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lines changed

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‎CI/build/conf/cores_config.json

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -546,6 +546,7 @@
546546
"GENERIC_G4A1REIX",
547547
"GENERIC_G4A1RETX",
548548
"GENERIC_H503CBTX",
549+
"GENERIC_H562RGTX",
549550
"GENERIC_H563IIKXQ",
550551
"GENERIC_H563RGTX",
551552
"GENERIC_H563RITX",
@@ -813,6 +814,13 @@
813814
"GENERIC_MP157AACX",
814815
"GENERIC_MP157CACX",
815816
"GENERIC_MP157DACX",
817+
"GENERIC_U073R8IX",
818+
"GENERIC_U073R8TX",
819+
"GENERIC_U073RBIX",
820+
"GENERIC_U073RBTX",
821+
"GENERIC_U073RCIX",
822+
"GENERIC_U073RCTX",
823+
"GENERIC_U083RCIX",
816824
"GENERIC_U575AGIXQ",
817825
"GENERIC_U575AIIXQ",
818826
"GENERIC_U575CGTX",

‎CI/build/conf/cores_config_ci.json

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -546,6 +546,7 @@
546546
"GENERIC_G4A1REIX",
547547
"GENERIC_G4A1RETX",
548548
"GENERIC_H503CBTX",
549+
"GENERIC_H562RGTX",
549550
"GENERIC_H563IIKXQ",
550551
"GENERIC_H563RGTX",
551552
"GENERIC_H563RITX",
@@ -813,6 +814,13 @@
813814
"GENERIC_MP157AACX",
814815
"GENERIC_MP157CACX",
815816
"GENERIC_MP157DACX",
817+
"GENERIC_U073R8IX",
818+
"GENERIC_U073R8TX",
819+
"GENERIC_U073RBIX",
820+
"GENERIC_U073RBTX",
821+
"GENERIC_U073RCIX",
822+
"GENERIC_U073RCTX",
823+
"GENERIC_U083RCIX",
816824
"GENERIC_U575AGIXQ",
817825
"GENERIC_U575AIIXQ",
818826
"GENERIC_U575CGTX",

‎README.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -548,6 +548,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
548548
| :yellow_heart: | STM32H503CB | Generic Board | **2.9.0** | |
549549
| :green_heart: | STM32H503KB | Generic Board | *2.8.1* | |
550550
| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | |
551+
| :yellow_heart: | STM32H562RGT | WeAct H562RGT | **2.9.0** | |
552+
| :yellow_heart: | STM32H562RGT<br>STM32H562RIT | Generic Board | **2.9.0** | |
551553
| :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | |
552554
| :green_heart: | STM32H563RG<br>STM32H563RI | Generic Board | *2.8.1* | |
553555
| :green_heart: | STM32H563ZG<br>STM32H563ZI | Generic Board | *2.6.0* | |

‎boards.txt

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8442,6 +8442,17 @@ GenH5.upload.maximum_data_size=0
84428442
GenH5.vid.0=0x0483
84438443
GenH5.pid.0=0x5740
84448444

8445+
# WeAct H562RGT
8446+
GenH5.menu.pnum.WEACT_H562RG=WeAct H562RGT
8447+
GenH5.menu.pnum.WEACT_H562RG.upload.maximum_size=1048576
8448+
GenH5.menu.pnum.WEACT_H562RG.upload.maximum_data_size=655360
8449+
GenH5.menu.pnum.WEACT_H562RG.build.board=WEACT_H562RG
8450+
GenH5.menu.pnum.WEACT_H562RG.build.product_line=STM32H562xx
8451+
GenH5.menu.pnum.WEACT_H562RG.build.variant=STM32H5xx/H562R(G-I)T
8452+
GenH5.menu.pnum.WEACT_H562RG.build.variant_h=variant_WEACT_H562RG.h
8453+
GenH5.menu.pnum.WEACT_H562RG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
8454+
GenH5.menu.pnum.WEACT_H562RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
8455+
84458456
# Generic H503CBTx
84468457
GenH5.menu.pnum.GENERIC_H503CBTX=Generic H503CBTx
84478458
GenH5.menu.pnum.GENERIC_H503CBTX.upload.maximum_size=131072
@@ -8478,6 +8489,24 @@ GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
84788489
GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
84798490
GenH5.menu.pnum.GENERIC_H503RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd
84808491

8492+
# Generic H562RGTx
8493+
GenH5.menu.pnum.GENERIC_H562RGTX=Generic H562RGTx
8494+
GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_size=1048576
8495+
GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_data_size=655360
8496+
GenH5.menu.pnum.GENERIC_H562RGTX.build.board=GENERIC_H562RGTX
8497+
GenH5.menu.pnum.GENERIC_H562RGTX.build.product_line=STM32H562xx
8498+
GenH5.menu.pnum.GENERIC_H562RGTX.build.variant=STM32H5xx/H562R(G-I)T
8499+
GenH5.menu.pnum.GENERIC_H562RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
8500+
8501+
# Generic H562RITx
8502+
GenH5.menu.pnum.GENERIC_H562RITX=Generic H562RITx
8503+
GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_size=2097152
8504+
GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_data_size=655360
8505+
GenH5.menu.pnum.GENERIC_H562RITX.build.board=GENERIC_H562RITX
8506+
GenH5.menu.pnum.GENERIC_H562RITX.build.product_line=STM32H562xx
8507+
GenH5.menu.pnum.GENERIC_H562RITX.build.variant=STM32H5xx/H562R(G-I)T
8508+
GenH5.menu.pnum.GENERIC_H562RITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
8509+
84818510
# Generic H563IIKxQ
84828511
GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ
84838512
GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152

‎cmake/boards_db.cmake

Lines changed: 246 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73502,6 +73502,170 @@ target_compile_options(GENERIC_H503RBTX_xusb_HSFS INTERFACE
7350273502
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
7350373503
)
7350473504

73505+
# GENERIC_H562RGTX
73506+
# -----------------------------------------------------------------------------
73507+
73508+
set(GENERIC_H562RGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H562R(G-I)T")
73509+
set(GENERIC_H562RGTX_MAXSIZE 1048576)
73510+
set(GENERIC_H562RGTX_MAXDATASIZE 655360)
73511+
set(GENERIC_H562RGTX_MCU cortex-m33)
73512+
set(GENERIC_H562RGTX_FPCONF "-")
73513+
add_library(GENERIC_H562RGTX INTERFACE)
73514+
target_compile_options(GENERIC_H562RGTX INTERFACE
73515+
"SHELL:-DSTM32H562xx "
73516+
"SHELL:"
73517+
"SHELL:"
73518+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73519+
-mcpu=${GENERIC_H562RGTX_MCU}
73520+
)
73521+
target_compile_definitions(GENERIC_H562RGTX INTERFACE
73522+
"STM32H5xx"
73523+
"ARDUINO_GENERIC_H562RGTX"
73524+
"BOARD_NAME=\"GENERIC_H562RGTX\""
73525+
"BOARD_ID=GENERIC_H562RGTX"
73526+
"VARIANT_H=\"variant_generic.h\""
73527+
)
73528+
target_include_directories(GENERIC_H562RGTX INTERFACE
73529+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
73530+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
73531+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
73532+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
73533+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
73534+
${GENERIC_H562RGTX_VARIANT_PATH}
73535+
)
73536+
73537+
target_link_options(GENERIC_H562RGTX INTERFACE
73538+
"LINKER:--default-script=${GENERIC_H562RGTX_VARIANT_PATH}/ldscript.ld"
73539+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
73540+
"LINKER:--defsym=LD_MAX_SIZE=1048576"
73541+
"LINKER:--defsym=LD_MAX_DATA_SIZE=655360"
73542+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73543+
-mcpu=${GENERIC_H562RGTX_MCU}
73544+
)
73545+
73546+
add_library(GENERIC_H562RGTX_serial_disabled INTERFACE)
73547+
target_compile_options(GENERIC_H562RGTX_serial_disabled INTERFACE
73548+
"SHELL:"
73549+
)
73550+
add_library(GENERIC_H562RGTX_serial_generic INTERFACE)
73551+
target_compile_options(GENERIC_H562RGTX_serial_generic INTERFACE
73552+
"SHELL:-DHAL_UART_MODULE_ENABLED"
73553+
)
73554+
add_library(GENERIC_H562RGTX_serial_none INTERFACE)
73555+
target_compile_options(GENERIC_H562RGTX_serial_none INTERFACE
73556+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
73557+
)
73558+
add_library(GENERIC_H562RGTX_usb_CDC INTERFACE)
73559+
target_compile_options(GENERIC_H562RGTX_usb_CDC INTERFACE
73560+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
73561+
)
73562+
add_library(GENERIC_H562RGTX_usb_CDCgen INTERFACE)
73563+
target_compile_options(GENERIC_H562RGTX_usb_CDCgen INTERFACE
73564+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
73565+
)
73566+
add_library(GENERIC_H562RGTX_usb_HID INTERFACE)
73567+
target_compile_options(GENERIC_H562RGTX_usb_HID INTERFACE
73568+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
73569+
)
73570+
add_library(GENERIC_H562RGTX_usb_none INTERFACE)
73571+
target_compile_options(GENERIC_H562RGTX_usb_none INTERFACE
73572+
"SHELL:"
73573+
)
73574+
add_library(GENERIC_H562RGTX_xusb_FS INTERFACE)
73575+
target_compile_options(GENERIC_H562RGTX_xusb_FS INTERFACE
73576+
"SHELL:"
73577+
)
73578+
add_library(GENERIC_H562RGTX_xusb_HS INTERFACE)
73579+
target_compile_options(GENERIC_H562RGTX_xusb_HS INTERFACE
73580+
"SHELL:-DUSE_USB_HS"
73581+
)
73582+
add_library(GENERIC_H562RGTX_xusb_HSFS INTERFACE)
73583+
target_compile_options(GENERIC_H562RGTX_xusb_HSFS INTERFACE
73584+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
73585+
)
73586+
73587+
# GENERIC_H562RITX
73588+
# -----------------------------------------------------------------------------
73589+
73590+
set(GENERIC_H562RITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H562R(G-I)T")
73591+
set(GENERIC_H562RITX_MAXSIZE 2097152)
73592+
set(GENERIC_H562RITX_MAXDATASIZE 655360)
73593+
set(GENERIC_H562RITX_MCU cortex-m33)
73594+
set(GENERIC_H562RITX_FPCONF "-")
73595+
add_library(GENERIC_H562RITX INTERFACE)
73596+
target_compile_options(GENERIC_H562RITX INTERFACE
73597+
"SHELL:-DSTM32H562xx "
73598+
"SHELL:"
73599+
"SHELL:"
73600+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73601+
-mcpu=${GENERIC_H562RITX_MCU}
73602+
)
73603+
target_compile_definitions(GENERIC_H562RITX INTERFACE
73604+
"STM32H5xx"
73605+
"ARDUINO_GENERIC_H562RITX"
73606+
"BOARD_NAME=\"GENERIC_H562RITX\""
73607+
"BOARD_ID=GENERIC_H562RITX"
73608+
"VARIANT_H=\"variant_generic.h\""
73609+
)
73610+
target_include_directories(GENERIC_H562RITX INTERFACE
73611+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
73612+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
73613+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
73614+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
73615+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
73616+
${GENERIC_H562RITX_VARIANT_PATH}
73617+
)
73618+
73619+
target_link_options(GENERIC_H562RITX INTERFACE
73620+
"LINKER:--default-script=${GENERIC_H562RITX_VARIANT_PATH}/ldscript.ld"
73621+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
73622+
"LINKER:--defsym=LD_MAX_SIZE=2097152"
73623+
"LINKER:--defsym=LD_MAX_DATA_SIZE=655360"
73624+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73625+
-mcpu=${GENERIC_H562RITX_MCU}
73626+
)
73627+
73628+
add_library(GENERIC_H562RITX_serial_disabled INTERFACE)
73629+
target_compile_options(GENERIC_H562RITX_serial_disabled INTERFACE
73630+
"SHELL:"
73631+
)
73632+
add_library(GENERIC_H562RITX_serial_generic INTERFACE)
73633+
target_compile_options(GENERIC_H562RITX_serial_generic INTERFACE
73634+
"SHELL:-DHAL_UART_MODULE_ENABLED"
73635+
)
73636+
add_library(GENERIC_H562RITX_serial_none INTERFACE)
73637+
target_compile_options(GENERIC_H562RITX_serial_none INTERFACE
73638+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
73639+
)
73640+
add_library(GENERIC_H562RITX_usb_CDC INTERFACE)
73641+
target_compile_options(GENERIC_H562RITX_usb_CDC INTERFACE
73642+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
73643+
)
73644+
add_library(GENERIC_H562RITX_usb_CDCgen INTERFACE)
73645+
target_compile_options(GENERIC_H562RITX_usb_CDCgen INTERFACE
73646+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
73647+
)
73648+
add_library(GENERIC_H562RITX_usb_HID INTERFACE)
73649+
target_compile_options(GENERIC_H562RITX_usb_HID INTERFACE
73650+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
73651+
)
73652+
add_library(GENERIC_H562RITX_usb_none INTERFACE)
73653+
target_compile_options(GENERIC_H562RITX_usb_none INTERFACE
73654+
"SHELL:"
73655+
)
73656+
add_library(GENERIC_H562RITX_xusb_FS INTERFACE)
73657+
target_compile_options(GENERIC_H562RITX_xusb_FS INTERFACE
73658+
"SHELL:"
73659+
)
73660+
add_library(GENERIC_H562RITX_xusb_HS INTERFACE)
73661+
target_compile_options(GENERIC_H562RITX_xusb_HS INTERFACE
73662+
"SHELL:-DUSE_USB_HS"
73663+
)
73664+
add_library(GENERIC_H562RITX_xusb_HSFS INTERFACE)
73665+
target_compile_options(GENERIC_H562RITX_xusb_HSFS INTERFACE
73666+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
73667+
)
73668+
7350573669
# GENERIC_H563IIKXQ
7350673670
# -----------------------------------------------------------------------------
7350773671

@@ -109800,6 +109964,88 @@ target_link_options(VCCGND_F407ZG_MINI_hid INTERFACE
109800109964
)
109801109965

109802109966

109967+
# WEACT_H562RG
109968+
# -----------------------------------------------------------------------------
109969+
109970+
set(WEACT_H562RG_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H562R(G-I)T")
109971+
set(WEACT_H562RG_MAXSIZE 1048576)
109972+
set(WEACT_H562RG_MAXDATASIZE 655360)
109973+
set(WEACT_H562RG_MCU cortex-m33)
109974+
set(WEACT_H562RG_FPCONF "-")
109975+
add_library(WEACT_H562RG INTERFACE)
109976+
target_compile_options(WEACT_H562RG INTERFACE
109977+
"SHELL:-DSTM32H562xx "
109978+
"SHELL:-DCUSTOM_PERIPHERAL_PINS"
109979+
"SHELL:"
109980+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
109981+
-mcpu=${WEACT_H562RG_MCU}
109982+
)
109983+
target_compile_definitions(WEACT_H562RG INTERFACE
109984+
"STM32H5xx"
109985+
"ARDUINO_WEACT_H562RG"
109986+
"BOARD_NAME=\"WEACT_H562RG\""
109987+
"BOARD_ID=WEACT_H562RG"
109988+
"VARIANT_H=\"variant_WEACT_H562RG.h\""
109989+
)
109990+
target_include_directories(WEACT_H562RG INTERFACE
109991+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
109992+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
109993+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
109994+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
109995+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
109996+
${WEACT_H562RG_VARIANT_PATH}
109997+
)
109998+
109999+
target_link_options(WEACT_H562RG INTERFACE
110000+
"LINKER:--default-script=${WEACT_H562RG_VARIANT_PATH}/ldscript.ld"
110001+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
110002+
"LINKER:--defsym=LD_MAX_SIZE=1048576"
110003+
"LINKER:--defsym=LD_MAX_DATA_SIZE=655360"
110004+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
110005+
-mcpu=${WEACT_H562RG_MCU}
110006+
)
110007+
110008+
add_library(WEACT_H562RG_serial_disabled INTERFACE)
110009+
target_compile_options(WEACT_H562RG_serial_disabled INTERFACE
110010+
"SHELL:"
110011+
)
110012+
add_library(WEACT_H562RG_serial_generic INTERFACE)
110013+
target_compile_options(WEACT_H562RG_serial_generic INTERFACE
110014+
"SHELL:-DHAL_UART_MODULE_ENABLED"
110015+
)
110016+
add_library(WEACT_H562RG_serial_none INTERFACE)
110017+
target_compile_options(WEACT_H562RG_serial_none INTERFACE
110018+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
110019+
)
110020+
add_library(WEACT_H562RG_usb_CDC INTERFACE)
110021+
target_compile_options(WEACT_H562RG_usb_CDC INTERFACE
110022+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
110023+
)
110024+
add_library(WEACT_H562RG_usb_CDCgen INTERFACE)
110025+
target_compile_options(WEACT_H562RG_usb_CDCgen INTERFACE
110026+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
110027+
)
110028+
add_library(WEACT_H562RG_usb_HID INTERFACE)
110029+
target_compile_options(WEACT_H562RG_usb_HID INTERFACE
110030+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
110031+
)
110032+
add_library(WEACT_H562RG_usb_none INTERFACE)
110033+
target_compile_options(WEACT_H562RG_usb_none INTERFACE
110034+
"SHELL:"
110035+
)
110036+
add_library(WEACT_H562RG_xusb_FS INTERFACE)
110037+
target_compile_options(WEACT_H562RG_xusb_FS INTERFACE
110038+
"SHELL:"
110039+
)
110040+
add_library(WEACT_H562RG_xusb_HS INTERFACE)
110041+
target_compile_options(WEACT_H562RG_xusb_HS INTERFACE
110042+
"SHELL:-DUSE_USB_HS"
110043+
)
110044+
add_library(WEACT_H562RG_xusb_HSFS INTERFACE)
110045+
target_compile_options(WEACT_H562RG_xusb_HSFS INTERFACE
110046+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
110047+
)
110048+
109803110049
# WeActMiniH743VITX
109804110050
# -----------------------------------------------------------------------------
109805110051

‎variants/STM32H5xx/H562R(G-I)T/CMakeLists.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage)
2121
add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2222
generic_clock.c
2323
PeripheralPins.c
24+
PeripheralPins_WEACT_H562RG.c
2425
variant_generic.cpp
26+
variant_WEACT_H562RG.cpp
2527
)
2628
target_link_libraries(variant_bin PUBLIC variant_usage)
2729

‎variants/STM32H5xx/H562R(G-I)T/PeripheralPins_WEACT_H562RG.c

Lines changed: 543 additions & 0 deletions
Large diffs are not rendered by default.

‎variants/STM32H5xx/H562R(G-I)T/generic_clock.c

Lines changed: 83 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,89 @@
2020
*/
2121
WEAK void SystemClock_Config(void)
2222
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
23+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
24+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
25+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
26+
27+
/** Configure the main internal regulator output voltage
28+
*/
29+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
30+
31+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
32+
33+
/** Initializes the RCC Oscillators according to the specified parameters
34+
* in the RCC_OscInitTypeDef structure.
35+
*/
36+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI;
37+
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
38+
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
39+
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
40+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
41+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
42+
RCC_OscInitStruct.PLL.PLLM = 1;
43+
RCC_OscInitStruct.PLL.PLLN = 120;
44+
RCC_OscInitStruct.PLL.PLLP = 2;
45+
RCC_OscInitStruct.PLL.PLLQ = 10;
46+
RCC_OscInitStruct.PLL.PLLR = 2;
47+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
48+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
49+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
50+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
51+
Error_Handler();
52+
}
53+
54+
/** Initializes the CPU, AHB and APB buses clocks
55+
*/
56+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
57+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
58+
| RCC_CLOCKTYPE_PCLK3;
59+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
60+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
61+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
62+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
63+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
64+
65+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
66+
Error_Handler();
67+
}
68+
69+
/** Initializes the peripherals clock
70+
*/
71+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC
72+
| RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SDMMC1
73+
| RCC_PERIPHCLK_USB;
74+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
75+
PeriphClkInitStruct.PLL2.PLL2M = 1;
76+
PeriphClkInitStruct.PLL2.PLL2N = 125;
77+
PeriphClkInitStruct.PLL2.PLL2P = 2;
78+
PeriphClkInitStruct.PLL2.PLL2Q = 2;
79+
PeriphClkInitStruct.PLL2.PLL2R = 5;
80+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
81+
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
82+
PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
83+
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVR;
84+
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
85+
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI;
86+
PeriphClkInitStruct.PLL3.PLL3M = 1;
87+
PeriphClkInitStruct.PLL3.PLL3N = 40;
88+
PeriphClkInitStruct.PLL3.PLL3P = 2;
89+
PeriphClkInitStruct.PLL3.PLL3Q = 5;
90+
PeriphClkInitStruct.PLL3.PLL3R = 2;
91+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0;
92+
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM;
93+
PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
94+
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
95+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3Q;
96+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
97+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL1Q;
98+
99+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
100+
Error_Handler();
101+
}
102+
103+
/** Configure the programming delay
104+
*/
105+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
25106
}
26107

27108
#endif /* ARDUINO_GENERIC_* */

‎variants/STM32H5xx/H562R(G-I)T/ldscript.ld

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,187 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32H562RGTx Device from STM32H5 series
9+
** 1024KBytes FLASH
10+
** 640KBytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2024 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
42+
_Min_Stack_Size = 0x400; /* required amount of stack */
43+
44+
/* Memories definition */
45+
MEMORY
46+
{
47+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
48+
FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
51+
/* Sections */
52+
SECTIONS
53+
{
54+
/* The startup code into "FLASH" Rom type memory */
55+
.isr_vector :
56+
{
57+
. = ALIGN(4);
58+
KEEP(*(.isr_vector)) /* Startup code */
59+
. = ALIGN(4);
60+
} >FLASH
61+
62+
/* The program code and other data into "FLASH" Rom type memory */
63+
.text :
64+
{
65+
. = ALIGN(4);
66+
*(.text) /* .text sections (code) */
67+
*(.text*) /* .text* sections (code) */
68+
*(.glue_7) /* glue arm to thumb code */
69+
*(.glue_7t) /* glue thumb to arm code */
70+
*(.eh_frame)
71+
72+
KEEP (*(.init))
73+
KEEP (*(.fini))
74+
75+
. = ALIGN(4);
76+
_etext = .; /* define a global symbols at end of code */
77+
} >FLASH
78+
79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
84+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
85+
. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
89+
{
90+
. = ALIGN(4);
91+
*(.ARM.extab* .gnu.linkonce.armextab.*)
92+
. = ALIGN(4);
93+
} >FLASH
94+
95+
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
96+
{
97+
. = ALIGN(4);
98+
__exidx_start = .;
99+
*(.ARM.exidx*)
100+
__exidx_end = .;
101+
. = ALIGN(4);
102+
} >FLASH
103+
104+
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
105+
{
106+
. = ALIGN(4);
107+
PROVIDE_HIDDEN (__preinit_array_start = .);
108+
KEEP (*(.preinit_array*))
109+
PROVIDE_HIDDEN (__preinit_array_end = .);
110+
. = ALIGN(4);
111+
} >FLASH
112+
113+
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
114+
{
115+
. = ALIGN(4);
116+
PROVIDE_HIDDEN (__init_array_start = .);
117+
KEEP (*(SORT(.init_array.*)))
118+
KEEP (*(.init_array*))
119+
PROVIDE_HIDDEN (__init_array_end = .);
120+
. = ALIGN(4);
121+
} >FLASH
122+
123+
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
124+
{
125+
. = ALIGN(4);
126+
PROVIDE_HIDDEN (__fini_array_start = .);
127+
KEEP (*(SORT(.fini_array.*)))
128+
KEEP (*(.fini_array*))
129+
PROVIDE_HIDDEN (__fini_array_end = .);
130+
. = ALIGN(4);
131+
} >FLASH
132+
133+
/* Used by the startup to initialize data */
134+
_sidata = LOADADDR(.data);
135+
136+
/* Initialized data sections into "RAM" Ram type memory */
137+
.data :
138+
{
139+
. = ALIGN(4);
140+
_sdata = .; /* create a global symbol at data start */
141+
*(.data) /* .data sections */
142+
*(.data*) /* .data* sections */
143+
*(.RamFunc) /* .RamFunc sections */
144+
*(.RamFunc*) /* .RamFunc* sections */
145+
146+
. = ALIGN(4);
147+
_edata = .; /* define a global symbol at data end */
148+
149+
} >RAM AT> FLASH
150+
151+
/* Uninitialized data section into "RAM" Ram type memory */
152+
. = ALIGN(4);
153+
.bss :
154+
{
155+
/* This is used by the startup in order to initialize the .bss section */
156+
_sbss = .; /* define a global symbol at bss start */
157+
__bss_start__ = _sbss;
158+
*(.bss)
159+
*(.bss*)
160+
*(COMMON)
161+
162+
. = ALIGN(4);
163+
_ebss = .; /* define a global symbol at bss end */
164+
__bss_end__ = _ebss;
165+
} >RAM
166+
167+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
168+
._user_heap_stack :
169+
{
170+
. = ALIGN(8);
171+
PROVIDE ( end = . );
172+
PROVIDE ( _end = . );
173+
. = . + _Min_Heap_Size;
174+
. = . + _Min_Stack_Size;
175+
. = ALIGN(8);
176+
} >RAM
177+
178+
/* Remove information from the compiler libraries */
179+
/DISCARD/ :
180+
{
181+
libc.a ( * )
182+
libm.a ( * )
183+
libgcc.a ( * )
184+
}
185+
186+
.ARM.attributes 0 : { *(.ARM.attributes) }
187+
}

‎variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp

Lines changed: 186 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,186 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2024, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#if defined(ARDUINO_WEACT_H562RG)
14+
#include "pins_arduino.h"
15+
#include "Arduino.h"
16+
// Digital PinName array
17+
const PinName digitalPin[] = {
18+
PC_14, // D0
19+
PC_0, // D1/A0
20+
PC_2, // D2/A1
21+
PA_0, // D3/A2
22+
PA_2, // D4/A3
23+
PA_4, // D5/A4
24+
PA_6, // D6/A5
25+
PC_4, // D7/A6
26+
PB_0, // D8/A7
27+
PB_2, // D9
28+
PC_13, // D10
29+
PC_15, // D11
30+
PC_1, // D12/A8
31+
PC_3, // D13/A9
32+
PA_1, // D14/A10
33+
PA_3, // D15/A11
34+
PA_5, // D16/A12
35+
PA_7, // D17/A13
36+
PC_5, // D18/A14
37+
PB_1, // D19/A15
38+
PB_10, // D20
39+
PB_7, // D21
40+
PB_5, // D22
41+
PB_3, // D23
42+
PC_12, // D24
43+
PC_10, // D25
44+
PA_12, // D26
45+
PA_10, // D27
46+
PA_8, // D28
47+
PC_8, // D29
48+
PC_6, // D30
49+
PB_14, // D31
50+
PB_12, // D32
51+
PB_8, // D33
52+
PB_6, // D34
53+
PB_4, // D35
54+
PD_2, // D36
55+
PC_11, // D37
56+
PA_15, // D38
57+
PA_11, // D39
58+
PA_9, // D40
59+
PC_9, // D41
60+
PC_7, // D42
61+
PB_15, // D43
62+
PB_13, // D44
63+
PA_13, // D45
64+
PA_14, // D46
65+
PH_0, // D47
66+
PH_1 // D48
67+
};
68+
69+
// Analog (Ax) pin number array
70+
const uint32_t analogInputPin[] = {
71+
1, // A0, PC0
72+
2, // A1, PC2
73+
3, // A2, PA0
74+
4, // A3, PA2
75+
5, // A4, PA4
76+
6, // A5, PA6
77+
7, // A6, PC4
78+
8, // A7, PB0
79+
12, // A8, PC1
80+
13, // A9, PC3
81+
14, // A10, PA1
82+
15, // A11, PA3
83+
16, // A12, PA5
84+
17, // A13, PA7
85+
18, // A14, PC5
86+
19 // A15, PB1
87+
};
88+
89+
// ----------------------------------------------------------------------------
90+
91+
#ifdef __cplusplus
92+
extern "C" {
93+
#endif
94+
95+
/**
96+
* @brief System Clock Configuration
97+
* @param None
98+
* @retval None
99+
*/
100+
WEAK void SystemClock_Config(void)
101+
{
102+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
103+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
104+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
105+
106+
/** Configure the main internal regulator output voltage
107+
*/
108+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
109+
110+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
111+
112+
/** Initializes the RCC Oscillators according to the specified parameters
113+
* in the RCC_OscInitTypeDef structure.
114+
*/
115+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSE ;
116+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
117+
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
118+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
119+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
120+
RCC_OscInitStruct.PLL.PLLM = 1;
121+
RCC_OscInitStruct.PLL.PLLN = 62;
122+
RCC_OscInitStruct.PLL.PLLP = 2;
123+
RCC_OscInitStruct.PLL.PLLQ = 2;
124+
RCC_OscInitStruct.PLL.PLLR = 2;
125+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3;
126+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
127+
RCC_OscInitStruct.PLL.PLLFRACN = 4096;
128+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
129+
Error_Handler();
130+
}
131+
132+
/** Initializes the CPU, AHB and APB buses clocks
133+
*/
134+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
135+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
136+
| RCC_CLOCKTYPE_PCLK3;
137+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
138+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
139+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
140+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
141+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
142+
143+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
144+
Error_Handler();
145+
}
146+
147+
/** Configure the programming delay
148+
*/
149+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
150+
/** Initializes the peripherals clock
151+
*/
152+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC
153+
| RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB;
154+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
155+
PeriphClkInitStruct.PLL2.PLL2M = 1;
156+
PeriphClkInitStruct.PLL2.PLL2N = 32;
157+
PeriphClkInitStruct.PLL2.PLL2P = 2;
158+
PeriphClkInitStruct.PLL2.PLL2Q = 8;
159+
PeriphClkInitStruct.PLL2.PLL2R = 4;
160+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
161+
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
162+
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
163+
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR;
164+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
165+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
166+
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
167+
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE;
168+
PeriphClkInitStruct.PLL3.PLL3M = 1;
169+
PeriphClkInitStruct.PLL3.PLL3N = 48;
170+
PeriphClkInitStruct.PLL3.PLL3P = 2;
171+
PeriphClkInitStruct.PLL3.PLL3Q = 8;
172+
PeriphClkInitStruct.PLL3.PLL3R = 2;
173+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0;
174+
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM;
175+
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
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PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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Error_Handler();
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}
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}
182+
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_WEACT_H562RG */

‎variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.h

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/*
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*******************************************************************************
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* Copyright (c) 2024, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#pragma once
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/*----------------------------------------------------------------------------
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* STM32 pins number
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*----------------------------------------------------------------------------*/
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/*
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Board orientation
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P1 P2
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.. OOO ..
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.. ..
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.. ..
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.. ..
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.. ..
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.. ..
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.. ..
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.. ..
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.. ..
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.. SWD _____ ..
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.. |||| | USB | ..
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.. |_____| ..
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*/
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// Connector P1
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// Left side
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#define PC14 0 // OSC32_IN
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#define PC0 PIN_A0
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#define PC2 PIN_A1
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#define PA0 PIN_A2
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#define PA2 PIN_A3
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#define PA4 PIN_A4 // SPI CS
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#define PA6 PIN_A5 // SPI MISO
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#define PC4 PIN_A6
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#define PB0 PIN_A7
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#define PB2 9 // LED_BUILTIN
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// PB11/VCAP
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// Right side
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#define PC13 10 // USER_BTN
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#define PC15 11 // OSC32_OUT
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#define PC1 PIN_A8
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#define PC3 PIN_A9
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#define PA1 PIN_A10
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#define PA3 PIN_A11
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#define PA5 PIN_A12 // SPI SCK
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#define PA7 PIN_A13 // SPI MOSI
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#define PC5 PIN_A14
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#define PB1 PIN_A15
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#define PB10 20
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// Connector P2
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// Left side
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// PB9/VCAP
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#define PB7 21 // I2C SDA
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#define PB5 22
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#define PB3 23
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#define PC12 24 // SDX_CLK
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#define PC10 25 // SDX_D2
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#define PA12 26 // USB DP
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#define PA10 27 // Rx
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#define PA8 28 // SD_DETECT
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#define PC8 29 // SDX_D0
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#define PC6 30
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#define PB14 31
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#define PB12 32
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// Right side
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#define PB8 33
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#define PB6 34 // I2C SCL
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#define PB4 35
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#define PD2 36 // SDX_CMD
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#define PC11 37 // SDX_D3
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#define PA15 38
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#define PA11 39 // USB DM
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#define PA9 40 // Tx
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#define PC9 41 // SDX_D1
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#define PC7 42
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#define PB15 43
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#define PB13 44
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// Other pins
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#define PA13 45 // SWDIO
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#define PA14 46 // SWCLK
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#define PH0 47 // OSC_IN
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#define PH1 48 // OSC_OUT
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// Alternate pins number
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#define PA0_ALT1 (PA0 | ALT1)
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#define PA1_ALT1 (PA1 | ALT1)
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#define PA1_ALT2 (PA1 | ALT2)
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#define PA2_ALT1 (PA2 | ALT1)
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#define PA2_ALT2 (PA2 | ALT2)
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#define PA3_ALT1 (PA3 | ALT1)
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#define PA3_ALT2 (PA3 | ALT2)
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#define PA4_ALT1 (PA4 | ALT1)
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#define PA4_ALT2 (PA4 | ALT2)
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#define PA5_ALT1 (PA5 | ALT1)
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#define PA6_ALT1 (PA6 | ALT1)
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#define PA7_ALT1 (PA7 | ALT1)
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#define PA7_ALT2 (PA7 | ALT2)
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#define PA7_ALT3 (PA7 | ALT3)
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#define PA9_ALT1 (PA9 | ALT1)
110+
#define PA10_ALT1 (PA10 | ALT1)
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#define PA11_ALT1 (PA11 | ALT1)
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#define PA12_ALT1 (PA12 | ALT1)
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#define PA15_ALT1 (PA15 | ALT1)
114+
#define PA15_ALT2 (PA15 | ALT2)
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#define PB0_ALT1 (PB0 | ALT1)
116+
#define PB0_ALT2 (PB0 | ALT2)
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#define PB1_ALT1 (PB1 | ALT1)
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#define PB1_ALT2 (PB1 | ALT2)
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#define PB3_ALT1 (PB3 | ALT1)
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#define PB3_ALT2 (PB3 | ALT2)
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#define PB4_ALT1 (PB4 | ALT1)
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#define PB4_ALT2 (PB4 | ALT2)
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#define PB5_ALT1 (PB5 | ALT1)
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#define PB5_ALT2 (PB5 | ALT2)
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#define PB6_ALT1 (PB6 | ALT1)
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#define PB6_ALT2 (PB6 | ALT2)
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#define PB7_ALT1 (PB7 | ALT1)
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#define PB8_ALT1 (PB8 | ALT1)
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#define PB14_ALT1 (PB14 | ALT1)
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#define PB14_ALT2 (PB14 | ALT2)
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#define PB15_ALT1 (PB15 | ALT1)
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#define PB15_ALT2 (PB15 | ALT2)
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#define PC0_ALT1 (PC0 | ALT1)
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#define PC1_ALT1 (PC1 | ALT1)
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#define PC2_ALT1 (PC2 | ALT1)
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#define PC3_ALT1 (PC3 | ALT1)
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#define PC4_ALT1 (PC4 | ALT1)
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#define PC5_ALT1 (PC5 | ALT1)
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#define PC6_ALT1 (PC6 | ALT1)
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#define PC7_ALT1 (PC7 | ALT1)
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#define PC8_ALT1 (PC8 | ALT1)
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#define PC9_ALT1 (PC9 | ALT1)
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#define PC10_ALT1 (PC10 | ALT1)
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#define PC11_ALT1 (PC11 | ALT1)
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#define NUM_DIGITAL_PINS 49
147+
#define NUM_ANALOG_INPUTS 16
148+
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// On-board LED pin number
150+
#ifndef LED_BUILTIN
151+
#define LED_BUILTIN PB2
152+
#endif
153+
#define LED_BLUE LED_BUILTIN
154+
155+
// On-board user button
156+
#ifndef USER_BTN
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#define USER_BTN PC13
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#endif
159+
160+
// SPI definitions
161+
#ifndef PIN_SPI_SS
162+
#define PIN_SPI_SS PA4
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#endif
164+
#ifndef PIN_SPI_SS1
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#define PIN_SPI_SS1 PA15
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#endif
167+
#ifndef PIN_SPI_SS2
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#define PIN_SPI_SS2 PNUM_NOT_DEFINED
169+
#endif
170+
#ifndef PIN_SPI_SS3
171+
#define PIN_SPI_SS3 PNUM_NOT_DEFINED
172+
#endif
173+
#ifndef PIN_SPI_MOSI
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#define PIN_SPI_MOSI PA7
175+
#endif
176+
#ifndef PIN_SPI_MISO
177+
#define PIN_SPI_MISO PA6
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#endif
179+
#ifndef PIN_SPI_SCK
180+
#define PIN_SPI_SCK PA5
181+
#endif
182+
183+
// I2C definitions
184+
#ifndef PIN_WIRE_SDA
185+
#define PIN_WIRE_SDA PB7
186+
#endif
187+
#ifndef PIN_WIRE_SCL
188+
#define PIN_WIRE_SCL PB6
189+
#endif
190+
191+
// Timer Definitions
192+
// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
193+
#ifndef TIMER_TONE
194+
#define TIMER_TONE TIM6
195+
#endif
196+
#ifndef TIMER_SERVO
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#define TIMER_SERVO TIM7
198+
#endif
199+
200+
// UART Definitions
201+
#ifndef SERIAL_UART_INSTANCE
202+
#define SERIAL_UART_INSTANCE 101
203+
#endif
204+
205+
// Default pin used for generic 'Serial' instance
206+
// Mandatory for Firmata
207+
#ifndef PIN_SERIAL_RX
208+
#define PIN_SERIAL_RX PA10
209+
#endif
210+
#ifndef PIN_SERIAL_TX
211+
#define PIN_SERIAL_TX PA9
212+
#endif
213+
214+
// Extra HAL modules
215+
#if !defined(HAL_DAC_MODULE_DISABLED)
216+
#define HAL_DAC_MODULE_ENABLED
217+
#endif
218+
#if !defined(HAL_OSPI_MODULE_DISABLED)
219+
#define HAL_OSPI_MODULE_ENABLED
220+
#endif
221+
#if !defined(HAL_SD_MODULE_DISABLED)
222+
#define HAL_SD_MODULE_ENABLED
223+
#endif
224+
225+
#define HSE_VALUE 8000000UL
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// SD card slot Definitions
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// SDMMC signals not available
229+
#define SDMMC_CDIR_NA
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#define SDMMC_CKIN_NA
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#define SDMMC_D0DIR_NA
232+
233+
// SD detect signal can be defined if required
234+
#ifndef SD_DETECT_PIN
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#define SD_DETECT_PIN PA8
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#endif
237+
#ifndef SD_DETECT_LEVEL
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#define SD_DETECT_LEVEL HIGH
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#endif
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#ifndef SDX_D0
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#define SDX_D0 PC8
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#endif
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#ifndef SDX_D1
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#define SDX_D1 PC9
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#endif
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#ifndef SDX_D2
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#define SDX_D2 PC10
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#endif
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#ifndef SDX_D3
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#define SDX_D3 PC11
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#endif
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#ifndef SDX_CMD
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#define SDX_CMD PD2
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#endif
256+
#ifndef SDX_CK
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#define SDX_CK PC12
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#endif
259+
260+
/*----------------------------------------------------------------------------
261+
* Arduino objects - C++ only
262+
*----------------------------------------------------------------------------*/
263+
264+
#ifdef __cplusplus
265+
// These serial port names are intended to allow libraries and architecture-neutral
266+
// sketches to automatically default to the correct port name for a particular type
267+
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
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// the first hardware serial port whose RX/TX pins are not dedicated to another use.
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//
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// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
271+
//
272+
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
273+
//
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// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
275+
//
276+
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
277+
//
278+
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
279+
// pins are NOT connected to anything by default.
280+
#ifndef SERIAL_PORT_MONITOR
281+
#define SERIAL_PORT_MONITOR Serial
282+
#endif
283+
#ifndef SERIAL_PORT_HARDWARE
284+
#define SERIAL_PORT_HARDWARE Serial
285+
#endif
286+
#endif

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