diff --git a/.cargo/config.toml b/.cargo/config.toml index 22153f86..ad81ad5c 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -1,3 +1,21 @@ +[target.thumbv6m-none-eabi] +rustflags = [ + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", +] + +[target.thumbv7m-none-eabi] +rustflags = [ + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", +] + +[target.thumbv7em-none-eabi] +rustflags = [ + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", +] + [target.thumbv7em-none-eabihf] runner = 'probe-rs run --chip STM32F411CEUx' rustflags = [ @@ -10,6 +28,12 @@ rustflags = [ #"-C", "link-arg=--nmagic", ] +[target.thumbv8m.main-none-eabihf] +rustflags = [ + "-C", "link-arg=-Tlink.x", + "-C", "link-arg=-Tdefmt.x", +] + [build] target = "thumbv7em-none-eabihf" diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 08d7222c..b5f3b9d9 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -38,6 +38,15 @@ jobs: - stm32f446 - stm32f469 - stm32f479 + - stm32f722 + - stm32f723 + - stm32f730 + - stm32f745 + - stm32f746 + - stm32f765 + - stm32f767 + - stm32f769 + rust: - stable features: diff --git a/.vscode/settings.json b/.vscode/settings.json index 2268655a..d9fc00f0 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,5 +1,5 @@ { "rust-analyzer.check.allTargets": false, "rust-analyzer.check.targets": "thumbv7em-none-eabihf", - "rust-analyzer.cargo.features": ["defmt", "rtic1", "stm32f411"] + "rust-analyzer.cargo.features": ["defmt", "rtic1", "stm32f746"] } diff --git a/CHANGELOG.md b/CHANGELOG.md index 26359037..df6be85b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added - I2C 10-bit address support for I2c [#772] [#783] + - FMPI2c APB timings [#770] - `i2c_scanner` example [#758] - Enable `sdio` for stm32f446 - port LTDC implementation and example from stm32f7xx-hal [#731] @@ -23,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Use `stm32f4-staging` until `stm32f4` is released [#706] - use GPIO pac fields instead of raw write - RTIC2 monotonics fix: CC1 instead of CC3 + - Fefactor FMPI2c `embedded-hal` implementations - Allow different lengths of buffers in hal_1 SpiBus impl [#566] - Clean SPI write impls - move `ptr()` to `Ptr` trait [#773] @@ -34,6 +36,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). [#725]: https://github.com/stm32-rs/stm32f4xx-hal/pull/725 [#731]: https://github.com/stm32-rs/stm32f4xx-hal/pull/731 [#758]: https://github.com/stm32-rs/stm32f4xx-hal/pull/758 +[#770]: https://github.com/stm32-rs/stm32f4xx-hal/pull/770 [#772]: https://github.com/stm32-rs/stm32f4xx-hal/pull/772 [#773]: https://github.com/stm32-rs/stm32f4xx-hal/pull/773 [#783]: https://github.com/stm32-rs/stm32f4xx-hal/pull/783 diff --git a/Cargo.toml b/Cargo.toml index c3e35821..c1b68697 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -56,6 +56,9 @@ embedded-hal-async = { version = "1.0", optional = true } rtic = { version = "2.0.1", features = ["thumbv7-backend"], optional = true } atomic-polyfill = { version = "1.0.3", optional = true } +stm32-fmc = { version = "0.3.0", optional = true } +fdcan = { version = "0.1.2", features = ["fdcan_g0_g4_l5"], optional = true } + enumflags2 = "0.7.8" embedded-storage = "0.3" vcell = "0.1.3" @@ -63,10 +66,75 @@ document-features = "0.2" micromath = { version = "2.1.0", optional = true } +[dependencies.stm32f0] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32f2] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32f3] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + [dependencies.stm32f4] -package = "stm32f4-staging" -version = "0.16.0" +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32f7] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32g0] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32g4] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32h7] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32l0] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32l1] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32l4] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32l5] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32wb] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true + +[dependencies.stm32wl] +git = "https://github.com/stm32-rs/stm32-rs-nightlies" +features = ["defmt", "atomics"] +optional = true [dependencies.time] version = "0.3.14" @@ -123,6 +191,201 @@ default-features = false features = ["macros"] [features] +c0 = [] +f0 = ["dep:stm32f0"] +f2 = ["dep:stm32f2", "bb", "dma", "i2c_v1", "spi_v1", "uart_v2"] +f3 = ["dep:stm32f3", "bb", "uart_v3"] +f4 = ["dep:stm32f4", "bb", "dma", "i2c_v1", "spi_v1", "uart_v2"] +f7 = [ + "dep:stm32f7", + "dep:micromath", + "dep:stm32-fmc", + "dma", + "i2c_v2", + "spi_v2", + "uart_v3", +] +g0 = ["dep:stm32g0"] +g4 = ["dep:stm32g4", "bb", "dep:fdcan", "uart_v3"] +h7 = ["dep:stm32h7"] +l0 = ["dep:stm32l0"] +l1 = ["dep:stm32l1"] +l4 = ["dep:stm32l4", "uart_v3"] +l4x = ["l4"] +l4p = ["l4"] +l5 = ["dep:stm32l5"] # thumbv8m.main-none-eabihf +u5 = [] +wb = ["dep:stm32wb"] +wl = ["dep:stm32wl"] + +mem-4 = [] +mem-6 = [] +mem-8 = [] +mem-b = [] +mem-c = [] +mem-d = [] +mem-e = [] + +# common features: "i2c1", "rcc", "gpioa", "gpiob", + +# C0 + +gpio-c0xx = [ + "debug", "gpioc", "gpiof", "i2s", "i2s1", "ir", "spi1", "spi2", "tim1", "tim14", "tim15", "tim16", "tim17", "tim3", "usart1", "usart2", +] +gpio-c0xx_453 = [ + "debug", "gpioc", "gpiod", "gpiof", "i2s", "i2s1", "ir", "spi1", "spi2", "tim1", "tim14", "tim15", "tim16", "tim17", "tim3", "usart1", "usart2", +] + +# F0 + +stm32f030x4 = ["svd-f0x0", "gpio-f031"] +stm32f030x6 = ["svd-f0x0", "gpio-f031"] +stm32f030x8 = ["svd-f0x0", "gpio-f051"] +stm32f030xc = ["svd-f0x0", "gpio-f091"] +stm32f031 = ["svd-f0x1", "gpio-f031"] +stm32f038 = ["svd-f0x8", "gpio-f031"] +stm32f042 = ["svd-f0x2", "gpio-f042"] +stm32f048 = ["svd-f0x8", "gpio-f042"] +stm32f051 = ["svd-f0x1", "gpio-f051"] +stm32f058 = ["svd-f0x8", "gpio-f051"] +stm32f070x6 = ["svd-f0x0", "gpio-f042"] +stm32f070xb = ["svd-f0x0", "gpio-f052"] +stm32f071 = ["svd-f0x1", "gpio-f052"] +stm32f072 = ["svd-f0x2", "gpio-f052"] +stm32f078 = ["svd-f0x8", "gpio-f052"] +stm32f091 = ["svd-f0x1", "gpio-f091"] +stm32f098 = ["svd-f0x8", "gpio-f091"] + +svd-f0x0 = ["f0", "stm32f0?/stm32f0x0"] +svd-f0x1 = ["f0", "stm32f0?/stm32f0x1"] +svd-f0x2 = ["f0", "stm32f0?/stm32f0x2"] +svd-f0x8 = ["f0", "stm32f0?/stm32f0x8"] + +gpio-f031 = [ + "hdmi", "i2c2", "i2s1", "ir", "rtc", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tsc", "usart1", "usart2", +] +gpio-f042 = [ + "can", "crs", "gpiof", "i2c2", "i2s1", "ir", "spi1", "spi2", "sys", "tim1", "tim14", "tim16", "tim17", "tim2", "tim3", "tsc", "usart1", "usart2", "usb", +] +gpio-f051 = [ + "comp1", "comp2", "gpioc", "gpiod", "i2c2", "i2s1", "ir", "rtc", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tsc", "usart1", "usart2", +] +gpio-f052 = [ + "can", "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioe", "gpiof", "i2c2", "i2s1", "i2s2", "ir", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tsc", "usart1", "usart2", "usart3", "usart4", "usb", +] +gpio-f091 = [ + "can", "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioe", "gpiof", "i2c2", "i2s1", "i2s2", "ir", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tsc", "usart1", "usart2", "usart3", "usart4", "usart5", "usart6", "usart7", "usart8", "usb", +] +# F2 + +stm32f215 = ["svd-f215"] +stm32f217 = ["svd-f217"] + +svd-f215 = ["f2", "stm32f2?/stm32f215", "gpio-f217"] +svd-f217 = ["f2", "stm32f2?/stm32f217", "gpio-f217"] + + +gpio-f217 = [ + "can1", + "can2", + "dcmi", + "eth", + "fsmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "gpioh", + "gpioi", + "i2c2", + "i2c3", + "i2s", + "i2s2", + "i2s3", + "rtc", + "sdio", + "spi1", + "spi2", + "spi3", + "sys", + "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", + "tim2", + "tim3", + "tim4", + "tim5", + "tim8", + "tim9", + "uart4", + "uart5", + "usart1", + "usart2", + "usart3", + "usart6", + "otg-fs", + "otg-hs", +] + +# F3 + +# Any changes here should be mirrored in README.md, build.rs, src/lib.rs, and +# .github/workflows/ci.yml. +stm32f301x6 = ["svd-f301", "mem-6", "gpio-f302"] +stm32f301x8 = ["svd-f301", "mem-8", "gpio-f302"] +stm32f302x6 = ["svd-f302", "mem-6", "gpio-f302"] +stm32f302x8 = ["svd-f302", "mem-8", "gpio-f302"] +stm32f302xb = ["svd-f302", "mem-b", "gpio-f303"] +stm32f302xc = ["svd-f302", "mem-c", "gpio-f303"] +stm32f302xd = ["svd-f302", "mem-d", "gpio-f303e"] +stm32f302xe = ["svd-f302", "mem-e", "gpio-f303e"] +stm32f303x6 = ["svd-f303", "mem-6", "gpio-f333"] +stm32f303x8 = ["svd-f303", "mem-8", "gpio-f333"] +stm32f303xb = ["svd-f303", "mem-b", "gpio-f303"] +stm32f303xc = ["svd-f303", "mem-c", "gpio-f303"] +stm32f303xd = ["svd-f303", "mem-d", "gpio-f303e"] +stm32f303xe = ["svd-f303", "mem-e", "gpio-f303e"] +stm32f318x8 = ["svd-f301", "mem-8", "gpio-f302"] +stm32f328x8 = ["svd-f303", "mem-8", "gpio-f333"] +stm32f334x4 = ["svd-f3x4", "mem-4", "gpio-f333"] +stm32f334x6 = ["svd-f3x4", "mem-6", "gpio-f333"] +stm32f334x8 = ["svd-f3x4", "mem-8", "gpio-f333"] +stm32f358xc = ["svd-f303", "mem-c", "gpio-f303"] +stm32f373x8 = ["svd-f373", "mem-8", "gpio-f373"] +stm32f373xb = ["svd-f373", "mem-b", "gpio-f373"] +stm32f373xc = ["svd-f373", "mem-c", "gpio-f373"] +stm32f378xc = ["svd-f373", "mem-c", "gpio-f373"] +stm32f398xe = ["svd-f303", "mem-e", "gpio-f303e"] + +svd-f301 = ["f3", "stm32f3?/stm32f301"] +svd-f302 = ["f3", "stm32f3?/stm32f302"] +svd-f303 = ["f3", "stm32f3?/stm32f303"] +svd-f373 = ["f3", "stm32f3?/stm32f373"] +svd-f3x4 = ["f3", "stm32f3?/stm32f3x4"] + +gpio-f302 = [ + "can1", "comp2", "comp4", "comp6", "gpioc", "gpiof", "i2c2", "i2c3", "i2s", "i2s2", "i2s3", "ir", "rtc", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tsc", "usart1", "usart2", "usart3", +] +gpio-f303 = [ + "can1", "comp1", "comp2", "comp3", "comp4", "comp5", "comp6", "comp7", "gpioc", "gpiod", "gpioe", "gpiof", "i2c2", "i2s", "i2s2", "i2s3", "ir", "rtc", "spi1", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim8", "tsc", "uart4", "uart5", "usart1", "usart2", "usart3", "usb", +] +gpio-f303e = [ + "can1", "comp1", "comp2", "comp3", "comp4", "comp5", "comp6", "comp7", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "i2c2", "i2c3", "i2s", "i2s2", "i2s3", "ir", "rtc", "spi1", "spi2", "spi3", "spi4", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim20", "tim3", "tim4", "tim8", "tsc", "uart4", "uart5", "usart1", "usart2", "usart3", +] +gpio-f333 = [ + "can1", "comp2", "comp4", "comp6", "gpioc", "gpiod", "gpiof", "hrtim1", "ir", "opamp2", "spi1", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tsc", "usart1", "usart2", "usart3", +] +gpio-f373 = [ + "can1", "comp1", "comp2", "gpioc", "gpiod", "gpioe", "gpiof", "i2c2", "i2s1", "i2s2", "i2s3", "ir", "rtc", "spi1", "spi2", "spi3", "sys", "tim12", "tim13", "tim14", "tim15", "tim16", "tim17", "tim19", "tim2", "tim3", "tim4", "tim5", "tsc", "usart1", "usart2", "usart3", "usb", +] + +# F4 + #! Use one of the supported STM32-serie related features: #! `stm32f401`, `stm32f405`, `stm32f407`, `stm32f415`, `stm32f417`, `stm32f410`, #! `stm32f411`, `stm32f412`, `stm32f413`, `stm32f423`, `stm32f427`, `stm32f429`, @@ -130,89 +393,159 @@ features = ["macros"] # Note: stm32f4 has only one feature for some very similar device families, # so it's intended for e.g. stm32f405/415 to both enable stm32f4/stm32f405. -stm32f401 = ["stm32f4/stm32f401", "gpio-f401"] -stm32f405 = ["stm32f4/stm32f405", "gpio-f417"] -stm32f407 = ["stm32f4/stm32f407", "gpio-f417"] -stm32f415 = ["stm32f4/stm32f405", "gpio-f417", "cryp"] -stm32f417 = ["stm32f4/stm32f407", "gpio-f417", "cryp"] -stm32f410 = ["stm32f4/stm32f410", "gpio-f410"] -stm32f411 = ["stm32f4/stm32f411", "gpio-f411"] -stm32f412 = ["stm32f4/stm32f412", "gpio-f412"] -stm32f413 = ["stm32f4/stm32f413", "gpio-f413"] -stm32f423 = ["stm32f4/stm32f413", "gpio-f413", "aes"] -stm32f427 = ["stm32f4/stm32f427", "gpio-f427", "fsmc"] -stm32f429 = ["stm32f4/stm32f429", "gpio-f427", "fmc"] -stm32f437 = ["stm32f4/stm32f427", "gpio-f427", "fsmc", "cryp"] -stm32f439 = ["stm32f4/stm32f429", "gpio-f427", "fmc", "cryp"] -stm32f446 = ["stm32f4/stm32f446", "gpio-f446"] -stm32f469 = ["stm32f4/stm32f469", "gpio-f469"] -stm32f479 = ["stm32f4/stm32f469", "gpio-f469", "cryp"] +stm32f401 = ["svd-f401"] +stm32f405 = ["svd-f405"] +stm32f407 = ["svd-f407"] +stm32f415 = ["svd-f405", "cryp"] +stm32f417 = ["svd-f407", "cryp"] +stm32f410 = ["svd-f410"] +stm32f411 = ["svd-f411"] +stm32f412 = ["svd-f412"] +stm32f413 = ["svd-f413"] +stm32f423 = ["svd-f413", "aes"] +stm32f427 = ["svd-f427"] +stm32f429 = ["svd-f429"] +stm32f437 = ["svd-f427", "cryp"] +stm32f439 = ["svd-f429", "cryp"] +stm32f446 = ["svd-f446"] +stm32f469 = ["svd-f469"] +stm32f479 = ["svd-f469", "cryp"] + +svd-f401 = ["f4", "stm32f4?/stm32f401", "gpio-f401"] +svd-f405 = ["f4", "stm32f4?/stm32f405", "gpio-f417"] +svd-f407 = ["f4", "stm32f4?/stm32f407", "gpio-f417"] +svd-f410 = ["f4", "stm32f4?/stm32f410", "gpio-f410"] +svd-f411 = ["f4", "stm32f4?/stm32f411", "gpio-f411"] +svd-f412 = ["f4", "stm32f4?/stm32f412", "gpio-f412"] +svd-f413 = ["f4", "stm32f4?/stm32f413", "gpio-f413"] +svd-f427 = ["f4", "stm32f4?/stm32f427", "gpio-f427", "fsmc"] +svd-f429 = ["f4", "stm32f4?/stm32f429", "gpio-f427", "fmc"] +svd-f446 = ["f4", "stm32f4?/stm32f446", "gpio-f446"] +svd-f469 = ["f4", "stm32f4?/stm32f469", "gpio-f469"] gpio-f401 = [ + "gpioc", "gpiod", "gpioe", + "i2c2", "i2c3", - "otg-fs", + "i2s", + "i2s2", + "i2s2ext", + "i2s3", + "i2s3ext", + "rtc", "sdio", + "spi1", + "spi2", "spi3", "spi4", + "sys", "tim1", + "tim10", + "tim11", "tim2", "tim3", "tim4", "tim5", "tim9", - "tim10", - "tim11", + "usart1", + "usart2", + "usart6", ] gpio-f410 = [ - "dac", "fmpi2c1", + "gpioc", + "i2c2", + "i2s", + "i2s1", + "i2s2", + "i2s5", "lptim1", + "rtc", + "spi1", + "spi2", "spi5", + "sys", "tim1", + "tim11", "tim5", "tim6", "tim9", - "tim11", + "usart1", + "usart2", + "usart6", ] gpio-f411 = [ + "otg-fs", + "gpioc", "gpiod", - "gpioe", # "gpioi", + "gpioe", + "i2c2", "i2c3", - "otg-fs", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "i2s4", + "i2s5", + "rtc", "sdio", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + "sys", "tim1", + "tim10", + "tim11", "tim2", "tim3", "tim4", "tim5", "tim9", - "tim10", - "tim11", - "spi3", - "spi4", - "spi5", + "usart1", + "usart2", + "usart6", + ] gpio-f412 = [ - "gpiod", - "gpioe", - "gpiof", - "gpiog", + "otg-fs", + "rng", "can1", "can2", "dfsdm1", "fmpi2c1", "fsmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "i2c2", "i2c3", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "i2s4", + "i2s5", "quadspi", - "otg-fs", - "rng", + "rtc", "sdio", + "spi1", + "spi2", "spi3", "spi4", "spi5", + "sys", "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", "tim2", "tim3", "tim4", @@ -221,37 +554,52 @@ gpio-f412 = [ "tim7", "tim8", "tim9", - "tim10", - "tim11", - "tim12", - "tim13", - "tim14", + "usart1", + "usart2", "usart3", + "usart6", ] gpio-f413 = [ - "gpiod", - "gpioe", - "gpiof", - "gpiog", + "otg-fs", + "rng", + "aes", "can1", "can2", "can3", - "dac", "dfsdm1", "dfsdm2", - "fsmc", "fmpi2c1", + "fsmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "i2c2", "i2c3", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "i2s4", + "i2s5", "lptim1", "quadspi", - "otg-fs", - "rng", + "rtc", "sai1", "sdio", + "spi1", + "spi2", "spi3", "spi4", "spi5", + "sys", "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", "tim2", "tim3", "tim4", @@ -260,40 +608,51 @@ gpio-f413 = [ "tim7", "tim8", "tim9", - "tim10", - "tim11", - "tim12", - "tim13", - "tim14", - "usart3", + "uart10", "uart4", "uart5", "uart7", "uart8", "uart9", - "uart10", + "usart1", + "usart2", + "usart3", + "usart6", ] gpio-f417 = [ - "gpiod", - "gpioe", - "gpiof", - "gpiog", - "gpioi", "adc2", "adc3", + "otg-fs", + "otg-hs", + "rng", "can1", "can2", - "dac", "dcmi", - "eth", - "fsmc", + "eth", #"fsmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "gpioh", + "gpioi", + "i2c2", "i2c3", - "otg-fs", - "otg-hs", - "rng", + "i2s", + "i2s2", + "i2s3", + "rtc", "sdio", + "spi1", + "spi2", "spi3", + "sys", "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", "tim2", "tim3", "tim4", @@ -302,43 +661,55 @@ gpio-f417 = [ "tim7", "tim8", "tim9", - "tim10", - "tim11", - "tim12", - "tim13", - "tim14", - "usart3", "uart4", "uart5", + "usart1", + "usart2", + "usart3", + "usart6", ] gpio-f427 = [ + "adc2", + "adc3", + "dma2d", + "otg-fs", + "otg-hs", + "rng", + "can1", + "can2", + "dcmi", + "eth", + "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", + "gpioh", "gpioi", "gpioj", "gpiok", - "adc2", - "adc3", - "can1", - "can2", - "dac", - "dcmi", - "dma2d", - "eth", + "i2c2", "i2c3", + "i2s", + "i2s2", + "i2s3", "ltdc", - "otg-fs", - "otg-hs", - "rng", + "rtc", "sai1", "sdio", + "spi1", + "spi2", "spi3", "spi4", "spi5", "spi6", + "sys", "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", "tim2", "tim3", "tim4", @@ -347,41 +718,114 @@ gpio-f427 = [ "tim7", "tim8", "tim9", - "tim10", - "tim11", - "tim12", - "tim13", - "tim14", - "usart3", "uart4", "uart5", "uart7", "uart8", + "usart1", + "usart2", + "usart3", + "usart6", ] gpio-f446 = [ + "adc2", + "adc3", + "otg-fs", + "otg-hs", + "can1", + "can2", + "dcmi", + "fmc", + "fmpi2c1", + "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", + "i2c2", + "i2c3", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "quadspi", + "rtc", + "sai1", + "sai2", + "spdifrx", + "spi1", + "spi2", + "spi3", + "spi4", + "sys", + "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", + "tim2", + "tim3", + "tim4", + "tim5", + "tim6", + "tim7", + "tim8", + "tim9", + "uart4", + "uart5", + "usart1", + "usart2", + "usart3", + "usart6", + "sdio", + +] +gpio-f469 = [ "adc2", "adc3", + "dma2d", + "otg-fs", + "otg-hs", + "rng", "can1", "can2", - "dac", "dcmi", - "fmpi2c1", + "dsihost", + "eth", "fmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "gpioh", + "gpioi", + "gpioj", + "gpiok", + "i2c2", "i2c3", + "i2s", + "i2s2", + "i2s3", + "ltdc", "quadspi", - "otg-fs", - "otg-hs", + "rtc", "sai1", - "sai2", "sdio", + "spi1", + "spi2", "spi3", "spi4", - "spdifrx", + "spi5", + "spi6", + "sys", "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", "tim2", "tim3", "tim4", @@ -390,65 +834,425 @@ gpio-f446 = [ "tim7", "tim8", "tim9", + "uart4", + "uart5", + "uart7", + "uart8", + "usart1", + "usart2", + "usart3", + "usart6", +] + +# F7 + +stm32f722 = ["svd-f7x2"] +stm32f723 = ["svd-f7x3", "usb_hs_phy"] +stm32f730 = ["svd-f730", "usb_hs_phy"] +stm32f732 = ["svd-f7x2"] +stm32f733 = ["svd-f7x3", "usb_hs_phy"] +stm32f745 = ["svd-f745"] +stm32f746 = ["svd-f7x6"] +stm32f756 = ["svd-f7x6"] +stm32f765 = ["svd-f765"] +stm32f767 = ["svd-f7x7"] +stm32f769 = ["svd-f7x9"] +stm32f777 = ["svd-f7x7"] +stm32f778 = ["svd-f7x9"] +stm32f779 = ["svd-f7x9"] + +svd-f7x2 = ["f7", "stm32f7?/stm32f7x2", "gpio-f72x"] +svd-f7x3 = ["f7", "stm32f7?/stm32f7x3", "gpio-f72x"] +svd-f730 = ["f7", "stm32f7?/stm32f730", "gpio-f72x"] +svd-f745 = ["f7", "stm32f7?/stm32f745", "gpio-f746"] +svd-f7x6 = ["f7", "stm32f7?/stm32f7x6", "gpio-f746"] +svd-f765 = ["f7", "stm32f7?/stm32f765", "gpio-f76x"] +svd-f7x7 = ["f7", "stm32f7?/stm32f7x7", "gpio-f76x"] +svd-f7x9 = ["f7", "stm32f7?/stm32f7x9", "gpio-f76x"] + +gpio-f72x = [ + "adc2", + "adc3", + "aes", + "can1", + "fmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "gpioh", + "gpioi", + "i2c2", + "i2c3", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "lptim1", + "quadspi", + "rtc", + "sai1", + "sai2", + "sdmmc1", + "sdmmc2", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + "sys", + "tim1", "tim10", "tim11", "tim12", "tim13", "tim14", - "usart3", + "tim2", + "tim3", + "tim4", + "tim5", + "tim8", + "tim9", "uart4", "uart5", + "uart7", + "uart8", + "usart1", + "usart2", + "usart3", + "usart6", + "otg-fs", + "otg-hs", ] -gpio-f469 = [ +gpio-f746 = [ + "adc2", + "adc3", + "dma2d", + "can1", + "can2", + "cryp", + "dcmi", + "eth", + "fmc", + "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", + "gpioh", "gpioi", "gpioj", "gpiok", + "hash", + "i2c2", + "i2c3", + "i2c4", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "lptim1", + "ltdc", + "quadspi", + "rtc", + "sai1", + "sai2", + "sdmmc1", + "spdifrx", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + "spi6", + "sys", + "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", + "tim2", + "tim3", + "tim4", + "tim5", + "tim8", + "tim9", + "uart4", + "uart5", + "uart7", + "uart8", + "usart1", + "usart2", + "usart3", + "usart6", + "otg-fs", + "otg-hs", +] +gpio-f76x = [ "adc2", "adc3", + "dma2d", "can1", "can2", - "dac", - "dma2d", + "cryp", + "can3", "dcmi", + "dfsdm1", "dsihost", "eth", "fmc", + "gpioc", + "gpiod", + "gpioe", + "gpiof", + "gpiog", + "gpioh", + "gpioi", + "gpioj", + "gpiok", + "hash", + "i2c2", "i2c3", + "i2c4", + "i2s", + "i2s1", + "i2s2", + "i2s3", + "lptim1", "ltdc", + "mdios", "quadspi", - "otg-fs", - "otg-hs", - "rng", + "rtc", "sai1", - "sdio", + "sai2", + "sdmmc1", + "sdmmc2", + "spdifrx", + "spi1", + "spi2", "spi3", "spi4", "spi5", "spi6", + "sys", "tim1", + "tim10", + "tim11", + "tim12", + "tim13", + "tim14", "tim2", "tim3", "tim4", "tim5", - "tim6", - "tim7", "tim8", "tim9", - "tim10", - "tim11", - "tim12", - "tim13", - "tim14", - "usart3", "uart4", "uart5", "uart7", "uart8", + "usart1", + "usart2", + "usart3", + "usart6", + "otg-fs", + "otg-hs", +] + +# G0 + +gpio-g03x = [ + "gpioc", "gpiod", "gpiof", "i2c2", "i2s", "i2s1", "ir", "lptim1", "lptim2", "lpuart1", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "usart1", "usart2", ] +gpio-g05x = [ + "comp1", "comp2", "gpioc", "gpiod", "gpiof", "i2c2", "i2s", "i2s1", "ir", "lptim1", "lptim2", "lpuart1", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "usart1", "usart2", +] +gpio-g07x = [ + "comp1", "comp2", "gpioc", "gpiod", "gpiof", "i2c2", "i2s", "i2s1", "ir", "lptim1", "lptim2", "lpuart1", "spi1", "spi2", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "ucpd1", "ucpd2", "usart1", "usart2", "usart3", "usart4", +] +gpio-g0bx = [ + "comp1", "comp2", "comp3", "crs1", "fdcan1", "fdcan2", "gpioc", "gpiod", "gpioe", "gpiof", "i2c2", "i2c3", "i2s", "i2s1", "i2s2", "ir", "lptim1", "lptim2", "lpuart1", "lpuart2", "spi1", "spi2", "spi3", "sys", "tim1", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "ucpd1", "ucpd2", "usart1", "usart2", "usart3", "usart4", "usart5", "usart6", "usb", +] + +# G4 + +stm32g431 = ["svd-g431"] +stm32g441 = ["svd-g441"] +stm32g471 = ["svd-g471"] +stm32g473 = ["svd-g473"] +stm32g474 = ["svd-g474"] +stm32g483 = ["svd-g483"] +stm32g484 = ["svd-g484"] +stm32g491 = ["svd-g491"] +stm32g4a1 = ["svd-g4a1"] + +svd-g431 = ["g4", "stm32g4?/stm32g431", "gpio-g43x"] +svd-g441 = ["g4", "stm32g4?/stm32g441", "gpio-g43x"] +svd-g471 = ["g4", "stm32g4?/stm32g471", "gpio-g47x"] +svd-g473 = ["g4", "stm32g4?/stm32g473", "gpio-g47x"] +svd-g474 = ["g4", "stm32g4?/stm32g474", "gpio-g47x"] +svd-g483 = ["g4", "stm32g4?/stm32g483", "gpio-g47x"] +svd-g484 = ["g4", "stm32g4?/stm32g484", "gpio-g47x"] +svd-g491 = ["g4", "stm32g4?/stm32g491", "gpio-g49x"] +svd-g4a1 = ["g4", "stm32g4?/stm32g4a1", "gpio-g49x"] + +gpio-g43x = [ + "comp1", "comp2", "comp3", "comp4", "crs", "fdcan1", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "i2c2", "i2c3", "i2s", "i2s2", "i2s3", "ir", "lptim1", "lpuart1", "rtc", "sai1", "spi1", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim8", "uart4", "ucpd1", "usart1", "usart2", "usart3", +] +gpio-g47x = [ + "comp1", "comp2", "comp3", "comp4", "comp5", "comp6", "comp7", "crs", "fdcan1", "fdcan2", "fdcan3", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "hrtim1", "i2c2", "i2c3", "i2c4", "i2s", "i2s2", "i2s3", "ir", "lptim1", "lpuart1", "quadspi", "rtc", "sai1", "spi1", "spi2", "spi3", "spi4", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim20", "tim3", "tim4", "tim5", "tim8", "uart4", "uart5", "ucpd1", "usart1", "usart2", "usart3", +] +gpio-g49x = [ + "comp1", "comp2", "comp3", "comp4", "crs", "fdcan1", "fdcan2", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "i2c2", "i2c3", "i2s", "i2s2", "i2s3", "ir", "lptim1", "lpuart1", "quadspi", "rtc", "sai1", "spi1", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim20", "tim3", "tim4", "tim8", "uart4", "uart5", "ucpd1", "usart1", "usart2", "usart3", +] + +# H7 + +gpio-h72 = [ + "comp1", "comp2", "crs", "dcmi", "debug", "dfsdm1", "eth", "fdcan1", "fdcan2", "fdcan3", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioj", "gpiok", "i2c2", "i2c3", "i2c4", "i2c5", "i2s", "i2s1", "i2s2", "i2s3", "i2s6", "lptim1", "lptim2", "lptim3", "lptim4", "lptim5", "lpuart1", "ltdc", "mdios", "octospi", "pssi", "rtc", "sai1", "sai4", "sdmmc1", "sdmmc2", "spdifrx", "spi1", "spi2", "spi3", "spi4", "spi5", "spi6", "swpmi1", "tim1", "tim12", "tim13", "tim14", "tim15", "tim16", "tim17", "tim2", "tim23", "tim24", "tim3", "tim4", "tim5", "tim8", "uart4", "uart5", "uart7", "uart8", "uart9", "usart1", "usart10", "usart2", "usart3", "usart6", "otg-hs", +] +gpio-h747 = [ + "comp1", "comp2", "crs", "dcmi", "debug", "dfsdm1", "dsihost", "eth", "fdcan1", "fdcan2", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "gpioj", "gpiok", "hrtim1", "i2c2", "i2c3", "i2c4", "i2s", "i2s1", "i2s2", "i2s3", "lptim1", "lptim2", "lptim3", "lptim4", "lptim5", "lpuart1", "ltdc", "mdios", "quadspi", "rtc", "sai1", "sai2", "sai3", "sai4", "sdmmc1", "sdmmc2", "spdifrx", "spi1", "spi2", "spi3", "spi4", "spi5", "spi6", "swpmi1", "sys", "tim1", "tim12", "tim13", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "uart4", "uart5", "uart7", "uart8", "usart1", "usart2", "usart3", "usart6", "otg-fs", "otg-hs", +] +gpio-h7a2 = [ + "comp1", "comp2", "crs", "dcmi", "debug", "dfsdm1", "dfsdm2", "fdcan1", "fdcan2", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "gpioj", "gpiok", "i2c2", "i2c3", "i2c4", "i2s", "i2s1", "i2s2", "i2s3", "i2s6", "lptim1", "lptim2", "lptim3", "lpuart1", "ltdc", "mdios", "octospi", "pssi", "pwr", "rtc", "sai1", "sai2", "sdmmc1", "sdmmc2", "spdifrx", "spi1", "spi2", "spi3", "spi4", "spi5", "spi6", "swpmi1", "tim1", "tim12", "tim13", "tim14", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "uart4", "uart5", "uart7", "uart8", "uart9", "usart1", "usart10", "usart2", "usart3", "usart6", "otg-hs", +] + +# L0 + +gpio-l021 = [ + "comp1", "comp2", "lptim1", "lpuart1", "rtc", "spi1", "sys", "tim2", "tim21", "usart2", +] +gpio-l031 = [ + "comp1", "comp2", "gpioc", "lptim1", "lpuart1", "rtc", "spi1", "sys", "tim2", "tim21", "tim22", "usart2", +] +gpio-l051 = [ + "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioh", "i2c2", "i2s2", "lcd", "lptim1", "lpuart1", "rtc", "spi1", "spi2", "sys", "tim2", "tim21", "tim22", "tsc", "usart1", "usart2", "usb", +] +gpio-l071 = [ + "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioe", "gpioh", "i2c2", "i2c3", "i2s2", "lcd", "lptim1", "lpuart1", "rtc", "spi1", "spi2", "sys", "tim2", "tim21", "tim22", "tim3", "tsc", "usart1", "usart2", "usart4", "usart5", "usb", +] + +# L1 + +gpio-l152x8 = [ + "gpioc", "gpiod", "gpioe", "gpioh", "i2c2", "lcd", "rtc", "spi1", "spi2", "sys", "tim10", "tim11", "tim2", "tim3", "tim4", "tim9", "timx", "ts", "usart1", "usart2", "usart3", "usb", +] +gpio-l152xc = [ + "gpioc", "gpiod", "gpioe", "gpioh", "i2c2", "i2s2", "i2s3", "lcd", "rtc", "spi1", "spi2", "spi3", "sys", "tim10", "tim11", "tim2", "tim3", "tim4", "tim5", "tim9", "timx", "ts", "usart1", "usart2", "usart3", "usb", +] +gpio-l15xxa = [ + "gpioc", "gpiod", "gpioe", "gpioh", "i2c2", "i2s2", "i2s3", "lcd", "rtc", "spi1", "spi2", "spi3", "sys", "tim10", "tim11", "tim2", "tim3", "tim4", "tim5", "tim9", "timx", "ts", "usart1", "usart2", "usart3", "usb", +] +gpio-l162xd = [ + "fsmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "i2c2", "i2s2", "i2s3", "lcd", "rtc", "sdio", "spi1", "spi2", "spi3", "sys", "tim10", "tim11", "tim2", "tim3", "tim4", "tim5", "tim9", "timx", "ts", "uart4", "uart5", "usart1", "usart2", "usart3", "usb", +] +gpio-l162xe = [ + "comp1", "comp2", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "i2c2", "i2s2", "i2s3", "lcd", "rtc", "spi1", "spi2", "spi3", "sys", "tim10", "tim11", "tim2", "tim3", "tim4", "tim5", "tim9", "timx", "ts", "uart4", "uart5", "usart1", "usart2", "usart3", "usb", "v_ref", +] + +# L4 + +stm32l431 = [ "svd-l4x1", "gpio-l43x" ] +stm32l451 = [ "svd-l4x1", "gpio-l45x" ] +stm32l471 = [ "svd-l4x1", "gpio-l47x" ] +stm32l412 = [ "svd-l412", "gpio-l41x" ] +stm32l422 = [ "svd-l412", "gpio-l41x" ] +stm32l432 = [ "svd-l4x2", "gpio-l43x" ] +stm32l442 = [ "svd-l4x2", "gpio-l43x" ] +stm32l452 = [ "svd-l4x2", "gpio-l45x" ] +stm32l462 = [ "svd-l4x2", "gpio-l45x" ] +stm32l433 = [ "svd-l4x3", "gpio-l43x" ] +stm32l443 = [ "svd-l4x3", "gpio-l43x" ] +stm32l475 = [ "svd-l4x5", "gpio-l47x" ] +stm32l476 = [ "svd-l4x6", "gpio-l47x" ] +stm32l486 = [ "svd-l4x6", "gpio-l47x" ] +stm32l496 = [ "svd-l4x6", "gpio-l49x" ] +stm32l4a6 = [ "svd-l4x6", "gpio-l49x" ] + +svd-l4x1 = [ "l4x", "stm32l4?/stm32l4x1" ] +svd-l412 = [ "l4x", "stm32l4?/stm32l412" ] +svd-l4x2 = [ "l4x", "stm32l4?/stm32l4x2" ] +svd-l4x3 = [ "l4x", "stm32l4?/stm32l4x3" ] +svd-l4x5 = [ "l4x", "stm32l4?/stm32l4x5" ] +svd-l4x6 = [ "l4x", "stm32l4?/stm32l4x6" ] + +gpio-l41x = [ + "comp1", "crs", "gpioc", "gpiod", "i2c2", "i2c3", "ir", "lptim1", "lptim2", "lpuart1", "quadspi", "rtc", "spi1", "spi2", "sys", "tim1", "tim15", "tim16", "tim2", "tsc", "usart1", "usart2", "usart3", "usb", +] +gpio-l43x = [ + "can1", "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioe", "i2c2", "i2c3", "ir", "lcd", "lptim1", "lptim2", "lpuart1", "quadspi", "rtc", "sai1", "sdmmc1", "spi1", "spi2", "spi3", "swpmi1", "sys", "tim1", "tim15", "tim16", "tim2", "tsc", "usart1", "usart2", "usart3", "usb", +] +gpio-l45x = [ + "can1", "comp1", "comp2", "crs", "dfsdm1", "gpioc", "gpiod", "gpioe", "i2c2", "i2c3", "i2c4", "ir", "lptim1", "lptim2", "lpuart1", "quadspi", "rtc", "sai1", "sdmmc1", "spi1", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim2", "tim3", "tsc", "uart4", "usart1", "usart2", "usart3", "usb", +] +gpio-l47x = [ + "can1", "comp1", "comp2", "dfsdm1", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "i2c2", "i2c3", "ir", "lcd", "lptim1", "lptim2", "lpuart1", "quadspi", "rtc", "sai1", "sai2", "sdmmc1", "spi1", "spi2", "spi3", "swpmi1", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "usart1", "usart2", "usart3", "otg-fs", +] +gpio-l49x = [ + "can1", "can2", "comp1", "comp2", "crs", "dcmi", "dfsdm1", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "i2c2", "i2c3", "i2c4", "ir", "lcd", "lptim1", "lptim2", "lpuart1", "quadspi", "rtc", "sai1", "sai2", "sdmmc1", "spi1", "spi2", "spi3", "swpmi1", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "usart1", "usart2", "usart3", "otg-fs", +] + +# L4+ + +#stm32l4p5 = [ "svd-l4x5", "gpio-l4p" ] +#stm32l4q5 = [ "svd-l4x5", "gpio-l4p" ] +#stm32l4r5 = [ "svd-l4x5", "gpio-l4rx" ] +#stm32l4s5 = [ "svd-l4x5", "gpio-l4rx" ] +#stm32l4r7 = [ "svd-l4x7", "gpio-l4rx" ] +#stm32l4s7 = [ "svd-l4x7", "gpio-l4rx" ] +stm32l4r9 = [ "svd-l4r9", "gpio-l4rx" ] # PAC has an L4r9 specific variation +stm32l4s9 = [ "svd-l4r9", "gpio-l4rx" ] + +#svd-l4x5 = [ "l4p", "stm32l4?/stm32l4x5" ] +#svd-l4x7 = [ "l4p", "stm32l4?/stm32l4x7" ] +svd-l4r9 = [ "l4p", "stm32l4?/stm32l4r9" ] + +gpio-l4p = [ + "can1", "comp1", "comp2", "crs", "dcmi", "dfsdm1", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "i2c2", "i2c3", "i2c4", "ir", "lptim1", "lptim2", "lpuart1", "ltdc", "octospi", "pssi", "rtc", "sai1", "sai2", "sdmmc1", "sdmmc2", "spi1", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "usart1", "usart2", "usart3", "otg-fs", +] +gpio-l4rx = [ + "can1", "comp1", "comp2", "crs", "dcmi", "dfsdm1", "dsihost", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "i2c2", "i2c3", "i2c4", "ir", "lptim1", "lptim2", "lpuart1", "ltdc", "octospi", "rtc", "sai1", "sai2", "sdmmc1", "spi1", "spi2", "spi3", "sys", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "usart1", "usart2", "usart3", "otg-fs", +] + +# L5 + +gpio-l55x = [ + "comp1", "comp2", "crs", "debug", "dfsdm1", "fdcan1", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "i2c2", "i2c3", "i2c4", "ir", "lptim1", "lptim2", "lptim3", "lpuart1", "octospi", "rtc", "sai1", "sai2", "sdmmc1", "spi1", "spi2", "spi3", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "ucpd1", "usart1", "usart2", "usart3", "usb", +] + +# U5 + +gpio-u59x = [ + "adf1", "comp1", "comp2", "crs", "dcmi", "debug", "dsihost", "fdcan1", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "gpioj", "hspi1", "i2c2", "i2c3", "i2c4", "i2c5", "i2c6", "ir", "lptim1", "lptim2", "lptim3", "lptim4", "lpuart1", "ltdc", "mdf1", "octospi", "pssi", "pwr", "rtc", "sai1", "sai2", "sdmmc1", "sdmmc2", "spi1", "spi2", "spi3", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "ucpd1", "usart1", "usart2", "usart3", "usart6", "otg-hs", +] +gpio-u5x = [ + "adf1", "comp1", "comp2", "crs", "dcmi", "debug", "fdcan1", "fmc", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", "gpioh", "gpioi", "i2c2", "i2c3", "i2c4", "ir", "lptim1", "lptim2", "lptim3", "lptim4", "lpuart1", "mdf1", "octospi", "pssi", "pwr", "rtc", "sai1", "sai2", "sdmmc1", "sdmmc2", "spi1", "spi2", "spi3", "tim1", "tim15", "tim16", "tim17", "tim2", "tim3", "tim4", "tim5", "tim8", "tsc", "uart4", "uart5", "ucpd1", "usart1", "usart2", "usart3", "otg-fs", +] + +# WB + +gpio-wb35x = [ + "cm4", "comp1", "gpioc", "gpioe", "gpioh", "lptim1", "lptim2", "lpuart1", "rf", "rtc", "spi1", "sys", "tim1", "tim2", "tsc", "usart1", +] +gpio-wb3x = [ + "cm4", "comp1", "comp2", "crs", "gpioc", "gpioe", "gpioh", "i2c3", "ir", "lptim1", "lptim2", "lpuart1", "quadspi", "sai1", "spi1", "sys", "tim1", "tim16", "tim17", "tim2", "usart1", "usb", +] +gpio-wb55x = [ + "cm4", "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioe", "gpioh", "i2c3", "ir", "lcd", "lptim1", "lptim2", "lpuart1", "quadspi", "rf", "rtc", "sai1", "spi1", "spi2", "sys", "tim1", "tim16", "tim17", "tim2", "tsc", "usart1", "usb", +] +gpio-wb5mx = [ + "cm4", "comp1", "comp2", "crs", "gpioc", "gpiod", "gpioe", "gpioh", "i2c3", "ir", "lcd", "lptim1", "lptim2", "lpuart1", "quadspi", "rf", "rtc", "sai1", "spi1", "spi2", "sys", "tim1", "tim16", "tim17", "tim2", "tsc", "usart1", "usb", +] + +# WL + +gpio-wl = [ + "cm4", "comp1", "comp2", "debug", "gpioc", "gpioh", "i2c2", "i2c3", "i2s", "i2s2", "ir", "lptim1", "lptim2", "lptim3", "lpuart1", "rf", "rtc", "spi1", "spi2", "sys", "tim1", "tim16", "tim17", "tim2", "usart1", "usart2", +] + ## Support monotonic timers and other stuff that can be used by [RTICv1 framework](https://crates.io/crates/cortex-m-rtic) rtic1 = ["dep:rtic-monotonic", "dep:systick-monotonic", "cortex-m-rtic"] @@ -487,48 +1291,114 @@ fsmc_lcd = ["dep:display-interface", "dep:display-interface-04"] ## SDIO peripheral support. See [sdio-host](https://crates.io/crates/sdio-host) sdio-host = ["dep:sdio-host"] +bb = [] +dma = [] +i2c_v1 = [] +i2c_v2 = [] +spi_v1 = [] +spi_v2 = [] +uart_v2 = [] +uart_v3 = [] +usb_hs_phy = [] dfsdm = [] sai = [] adc2 = [] adc3 = [] +adf1 = [] aes = [] can1 = [] can2 = [] can3 = [] cryp = [] +cm4 = [] +crs1 = [] +comp1 = [] +comp2 = [] +comp3 = [] +comp4 = [] +comp5 = [] +comp6 = [] +comp7 = [] +crs = [] dac = [] dcmi = [] +debug = [] dfsdm1 = ["dfsdm"] dfsdm2 = ["dfsdm"] dma2d = [] dsihost = [] +hash = [] eth = [] +fdcan1 = [] +fdcan2 = [] +fdcan3 = [] fmc = [] fsmc = [] -fmpi2c1 = [] +fmpi2c1 = ["dep:micromath"] +gpioc = [] gpiod = [] gpioe = [] gpiof = [] gpiog = [] +gpioh = [] gpioi = [] gpioj = [] gpiok = [] +hdmi = [] +hrtim1 = [] +hspi1 = [] +i2c2 = [] i2c3 = [] +i2c4 = [] +i2c5 = [] +i2c6 = [] +i2s1 = [] +i2s2 = [] +i2s2ext = [] +i2s3 = [] +i2s3ext = [] +i2s4 = [] +i2s5 = [] +i2s6 = [] +ir = [] +lcd = [] lptim1 = [] +lptim2 = [] +lptim3 = [] +lptim4 = [] +lptim5 = [] +lpuart1 = [] +lpuart2 = [] ltdc = ["dep:micromath"] +mdios = [] +mdf1 = [] quadspi = [] +octospi = [] +opamp2 = [] otg-fs = [] otg-hs = [] +pssi = [] +pwr = [] +rf = [] rng = [] +rtc = [] sai1 = ["sai"] sai2 = ["sai"] +sai3 = [] +sai4 = [] sdio = [] +sdmmc1 = [] +sdmmc2 = [] +spi1 = [] +spi2 = [] spi3 = [] spi4 = [] spi5 = [] spi6 = [] +sys = [] spdifrx = [] +swpmi1 = [] tim1 = [] tim2 = [] tim3 = [] @@ -543,13 +1413,39 @@ tim11 = [] tim12 = [] tim13 = [] tim14 = [] +tim15 = [] +tim16 = [] +tim17 = [] +tim19 = [] +tim20 = [] +tim21 = [] +tim22 = [] +tim23 = [] +tim24 = [] +timx = [] +ts = [] +tsc = [] +ucpd1 = [] +ucpd2 = [] +usart1 = [] +usart2 = [] usart3 = [] +usart4 = [] +usart5 = [] +usart6 = [] +usart7 = [] +usart8 = [] +usart10 = [] uart4 = [] uart5 = [] uart7 = [] uart8 = [] uart9 = [] uart10 = [] +usb = [] # "dep:stm32-usbd" +v_ref = [] + +disabled = [] [profile.dev] debug = true @@ -564,7 +1460,7 @@ opt-level = "s" [[example]] name = "analog-stopwatch-with-spi-ssd1306" -required-features = ["spi4", "tim2", "gpioe", "gpiog"] # stm32f429 +required-features = ["f4", "spi4", "tim2", "gpioe", "gpiog"] # stm32f429 [[example]] name = "blinky-timer-irq" @@ -643,7 +1539,7 @@ required-features = ["rng"] # stm32f407 [[example]] name = "rtc" -required-features = [] +required-features = ["f4"] [[example]] name = "rtc_alarm" @@ -651,7 +1547,7 @@ required-features = ["stm32f411"] [[example]] name = "rtic-adc-dma" -required-features = ["rtic1"] # stm32f401 +required-features = ["rtic1", "f4"] # stm32f401 [[example]] name = "rtic-button" @@ -721,6 +1617,10 @@ required-features = ["stm32f411"] name = "uart-dma" required-features = ["stm32f405"] +[[example]] +name = "spi_16" +required-features = ["gpiod"] + [[example]] name = "ssd1306-image" required-features = [] # stm32f411 @@ -755,8 +1655,9 @@ required-features = ["otg-fs", "usb_fs"] # stm32f407 [[example]] name = "usb-serial-poll" -required-features = ["otg-fs", "usb_fs"] # stm32f401 +required-features = ["otg-fs", "usb_fs", "f4"] # stm32f401 [[example]] name = "ws2812-spi" required-features = [] + diff --git a/README.md b/README.md index 3a031deb..d3cd15c8 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ stm32f4xx-hal [![Continuous integration](https://github.com/stm32-rs/stm32f4xx-hal/workflows/Continuous%20integration/badge.svg)](https://github.com/stm32-rs/stm32f4xx-hal) _stm32f4xx-hal_ contains a multi device hardware abstraction on top of the -peripheral access API for the STMicro STM32F4 series microcontrollers. The +peripheral access API for the STMicro STM32F2/F4/F7 series microcontrollers. The selection of the MCU is done by feature gates, typically specified by board support crates. Currently supported configurations are: @@ -17,28 +17,50 @@ support crates. Currently supported configurations are: +* stm32f215 +* stm32f217 +* * stm32f401 * stm32f405 * stm32f407 + + * stm32f410 * stm32f411 * stm32f412 - - * stm32f413 * stm32f415 * stm32f417 * stm32f423 -* stm32f427 -* stm32f429 +* stm32f427 +* stm32f429 * stm32f437 * stm32f439 * stm32f446 * stm32f469 * stm32f479 + + +* stm32f722 +* stm32f723 +* stm32f730 +* stm32f732 +* stm32f733 +* stm32f745 +* stm32f746 + + +* stm32f756 +* stm32f765 +* stm32f767 +* stm32f769 +* stm32f777 +* stm32f778 +* stm32f779 + The idea behind this crate is to gloss over the slight differences in the diff --git a/build.rs b/build.rs index 8e25570e..c27e5348 100644 --- a/build.rs +++ b/build.rs @@ -23,7 +23,12 @@ impl IteratorExt for T { fn main() { let _chip_name = match env::vars() .map(|(a, _)| a) - .filter(|x| x.starts_with("CARGO_FEATURE_STM32F4")) + .filter(|x| { + x.starts_with("CARGO_FEATURE_STM32F3") + || x.starts_with("CARGO_FEATURE_STM32F4") + || x.starts_with("CARGO_FEATURE_STM32F7") + || x.starts_with("CARGO_FEATURE_STM32L4") + }) .get_one() { Ok(x) => x, diff --git a/examples/display-touch.rs b/examples/display-touch.rs index 1976403e..11857897 100644 --- a/examples/display-touch.rs +++ b/examples/display-touch.rs @@ -1,4 +1,4 @@ -//! +//! //! Demonstrates use of I2C bus to configure and use FT6x06 touchscreen controller //! //! Hardware Required: STM32F412G-DISCO board or STM32F413H-DISCO board diff --git a/examples/spi_16.rs b/examples/spi_16.rs new file mode 100644 index 00000000..fcd69979 --- /dev/null +++ b/examples/spi_16.rs @@ -0,0 +1,60 @@ +#![no_main] +#![no_std] + +use panic_semihosting as _; + +use stm32f4xx_hal as hal; + +use hal::{ + pac, + prelude::*, + spi::{NoMiso, Spi}, +}; + +use cortex_m_rt::entry; + +#[entry] +fn main() -> ! { + let p = pac::Peripherals::take().unwrap(); + + let rcc = p.RCC.constrain(); + let clocks = rcc.cfgr.freeze(); + + let gpioa = p.GPIOA.split(); + let gpioc = p.GPIOC.split(); + let gpiod = p.GPIOD.split(); + + // Configure pin for button. This happens to be the pin for the USER button + // on the NUCLEO-F746ZG board. + let button = gpioc.pc13.into_floating_input(); + + // Prepare pins for SPI + let mut ncs = gpiod.pd14.into_push_pull_output(); + let sck = gpioa.pa5; + let mosi = gpioa.pa7; + + // Set NCS pin to high (disabled) initially + ncs.set_high(); + + // Initialize SPI + let mut spi = Spi::new( + p.SPI1, + (sck, NoMiso::new(), mosi), + embedded_hal::spi::MODE_0, + 250.kHz(), + &clocks, + ) + .frame_size_16bit(); + + // Use a button to control output via the Maxim Integrated MAX5214 DAC. + loop { + let data = if button.is_high() { 0xffff } else { 0x0000 }; + + let word: u16 = (0b01 << 14) | // write-through mode + (data & 0x3fff); // data bits + + ncs.set_low(); + spi.write(&[word]).unwrap(); + ncs.set_high(); + } +} diff --git a/src/adc.rs b/src/adc.rs index 9c0d23c4..2b75439f 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -140,8 +140,13 @@ use crate::{ use core::fmt; pub mod config; + +#[cfg(feature = "f4")] mod f4; +#[cfg(feature = "f7")] +mod f7; + /// Vref internal signal, used for calibration pub struct Vref; diff --git a/src/adc/f2.rs b/src/adc/f2.rs new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/src/adc/f2.rs @@ -0,0 +1 @@ + diff --git a/src/adc/f4.rs b/src/adc/f4.rs index f1d1cb1b..87e56d14 100644 --- a/src/adc/f4.rs +++ b/src/adc/f4.rs @@ -12,7 +12,7 @@ adc_pins!( gpio::PA7 => (ADC1, 7), gpio::PB0 => (ADC1, 8), gpio::PB1 => (ADC1, 9), - Temperature => (ADC1, 16), + Temperature => (ADC1, 18), Vbat => (ADC1, 18), Vref => (ADC1, 17), ); @@ -205,7 +205,7 @@ adc_pins!( gpio::PA7 => (ADC1, 7), gpio::PB0 => (ADC1, 8), gpio::PB1 => (ADC1, 9), - Temperature => (ADC1, 16), + Temperature => (ADC1, 18), Vbat => (ADC1, 18), Vref => (ADC1, 17), ); diff --git a/src/adc/f7.rs b/src/adc/f7.rs new file mode 100644 index 00000000..53db7ca6 --- /dev/null +++ b/src/adc/f7.rs @@ -0,0 +1,63 @@ +use super::*; + +// See "Datasheet - production data" +// Pinouts and pin description (page 66..) +adc_pins!( + gpio::PA0 => (ADC1, 0), + gpio::PA1 => (ADC1, 1), + gpio::PA2 => (ADC1, 2), + gpio::PA3 => (ADC1, 3), + gpio::PA4 => (ADC1, 4), + gpio::PA5 => (ADC1, 5), + gpio::PA6 => (ADC1, 6), + gpio::PA7 => (ADC1, 7), + gpio::PB0 => (ADC1, 8), + gpio::PB1 => (ADC1, 9), + gpio::PC0 => (ADC1, 10), + gpio::PC1 => (ADC1, 11), + gpio::PC2 => (ADC1, 12), + gpio::PC3 => (ADC1, 13), + gpio::PC4 => (ADC1, 14), + gpio::PC5 => (ADC1, 15), + Temperature => (ADC1, 18), + Vbat => (ADC1, 18), + Vref => (ADC1, 17), +); + +adc_pins!( + gpio::PA0 => (ADC2, 0), + gpio::PA1 => (ADC2, 1), + gpio::PA2 => (ADC2, 2), + gpio::PA3 => (ADC2, 3), + gpio::PA4 => (ADC2, 4), + gpio::PA5 => (ADC2, 5), + gpio::PA6 => (ADC2, 6), + gpio::PA7 => (ADC2, 7), + gpio::PB0 => (ADC2, 8), + gpio::PB1 => (ADC2, 9), + gpio::PC0 => (ADC2, 10), + gpio::PC1 => (ADC2, 11), + gpio::PC2 => (ADC2, 12), + gpio::PC3 => (ADC2, 13), + gpio::PC4 => (ADC2, 14), + gpio::PC5 => (ADC2, 15), +); + +adc_pins!( + gpio::PA0 => (ADC3, 0), + gpio::PA1 => (ADC3, 1), + gpio::PA2 => (ADC3, 2), + gpio::PA3 => (ADC3, 3), + gpio::PF6 => (ADC3, 4), + gpio::PF7 => (ADC3, 5), + gpio::PF8 => (ADC3, 6), + gpio::PF9 => (ADC3, 7), + gpio::PF10 => (ADC3, 8), + gpio::PF3 => (ADC3, 9), + gpio::PC0 => (ADC3, 10), + gpio::PC1 => (ADC3, 11), + gpio::PC2 => (ADC3, 12), + gpio::PC3 => (ADC3, 13), + gpio::PF4 => (ADC3, 14), + gpio::PF5 => (ADC3, 15), +); diff --git a/src/adc/l4.rs b/src/adc/l4.rs new file mode 100644 index 00000000..e29c0766 --- /dev/null +++ b/src/adc/l4.rs @@ -0,0 +1,990 @@ +//! # Analog to Digital converter + +use core::{ + convert::Infallible, + marker::PhantomData, + //ops::DerefMut, + //sync::atomic::{self, Ordering}, +}; +#[cfg(feature = "dma")] +use stable_deref_trait::StableDeref; + +#[cfg(feature = "dma")] +use crate::{ + dma::{dma1, Event as DMAEvent, RxDma, Transfer, TransferPayload, W}, + dmamux::{DmaInput, DmaMux}, +}; +use crate::{ + gpio::{self, Analog}, + hal::{ + adc::{Channel as EmbeddedHalChannel, OneShot}, + blocking::delay::DelayUs, + }, + pac::{self, ADC1}, + rcc::{Enable, Reset, AHB2, CCIPR}, + signature::{VrefCal, VtempCalHigh, VtempCalLow, VDDA_CALIB_MV}, +}; + +/// Internal voltage reference channel, used for calibration. +pub struct Vref { + _0: (), +} + +/// Internal battery monitoring channel. +pub struct Vbat { + _0: (), +} + +/// Internal temperature sensor channel. +pub struct Temperature { + _0: (), +} + +/// Wrapper for safely sharing [`ADC_COMMON`](pac::ADC_COMMON) between `Adc`s. +#[derive(Clone, Copy)] +pub struct AdcCommon { + _0: PhantomData, + #[allow(unused)] + csr: AdcCommonCsr, + ccr: AdcCommonCcr, + #[allow(unused)] + cdr: AdcCommonCdr, +} + +#[derive(Clone, Copy)] +struct AdcCommonCsr { + _0: PhantomData>, +} + +#[derive(Clone, Copy)] +struct AdcCommonCcr { + _0: PhantomData>, +} + +#[derive(Clone, Copy)] +struct AdcCommonCdr { + _0: PhantomData>, +} + +impl AdcCommonCcr { + #[inline] + fn read(&self) -> pac::adc_common::ccr::R { + let adc_common = unsafe { &*pac::ADC_COMMON::ptr() }; + adc_common.ccr.read() + } + + #[inline] + fn modify(&mut self, f: F) + where + for<'w> F: FnOnce( + &pac::adc_common::ccr::R, + &'w mut pac::adc_common::ccr::W, + ) -> &'w mut stm32l4::W, + { + cortex_m::interrupt::free(|_| { + let adc_common = unsafe { &*pac::ADC_COMMON::ptr() }; + adc_common.ccr.modify(|r, w| f(r, w)) + }) + } +} + +impl AdcCommon { + /// Enable and reset [`ADC_COMMON`](pac::ADC_COMMON) peripheral. + pub fn new(adc_common: pac::ADC_COMMON, ahb: &mut AHB2) -> Self { + ::enable(ahb); + ::reset(ahb); + + drop(adc_common); + + Self { + _0: PhantomData, + csr: AdcCommonCsr { _0: PhantomData }, + ccr: AdcCommonCcr { _0: PhantomData }, + cdr: AdcCommonCdr { _0: PhantomData }, + } + } +} + +/// Analog to Digital converter interface +pub struct Adc { + adc: ADC, + adc_common: AdcCommon, + resolution: Resolution, + sample_time: SampleTime, + calibrated_vdda: u32, +} + +#[derive(Copy, Clone, PartialEq)] +pub enum DmaMode { + Disabled = 0, + Oneshot = 1, + // FIXME: Figure out how to get circular DMA to function properly (requires circbuffer?) + // Circular = 2, +} + +#[derive(PartialEq, PartialOrd, Clone, Copy)] +pub enum Sequence { + One = 0, + Two = 1, + Three = 2, + Four = 3, + Five = 4, + Six = 5, + Seven = 6, + Eight = 7, + Nine = 8, + Ten = 9, + Eleven = 10, + Twelve = 11, + Thirteen = 12, + Fourteen = 13, + Fifteen = 14, + Sixteen = 15, +} + +impl From for Sequence { + fn from(bits: u8) -> Self { + match bits { + 0 => Sequence::One, + 1 => Sequence::Two, + 2 => Sequence::Three, + 3 => Sequence::Four, + 4 => Sequence::Five, + 5 => Sequence::Six, + 6 => Sequence::Seven, + 7 => Sequence::Eight, + 8 => Sequence::Nine, + 9 => Sequence::Ten, + 10 => Sequence::Eleven, + 11 => Sequence::Twelve, + 12 => Sequence::Thirteen, + 13 => Sequence::Fourteen, + 14 => Sequence::Fifteen, + 15 => Sequence::Sixteen, + _ => unimplemented!(), + } + } +} + +impl Into for Sequence { + fn into(self) -> u8 { + match self { + Sequence::One => 0, + Sequence::Two => 1, + Sequence::Three => 2, + Sequence::Four => 3, + Sequence::Five => 4, + Sequence::Six => 5, + Sequence::Seven => 6, + Sequence::Eight => 7, + Sequence::Nine => 8, + Sequence::Ten => 9, + Sequence::Eleven => 10, + Sequence::Twelve => 11, + Sequence::Thirteen => 12, + Sequence::Fourteen => 13, + Sequence::Fifteen => 14, + Sequence::Sixteen => 15, + } + } +} + +#[derive(PartialEq, PartialOrd, Clone, Copy)] +pub enum Event { + EndOfRegularSequence, + EndOfRegularConversion, +} + +impl Adc { + /// Set the ADC resolution + pub fn set_resolution(&mut self, resolution: Resolution) { + self.resolution = resolution; + } + + /// Set the sample time + pub fn set_sample_time(&mut self, sample_time: SampleTime) { + self.sample_time = sample_time; + } + + /// Get the max value for the current resolution + pub fn get_max_value(&self) -> u16 { + match self.resolution { + Resolution::Bits12 => 4095, + Resolution::Bits10 => 1023, + Resolution::Bits8 => 255, + Resolution::Bits6 => 63, + } + } + + /// Release the ADC peripheral + /// + /// Drops `Adc` and returns the `(pac::ADC, pad::ADC_COMMON)` that it was wrapping, + /// giving the user full access to the peripheral. + pub fn release(self) -> ADC { + self.adc + } + + /// Convert a measurement to millivolts + pub fn to_millivolts(&self, sample: u16) -> u16 { + ((u32::from(sample) * self.calibrated_vdda) / self.resolution.to_max_count()) as u16 + } + + /// Convert a raw sample from the `Temperature` to deg C + pub fn to_degrees_centigrade(&self, sample: u16) -> f32 { + let sample = (u32::from(sample) * self.calibrated_vdda) / VDDA_CALIB_MV; + (VtempCalHigh::TEMP_DEGREES - VtempCalLow::TEMP_DEGREES) as f32 + // as signed because RM0351 doesn't specify against this being an + // inverse relation (which would result in a negative differential) + / (VtempCalHigh::get().read() as i32 - VtempCalLow::get().read() as i32) as f32 + // this can definitely be negative so must be done as a signed value + * (sample as i32 - VtempCalLow::get().read() as i32) as f32 + // while it would make sense for this to be `VtempCalLow::TEMP_DEGREES` (which is 30*C), + // the RM specifically uses 30*C so this will too + + 30.0 + } +} + +impl Adc { + // DMA channels: + // ADC1: DMA2_3 with C2S 0000 + // ADC2: DMA2_4 with C2S 0000 + // ADC1: DMA1_1 with C1S 0000 (implemented) + // ADC2: DMA1_2 with C1S 0000 +} + +impl OneShot for Adc +where + C: Channel, +{ + type Error = Infallible; + + fn read(&mut self, channel: &mut C) -> nb::Result { + self.configure_sequence(channel, Sequence::One, self.sample_time); + + self.start_conversion(); + while !self.has_completed_sequence() {} + + // Read ADC value first time and discard it, as per errata sheet. + // The errata state that if we do conversions slower than 1 kHz, the + // first read ADC value can be corrupted, so we discard it and measure again. + let _ = self.current_sample(); + + self.start_conversion(); + while !self.has_completed_sequence() {} + + // Read ADC value. + let val = self.current_sample(); + + // Disable ADC. + self.disable(); + + Ok(val) + } +} + +#[cfg(feature = "dma")] +impl TransferPayload for RxDma, dma1::C1> { + fn start(&mut self) { + self.channel.start(); + } + + fn stop(&mut self) { + self.channel.stop(); + } +} + +#[cfg(feature = "dma")] +impl RxDma, dma1::C1> { + pub fn split(mut self) -> (Adc, dma1::C1) { + self.stop(); + (self.payload, self.channel) + } +} + +#[cfg(feature = "dma")] +impl Transfer, dma1::C1>> +where + BUFFER: Sized + StableDeref + DerefMut + 'static, +{ + pub fn from_adc_dma( + dma: RxDma, dma1::C1>, + buffer: BUFFER, + dma_mode: DmaMode, + transfer_complete_interrupt: bool, + ) -> Self { + let (adc, channel) = dma.split(); + Transfer::from_adc(adc, channel, buffer, dma_mode, transfer_complete_interrupt) + } + + /// Initiate a new DMA transfer from an ADC. + /// + /// `dma_mode` indicates the desired mode for DMA. + /// + /// If `transfer_complete_interrupt` is true, the transfer + /// complete interrupt (= `DMA1_CH1`) will be enabled + pub fn from_adc( + mut adc: Adc, + mut channel: dma1::C1, + buffer: BUFFER, + dma_mode: DmaMode, + transfer_complete_interrupt: bool, + ) -> Self { + assert!(dma_mode != DmaMode::Disabled); + + let (enable, circular) = match dma_mode { + DmaMode::Disabled => (false, false), + DmaMode::Oneshot => (true, false), + }; + + adc.adc + .cfgr + .modify(|_, w| w.dmaen().bit(enable).dmacfg().bit(circular)); + + channel.set_peripheral_address(&adc.adc.dr as *const _ as u32, false); + + // SAFETY: since the length of BUFFER is known to be `N`, we are allowed + // to perform N transfers into said buffer + channel.set_memory_address(buffer.as_ptr() as u32, true); + channel.set_transfer_length(N as u16); + + channel.set_request_line(DmaInput::Adc1).unwrap(); + + channel.ccr().modify(|_, w| unsafe { + w.mem2mem() + .clear_bit() + // 00: Low, 01: Medium, 10: High, 11: Very high + .pl() + .bits(0b01) + // 00: 8-bits, 01: 16-bits, 10: 32-bits, 11: Reserved + .msize() + .bits(0b01) + // 00: 8-bits, 01: 16-bits, 10: 32-bits, 11: Reserved + .psize() + .bits(0b01) + // Peripheral -> Mem + .dir() + .clear_bit() + .circ() + .bit(circular) + }); + + if transfer_complete_interrupt { + channel.listen(DMAEvent::TransferComplete); + } + + atomic::compiler_fence(Ordering::Release); + + channel.start(); + adc.start_conversion(); + + Transfer::w( + buffer, + RxDma { + channel, + payload: adc, + }, + ) + } +} + +/// ADC resolution setting +/// +/// The default setting is 12 bits. +#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)] +pub enum Resolution { + /// 12-bit resolution + Bits12 = 0b00, + + /// 10-bit resolution + Bits10 = 0b01, + + /// 8-bit resolution + Bits8 = 0b10, + + /// 6-bit resolution + Bits6 = 0b11, +} + +impl Default for Resolution { + fn default() -> Self { + Self::Bits12 + } +} + +impl Resolution { + fn to_max_count(&self) -> u32 { + match self { + Resolution::Bits12 => (1 << 12) - 1, + Resolution::Bits10 => (1 << 10) - 1, + Resolution::Bits8 => (1 << 8) - 1, + Resolution::Bits6 => (1 << 6) - 1, + } + } +} + +/// ADC sample time +/// +/// The default setting is 2.5 ADC clock cycles. +#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)] +#[repr(u8)] +pub enum SampleTime { + /// 2.5 ADC clock cycles + Cycles2_5 = 0b000, + + /// 6.5 ADC clock cycles + Cycles6_5 = 0b001, + + /// 12.5 ADC clock cycles + Cycles12_5 = 0b010, + + /// 24.5 ADC clock cycles + Cycles24_5 = 0b011, + + /// 47.5 ADC clock cycles + Cycles47_5 = 0b100, + + /// 92.5 ADC clock cycles + Cycles92_5 = 0b101, + + /// 247.5 ADC clock cycles + Cycles247_5 = 0b110, + + /// 640.5 ADC clock cycles + Cycles640_5 = 0b111, +} + +impl Default for SampleTime { + fn default() -> Self { + Self::Cycles2_5 + } +} + +/// Implemented for all types that represent ADC channels +pub trait Channel: EmbeddedHalChannel { + fn set_sample_time(&mut self, adc: &mut T, sample_time: SampleTime); +} + +macro_rules! impl_embedded_hal_channel { + ($pin:ty => ($adc_type:ident, $chan:expr)) => { + impl EmbeddedHalChannel for $pin { + type ID = u8; + + fn channel() -> Self::ID { + $chan + } + } + }; +} + +macro_rules! impl_channel { + ($pin:ty => ($adc_type:ident, $smpr:ident, $smp:ident, $($min_sample_time:expr)?)) => { + impl Channel for $pin { + #[inline] + fn set_sample_time(&mut self, adc: &mut pac::$adc_type, sample_time: SampleTime) { + $( + // Ensure minimum sample time. + let sample_time = if sample_time < $min_sample_time { + $min_sample_time + } else { + sample_time + }; + )* + + adc.$smpr.modify(|_, w| { + // This is sound, as all `SampleTime` values are valid for this field. + unsafe { w.$smp().bits(sample_time as u8) } + }) + } + } + }; +} + +macro_rules! adc_pins { + ($($pin:ty => ($adc_type:ident, $chan:expr, $smpr:ident, $smp:ident $(, $min_sample_time:expr)?),)+ $(,)?) => { + $( + impl_embedded_hal_channel!($pin => ($adc_type, $chan)); + impl_channel!($pin =>($adc_type, $smpr, $smp, $($min_sample_time)*)); + )* + }; +} + +macro_rules! adc { + (@vref: $adc_type:ident => ($common_type:ident)) => { + /// Calculates the system VDDA by sampling the internal VREF channel and comparing + /// the result with the value stored at the factory. If the chip's VDDA is not stable, run + /// this before each ADC conversion. + /// + /// Returns the calibrated VDDA voltage in millivolts. + #[inline] + pub fn calibrate(&mut self, delay: &mut impl DelayUs) -> u16 { + let vref = self.enable_vref(delay); + + let vref_cal = VrefCal::get().read(); + + // This can't actually fail, it's just in a result to satisfy hal trait + let vref_samp = self.read(&mut Vref { _0: () }).unwrap(); + + // Safety: DIV by 0 is possible if vref_samp is 0 + self.calibrated_vdda = (VDDA_CALIB_MV * u32::from(vref_cal)) / u32::from(vref_samp); + + // Disable VREF again if it was disabled before. + if let Some(vref) = vref { + self.disable_vref(vref); + } + + self.calibrated_vdda as u16 + } + + /// Check if the internal voltage reference channel is enabled. + #[inline] + pub fn is_vref_enabled(&self) -> bool { + self.adc_common.ccr.read().vrefen().bit_is_set() + } + + /// Enable the internal voltage reference channel. + /// + /// Returns `Some(Vref)` if the channel was enabled or `None` if it was already enabled before. + #[inline] + pub fn enable_vref(&mut self, delay: &mut impl DelayUs) -> Option { + if self.is_vref_enabled() { + return None + } + + self.adc_common.ccr.modify(|_, w| w.vrefen().set_bit()); + + // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us + // to stabilize the internal voltage reference, we wait a little more. + delay.delay_us(15); + + Some(Vref { _0: () }) + } + + /// Disable the internal voltage reference channel. + #[inline] + pub fn disable_vref(&mut self, vref: Vref) { + drop(vref); + + self.adc_common.ccr.modify(|_, w| w.vrefen().clear_bit()); + } + }; + + // Provide a stub implementation for ADCs that do not have a means of sampling VREF. + (@no_vref: $adc_type:ident => ($common_type:ident)) => { + #[inline] + fn calibrate(&mut self, _delay: &mut impl DelayUs) {} + }; + + (@vbat: $adc_type:ident => ($common_type:ident)) => { + /// Check if the battery voltage monitoring channel is enabled. + #[inline] + pub fn is_vbat_enabled(&self) -> bool { + self.adc_common.ccr.read().ch18sel().bit_is_set() + } + + /// Enable the battery voltage monitoring channel. + /// + /// + /// Returns `Some(Vbat)` if the channel was enabled or `None` if it was already enabled before. + #[inline] + pub fn enable_vbat(&mut self) -> Option { + if self.is_vbat_enabled() { + return None + } + + self.adc_common.ccr.modify(|_, w| w.ch18sel().set_bit()); + Some(Vbat { _0: () }) + } + + /// Disable the battery voltage monitoring channel. + #[inline] + pub fn disable_vbat(&mut self, vbat: Vbat) { + drop(vbat); + + self.adc_common.ccr.modify(|_, w| w.ch18sel().clear_bit()); + } + }; + + (@no_vbat: $adc_type:ident => ($common_type:ident)) => { + + }; + + (@vts: $adc_type:ident => ($common_type:ident)) => { + /// Check if the internal temperature sensor channel is enabled. + pub fn is_temperature_enabled(&self) -> bool { + self.adc_common.ccr.read().ch17sel().bit_is_set() + } + + /// Enable the internal temperature sensor channel. + /// + /// Returns `Some(Temperature)` if the channel was enabled or `None` if it was already enabled before. + pub fn enable_temperature(&mut self, delay: &mut impl DelayUs) -> Option { + if self.is_temperature_enabled() { + return None + } + + self.adc_common.ccr.modify(|_, w| w.ch17sel().set_bit()); + + // FIXME: This note from the reference manual is currently not possible + // rm0351 section 18.4.32 pg580 (L47/L48/L49/L4A models) + // Note: + // The sensor has a startup time after waking from power-down mode before it can output VTS + // at the correct level. The ADC also has a startup time after power-on, so to minimize the + // delay, the ADEN and CH17SEL bits should be set at the same time. + // + // https://github.com/STMicroelectronics/STM32CubeL4/blob/master/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h#L1363 + // 120us is used in the ST HAL code + delay.delay_us(150); + + Some(Temperature { _0: () }) + } + + /// Disable the internal temperature sensor channel. + pub fn disable_temperature(&mut self, temperature: Temperature) { + drop(temperature); + + self.adc_common.ccr.modify(|_, w| w.ch17sel().clear_bit()) + } + }; + + (@no_vts: $adc_type:ident => ($common_type:ident)) => { + + }; + + // ADC1 supports VREF, VBAT and VTS. + (@additionals: ADC1 => ($common_type:ident)) => { + adc!(@vref: ADC1 => ($common_type)); + adc!(@vbat: ADC1 => ($common_type)); + adc!(@vts: ADC1 => ($common_type)); + }; + + // ADC3 supports VBAT and VTS. + (@additionals: ADC3 => ($common_type:ident)) => { + adc!(@no_vref: ADC3 => ($common_type)); + adc!(@vbat: ADC3 => ($common_type)); + adc!(@vts: ADC3 => ($common_type)); + }; + + (@additionals: $adc_type:ident => ($common_type:ident)) => { + adc!(@no_vref: $adc_type => ($common_type)); + adc!(@no_vbat: $adc_type => ($common_type)); + adc!(@no_vts: $adc_type => ($common_type)); + }; + + ($($adc_type:ident => ($constructor_fn_name:ident, $common_type:ident)),+ $(,)?) => { + $( + impl Adc { + /// Enable the ADC clock and runs calibration. + pub fn $constructor_fn_name( + adc: pac::$adc_type, + adc_common: AdcCommon, + ccipr: &mut CCIPR, + delay: &mut impl DelayUs, + ) -> Self { + // Select system clock as ADC clock source + ccipr.ccipr().modify(|_, w| w.adcsel().sysclk()); + + // Initialize the ADC, according to the STM32L4xx Reference Manual, + // section 16.4.6. + adc.cr.write(|w| w.deeppwd().clear_bit()); // exit deep-power-down mode + adc.cr.modify(|_, w| w.advregen().set_bit()); // enable internal voltage regulator + + // According to the STM32L4xx Reference Manual, section 16.4.6, we need + // to wait for T_ADCVREG_STUP after enabling the internal voltage + // regulator. For the STM32L433, this is 20 us. We choose 25 us to + // account for bad clocks. + delay.delay_us(25); + + // Calibration procedure according to section 16.4.8. + adc.cr.modify(|_, w| { + w.adcal().set_bit(); // start calibration + w.adcaldif().clear_bit(); // single-ended mode + + w + }); + + while adc.cr.read().adcal().bit_is_set() {} + + // We need to wait 4 ADC clock after ADCAL goes low, 1 us is more than enough + delay.delay_us(1); + + let mut s = Self { + adc, + adc_common, + resolution: Resolution::default(), + sample_time: SampleTime::default(), + calibrated_vdda: VDDA_CALIB_MV, + }; + + s.calibrate(delay); + + s + } + + adc!(@additionals: $adc_type => ($common_type)); + + /// Check if the ADC is enabled. + #[inline] + pub fn is_enabled(&self) -> bool { + self.adc.cr.read().aden().bit_is_set() + } + + /// Enable the ADC. + #[inline] + pub fn enable(&mut self) { + if !self.is_enabled() { + // Make sure bits are off + while self.adc.cr.read().addis().bit_is_set() {} + + // Clear ADRDY by setting it (See Reference Manual section 1.16.1) + self.adc.isr.modify(|_, w| w.adrdy().set_bit()); + self.adc.cr.modify(|_, w| w.aden().set_bit()); + while self.adc.isr.read().adrdy().bit_is_clear() {} + + // Configure ADC + self.adc.cfgr.modify(|_, w| { + // This is sound, as all `Resolution` values are valid for this + // field. + unsafe { w.res().bits(self.resolution as u8) } + }); + } + } + + /// Disable the ADC. + #[inline] + pub fn disable(&mut self) { + self.adc.cr.modify(|_, w| w.addis().set_bit()); + } + + /// Returns the current sample stored in the ADC data register. + #[inline] + pub fn current_sample(&self) -> u16 { + // Sound, as bits 31:16 are reserved, read-only and 0 in ADC_DR + // TODO: Switch to using `rdata` once https://github.com/stm32-rs/stm32-rs/pull/723 is released. + self.adc.dr.read().bits() as u16 + } + + /// Configure the channel for a specific step in the sequence. + /// + /// Automatically sets the sequence length to the farthes sequence + /// index that has been used so far. Use [`Adc::reset_sequence`] to + /// reset the sequence length. + pub fn configure_sequence( + &mut self, + channel: &mut C, + sequence: Sequence, + sample_time: SampleTime, + ) where + C: Channel, + { + let channel_bits = C::channel(); + channel.set_sample_time(&mut self.adc, sample_time); + + unsafe { + // This is sound as channel() always returns a valid channel number + match sequence { + Sequence::One => self.adc.sqr1.modify(|_, w| w.sq1().bits(channel_bits)), + Sequence::Two => self.adc.sqr1.modify(|_, w| w.sq2().bits(channel_bits)), + Sequence::Three => self.adc.sqr1.modify(|_, w| w.sq3().bits(channel_bits)), + Sequence::Four => self.adc.sqr1.modify(|_, w| w.sq4().bits(channel_bits)), + Sequence::Five => self.adc.sqr2.modify(|_, w| w.sq5().bits(channel_bits)), + Sequence::Six => self.adc.sqr2.modify(|_, w| w.sq6().bits(channel_bits)), + Sequence::Seven => self.adc.sqr2.modify(|_, w| w.sq7().bits(channel_bits)), + Sequence::Eight => self.adc.sqr2.modify(|_, w| w.sq8().bits(channel_bits)), + Sequence::Nine => self.adc.sqr2.modify(|_, w| w.sq9().bits(channel_bits)), + Sequence::Ten => self.adc.sqr3.modify(|_, w| w.sq10().bits(channel_bits)), + Sequence::Eleven => self.adc.sqr3.modify(|_, w| w.sq11().bits(channel_bits)), + Sequence::Twelve => self.adc.sqr3.modify(|_, w| w.sq12().bits(channel_bits)), + Sequence::Thirteen => self.adc.sqr3.modify(|_, w| w.sq13().bits(channel_bits)), + Sequence::Fourteen => self.adc.sqr3.modify(|_, w| w.sq14().bits(channel_bits)), + Sequence::Fifteen => self.adc.sqr4.modify(|_, w| w.sq15().bits(channel_bits)), + Sequence::Sixteen => self.adc.sqr4.modify(|_, w| w.sq16().bits(channel_bits)), + } + } + + // This will only ever extend the sequence, not shrink it. + let current_seql = self.get_sequence_length(); + let next_seql: u8 = sequence.into(); + if next_seql >= current_seql { + // Note: sequence length of 0 = 1 conversion + self.set_sequence_length(sequence.into()); + } + } + + /// Get the configured sequence length (= `actual sequence length - 1`) + #[inline] + pub(crate) fn get_sequence_length(&self) -> u8 { + self.adc.sqr1.read().l().bits() + } + + /// Private: length must be `actual sequence length - 1`, so not API-friendly. + /// Use [`Adc::reset_sequence`] and [`Adc::configure_sequence`] instead + #[inline] + fn set_sequence_length(&mut self, length: u8) { + self.adc.sqr1.modify(|_, w| unsafe { w.l().bits(length) }); + } + + /// Reset the sequence length to 1 + /// + /// Does *not* erase previously configured sequence settings, only + /// changes the sequence length + #[inline] + pub fn reset_sequence(&mut self) { + self.adc.sqr1.modify(|_, w| unsafe { w.l().bits(0b0000) }) + } + + #[inline] + pub fn has_completed_conversion(&self) -> bool { + self.adc.isr.read().eoc().bit_is_set() + } + + #[inline] + pub fn has_completed_sequence(&self) -> bool { + self.adc.isr.read().eos().bit_is_set() + } + + #[inline] + pub fn clear_end_flags(&mut self) { + // EOS and EOC are reset by setting them (See reference manual section 16.6.1) + self.adc + .isr + .modify(|_, w| w.eos().set_bit().eoc().set_bit()); + } + + #[inline] + pub fn start_conversion(&mut self) { + self.enable(); + self.clear_end_flags(); + self.adc.cr.modify(|_, w| w.adstart().set_bit()); + } + + #[inline] + pub fn is_converting(&self) -> bool { + self.adc.cr.read().adstart().bit_is_set() + } + + #[inline] + pub fn listen(&mut self, event: Event) { + self.adc.ier.modify(|_, w| match event { + Event::EndOfRegularSequence => w.eosie().set_bit(), + Event::EndOfRegularConversion => w.eocie().set_bit(), + }); + } + + #[inline] + pub fn unlisten(&mut self, event: Event) { + self.adc.ier.modify(|_, w| match event { + Event::EndOfRegularSequence => w.eosie().clear_bit(), + Event::EndOfRegularConversion => w.eocie().clear_bit(), + }); + } + } + )* + }; +} + +adc!(ADC1 => (adc1, ADC_COMMON)); + +adc_pins!( + // “Table 25. Embedded internal voltage reference” in the STM32L496xx datasheet states that + // the sample time needs to be at least 4 us. With 640.5 ADC cycles at 80 MHz, we have a + // minimum of 8 us, leaving some headroom. + Vref => (ADC1, 0, smpr1, smp0, SampleTime::Cycles640_5), + gpio::PC0 => (ADC1, 1, smpr1, smp1), + gpio::PC1 => (ADC1, 2, smpr1, smp2), + gpio::PC2 => (ADC1, 3, smpr1, smp3), + gpio::PC3 => (ADC1, 4, smpr1, smp4), + gpio::PA0 => (ADC1, 5, smpr1, smp5), + gpio::PA1 => (ADC1, 6, smpr1, smp6), + gpio::PA2 => (ADC1, 7, smpr1, smp7), + gpio::PA3 => (ADC1, 8, smpr1, smp8), + gpio::PA4 => (ADC1, 9, smpr1, smp9), + gpio::PA5 => (ADC1, 10, smpr2, smp10), + gpio::PA6 => (ADC1, 11, smpr2, smp11), + gpio::PA7 => (ADC1, 12, smpr2, smp12), + gpio::PC4 => (ADC1, 13, smpr2, smp13), + gpio::PC5 => (ADC1, 14, smpr2, smp14), + gpio::PB0 => (ADC1, 15, smpr2, smp15), + gpio::PB1 => (ADC1, 16, smpr2, smp16), + Temperature => (ADC1, 17, smpr2, smp17), + Vbat => (ADC1, 18, smpr2, smp18), +); + +#[cfg(not(any( + feature = "stm32l433", + feature = "stm32l443", + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +)))] +adc!(ADC2 => (adc2, ADC_COMMON)); + +#[cfg(not(any( + feature = "stm32l433", + feature = "stm32l443", + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +)))] +adc_pins!( + gpio::PC0 => (ADC2, 1, smpr1, smp1), + gpio::PC1 => (ADC2, 2, smpr1, smp2), + gpio::PC2 => (ADC2, 3, smpr1, smp3), + gpio::PC3 => (ADC2, 4, smpr1, smp4), + gpio::PA0 => (ADC2, 5, smpr1, smp5), + gpio::PA1 => (ADC2, 6, smpr1, smp6), + gpio::PA2 => (ADC2, 7, smpr1, smp7), + gpio::PA3 => (ADC2, 8, smpr1, smp8), + gpio::PA4 => (ADC2, 9, smpr1, smp9), + gpio::PA5 => (ADC2, 10, smpr2, smp10), + gpio::PA6 => (ADC2, 11, smpr2, smp11), + gpio::PA7 => (ADC2, 12, smpr2, smp12), + gpio::PC4 => (ADC2, 13, smpr2, smp13), + gpio::PC5 => (ADC2, 14, smpr2, smp14), + gpio::PB0 => (ADC2, 15, smpr2, smp15), + gpio::PB1 => (ADC2, 16, smpr2, smp16), + // DAC1 => (ADC2, 17, smpr2, smp17), + // DAC2 => (ADC2, 18, smpr2, smp18), +); + +#[cfg(any( + feature = "stm32l476", + feature = "stm32l486", + feature = "stm32l496", + feature = "stm32l4a6", +))] +adc!(ADC3 => (adc3, ADC_COMMON)); + +#[cfg(any( + feature = "stm32l476", + feature = "stm32l486", + feature = "stm32l496", + feature = "stm32l4a6", +))] +adc_pins!( + gpio::PC0 => (ADC3, 1, smpr1, smp1), + gpio::PC1 => (ADC3, 2, smpr1, smp2), + gpio::PC2 => (ADC3, 3, smpr1, smp3), + gpio::PC3 => (ADC3, 4, smpr1, smp4), + gpio::PF3 => (ADC3, 6, smpr1, smp6), + gpio::PF4 => (ADC3, 7, smpr1, smp7), + gpio::PF5 => (ADC3, 8, smpr1, smp8), + gpio::PF6 => (ADC3, 9, smpr1, smp9), + gpio::PF7 => (ADC3, 10, smpr2, smp10), + gpio::PF8 => (ADC3, 11, smpr2, smp11), + gpio::PF9 => (ADC3, 12, smpr2, smp12), + gpio::PF10 => (ADC3, 13, smpr2, smp13), + // DAC1 => (ADC2, 14, smpr2, smp14), + // DAC2 => (ADC2, 15, smpr2, smp15), + Temperature => (ADC3, 17, smpr2, smp17), + Vbat => (ADC3, 18, smpr2, smp18), +); diff --git a/src/can.rs b/src/can.rs index 44034f24..d06c8755 100644 --- a/src/can.rs +++ b/src/can.rs @@ -2,7 +2,7 @@ //! use crate::gpio::{self, NoPin}; -use crate::pac::{CAN1, CAN2}; +use crate::pac; use crate::rcc; pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + gpio::alt::CanCommon {} @@ -16,22 +16,22 @@ macro_rules! can { } // Implemented by all SPI instances -can! { CAN1: Can1 } -can! { CAN2: Can2 } +can! { pac::CAN1: Can1 } +#[cfg(feature = "can2")] +can! { pac::CAN2: Can2 } #[cfg(feature = "can3")] -can! { crate::pac::CAN3: Can3 } +can! { pac::CAN3: Can3 } /// Pins and definitions for models with a third CAN peripheral #[cfg(feature = "can3")] mod can3 { use super::*; - use crate::pac::CAN3; - unsafe impl bxcan::Instance for Can { - const REGISTERS: *mut bxcan::RegisterBlock = CAN3::ptr() as *mut _; + unsafe impl bxcan::Instance for Can { + const REGISTERS: *mut bxcan::RegisterBlock = pac::CAN3::ptr() as *mut _; } - unsafe impl bxcan::FilterOwner for Can { + unsafe impl bxcan::FilterOwner for Can { const NUM_FILTER_BANKS: u8 = 14; } } @@ -110,16 +110,20 @@ impl Can { } } -unsafe impl bxcan::Instance for Can { - const REGISTERS: *mut bxcan::RegisterBlock = CAN1::ptr() as *mut _; +unsafe impl bxcan::Instance for Can { + const REGISTERS: *mut bxcan::RegisterBlock = pac::CAN1::ptr() as *mut _; } -unsafe impl bxcan::Instance for Can { - const REGISTERS: *mut bxcan::RegisterBlock = CAN2::ptr() as *mut _; +#[cfg(feature = "can2")] +unsafe impl bxcan::Instance for Can { + const REGISTERS: *mut bxcan::RegisterBlock = pac::CAN2::ptr() as *mut _; } -unsafe impl bxcan::FilterOwner for Can { +unsafe impl bxcan::FilterOwner for Can { + #[cfg(any(feature = "f4", feature = "f7"))] const NUM_FILTER_BANKS: u8 = 28; + #[cfg(feature = "l4")] + const NUM_FILTER_BANKS: u8 = 14; } -unsafe impl bxcan::MasterInstance for Can {} +unsafe impl bxcan::MasterInstance for Can {} diff --git a/src/crc_l4.rs b/src/crc_l4.rs new file mode 100644 index 00000000..e62fb53c --- /dev/null +++ b/src/crc_l4.rs @@ -0,0 +1,205 @@ +//! CRC calculation unit +//! +//! Usage example: +//! ``` +//! let crc = dp.CRC.constrain(&mut rcc.ahb1); +//! +//! // Lets use the CRC-16-CCITT polynomial +//! let mut crc = crc.polynomial(crc::Polynomial::L16(0x1021)).freeze(); +//! +//! let data = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]; +//! crc.feed(&data); +//! +//! let result = crc.result(); +//! assert!(result == 0x78cb); +//! ``` + +#![deny(missing_docs)] + +use crate::pac::CRC; +use crate::rcc::{self, Enable}; +use core::hash::Hasher; + +/// Extension trait to constrain the CRC peripheral. +pub trait CrcExt { + /// Constrains the CRC peripheral to play nicely with the other abstractions + fn constrain(self, ahb1: &mut rcc::AHB1) -> Config; +} + +impl CrcExt for CRC { + fn constrain(self, ahb1: &mut rcc::AHB1) -> Config { + // Enable power to CRC unit + CRC::enable(ahb1); + + // Default values + Config { + initial_value: 0xffff_ffff, + polynomial: Polynomial::L32(0x04c1_1db7), + input_bit_reversal: None, + output_bit_reversal: false, + } + } +} + +/// Polynomial settings. +pub enum Polynomial { + /// 7-bit polynomial, only the lowest 7 bits are valid + L7(u8), + /// 8-bit polynomial + L8(u8), + /// 16-bit polynomial + L16(u16), + /// 32-bit polynomial + L32(u32), +} + +/// Bit reversal settings. +pub enum BitReversal { + /// Reverse bits by byte + ByByte, + /// Reverse bits by half-word + ByHalfWord, + /// Reverse bits by word + ByWord, +} + +/// CRC configuration structure, uses builder pattern. +pub struct Config { + initial_value: u32, + polynomial: Polynomial, + input_bit_reversal: Option, + output_bit_reversal: bool, +} + +impl Config { + /// Sets the initial value of the CRC. + pub fn initial_value(mut self, init: u32) -> Self { + self.initial_value = init; + + self + } + + /// Sets the polynomial of the CRC. + pub fn polynomial(mut self, polynomial: Polynomial) -> Self { + self.polynomial = polynomial; + + self + } + + /// Enables bit reversal of the inputs. + pub fn input_bit_reversal(mut self, rev: BitReversal) -> Self { + self.input_bit_reversal = Some(rev); + + self + } + + /// Enables bit reversal of the outputs. + pub fn output_bit_reversal(mut self, rev: bool) -> Self { + self.output_bit_reversal = rev; + + self + } + + /// Freezes the peripheral, making the configuration take effect. + pub fn freeze(self) -> Crc { + let crc = unsafe { &(*CRC::ptr()) }; + + let (poly, poly_bits, init) = match self.polynomial { + Polynomial::L7(val) => ((val & 0x7f) as u32, 0b11, self.initial_value & 0x7f), + Polynomial::L8(val) => (val as u32, 0b10, self.initial_value & 0xff), + Polynomial::L16(val) => (val as u32, 0b01, self.initial_value & 0xffff), + Polynomial::L32(val) => (val, 0b00, self.initial_value), + }; + + let in_rev_bits = match self.input_bit_reversal { + None => 0b00, + Some(BitReversal::ByByte) => 0b01, + Some(BitReversal::ByHalfWord) => 0b10, + Some(BitReversal::ByWord) => 0b11, + }; + + crc.init.write(|w| w.init().bits(init)); + crc.pol.write(|w| w.bits(poly)); + crc.cr.write(|w| { + w.rev_in().bits(in_rev_bits); + w.polysize().bits(poly_bits); + w.reset().set_bit(); + + if self.output_bit_reversal { + w.rev_out().set_bit() + } else { + w.rev_out().clear_bit() + } + }); + + Crc {} + } +} + +/// Constrained CRC peripheral. +pub struct Crc {} + +impl Crc { + /// This will reset the CRC to its initial condition. + #[inline] + pub fn reset(&mut self) { + let crc = unsafe { &(*CRC::ptr()) }; + + crc.cr.modify(|_, w| w.reset().set_bit()); + } + + /// This will reset the CRC to its initial condition, however with a specific initial value. + /// This is very useful if many task are sharing the CRC peripheral, as one can read out the + /// intermediate result, store it until the next time a task runs, and initialize with the + /// intermediate result to continue where the task left off. + #[inline] + pub fn reset_with_inital_value(&mut self, initial_value: u32) { + let crc = unsafe { &(*CRC::ptr()) }; + + crc.init.write(|w| w.init().bits(initial_value)); + crc.cr.modify(|_, w| w.reset().set_bit()); + } + + /// Feed the CRC with data + #[inline] + pub fn feed(&mut self, data: &[u8]) { + let crc = unsafe { &(*CRC::ptr()) }; + for &byte in data { + crc.dr8().write(|w| w.dr8().bits(byte)); + } + } + + /// Get the result of the CRC, depending on the polynomial chosen only a certain amount of the + /// bits are the result. This will reset the CRC peripheral after use. + #[inline] + pub fn result(&mut self) -> u32 { + let ret = self.peek_result(); + + self.reset(); + + ret + } + + /// Get a peed at the result of the CRC, depending on the polynomial chosen only a certain + /// amount of the bits are the result. + #[inline] + pub fn peek_result(&self) -> u32 { + let crc = unsafe { &(*CRC::ptr()) }; + + crc.dr().read().bits() + } +} + +impl Hasher for Crc { + #[inline] + fn finish(&self) -> u64 { + // `peek_result` as `core::hash::Hasher` required that the `finish` method does not reset + // the hasher. + self.peek_result() as u64 + } + + #[inline] + fn write(&mut self, data: &[u8]) { + self.feed(data); + } +} diff --git a/src/dma/traits.rs b/src/dma/traits.rs index 1d74e5f6..29c62f19 100644 --- a/src/dma/traits.rs +++ b/src/dma/traits.rs @@ -282,6 +282,7 @@ pub unsafe trait PeriAddress { } // Convenience macro for implementing addresses on peripherals +#[allow(unused)] macro_rules! address { ($(($peripheral:ty, $register:ident, $size: ty)),+ $(,)*) => { $( @@ -296,6 +297,7 @@ macro_rules! address { )+ }; } +#[allow(unused)] use address; /// Type alias to a DMA RegisterBlock. @@ -349,7 +351,109 @@ macro_rules! dma_map { } use dma_map; +/* +#[cfg(feature = "c0")] +mod c0; +#[allow(unused)] +#[cfg(feature = "c0")] +pub use c0::*; + +#[cfg(feature = "f0")] +mod f0; +#[allow(unused)] +#[cfg(feature = "f0")] +pub use f0::*; + +#[cfg(feature = "f2")] +mod f2; +#[allow(unused)] +#[cfg(feature = "f2")] +pub use f2::*; + +#[cfg(feature = "f3")] +mod f3; +#[allow(unused)] +#[cfg(feature = "f3")] +pub use f3::*; +*/ +#[cfg(feature = "f4")] mod f4; +#[allow(unused)] +#[cfg(feature = "f4")] +pub use f4::*; + +#[cfg(feature = "f7")] +mod f7; +#[allow(unused)] +#[cfg(feature = "f7")] +pub use f7::*; +/* +#[cfg(feature = "g0")] +mod g0; +#[allow(unused)] +#[cfg(feature = "g0")] +pub use g0::*; +*/ +#[cfg(feature = "g4")] +mod g4; +#[allow(unused)] +#[cfg(feature = "g4")] +pub use g4::*; +/* +#[cfg(feature = "h7")] +mod h7; +#[allow(unused)] +#[cfg(feature = "h7")] +pub use h7::*; + +#[cfg(feature = "l0")] +mod l0; +#[allow(unused)] +#[cfg(feature = "l0")] +pub use l0::*; + +#[cfg(feature = "l1")] +mod l1; +#[allow(unused)] +#[cfg(feature = "l1")] +pub use l1::*; +*/ +#[cfg(feature = "l4x")] +mod l4; +#[allow(unused)] +#[cfg(feature = "l4x")] +pub use l4::*; +/* +#[cfg(feature = "l4p")] +mod l4p; +#[allow(unused)] +#[cfg(feature = "l4p")] +pub use l4p::*; + +#[cfg(feature = "l5")] +mod l5; +#[allow(unused)] +#[cfg(feature = "l5")] +pub use l5::*; + +#[cfg(feature = "u5")] +mod u5; +#[allow(unused)] +#[cfg(feature = "u5")] +pub use u5::*; + +#[cfg(feature = "wl")] +mod wl; +#[allow(unused)] +#[cfg(feature = "wl")] +pub use wl::*; + +#[cfg(feature = "wb")] +mod wb; +#[allow(unused)] +#[cfg(feature = "wb")] +pub use wb::*; +*/ #[cfg(feature = "dfsdm")] pub struct FLT { diff --git a/src/dma/traits/f2.rs b/src/dma/traits/f2.rs new file mode 100644 index 00000000..73e176ed --- /dev/null +++ b/src/dma/traits/f2.rs @@ -0,0 +1,119 @@ +use super::*; + +dma_map! { + (Stream0:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX + (Stream2:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX + (Stream3:0, pac::SPI2, [PeripheralToMemory]), //SPI2_RX + (Stream4:0, pac::SPI2, [MemoryToPeripheral]), //SPI2_TX + (Stream5:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX + (Stream7:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX + + (Stream0:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX + (Stream2:1, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP + (Stream4:1, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP + (Stream5:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX + (Stream6:1, pac::I2C1, [MemoryToPeripheral]), //I2C1_TX + (Stream7:1, pac::I2C1, [MemoryToPeripheral]), //I2C1_TX + + (Stream0:2, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1 + (Stream3:2, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2 + (Stream6:2, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP + (Stream7:2, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3 + + (Stream1:3, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3 + (Stream1:3, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP + (Stream2:3, pac::I2C3, [PeripheralToMemory]), //I2C3_RX + (Stream4:3, pac::I2C3, [MemoryToPeripheral]), //I2C3_TX + (Stream5:3, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1 + (Stream6:3, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2 + (Stream6:3, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4 + (Stream7:3, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4 + (Stream7:3, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP + + (Stream0:4, pac::UART5, [PeripheralToMemory]), //UART5_RX + (Stream1:4, pac::USART3, [PeripheralToMemory]), //USART3_RX + (Stream2:4, pac::UART4, [PeripheralToMemory]), //UART4_RX + (Stream3:4, pac::USART3, [MemoryToPeripheral]), //USART3_TX + (Stream4:4, pac::UART4, [MemoryToPeripheral]), //UART4_TX + (Stream5:4, pac::USART2, [PeripheralToMemory]), //USART2_RX + (Stream6:4, pac::USART2, [MemoryToPeripheral]), //USART2_TX + (Stream7:4, pac::UART5, [MemoryToPeripheral]), //UART5_TX + + (Stream2:5, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4 + (Stream2:5, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_UP + (Stream4:5, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1 + (Stream4:5, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG + (Stream5:5, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2 + (Stream7:5, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3 + + (Stream0:6, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3/UP + (Stream0:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3/UP + (Stream1:6, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG + (Stream1:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG + (Stream2:6, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH1 + (Stream3:6, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4/TRIG + (Stream3:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_TRIG + (Stream4:6, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH2 + (Stream6:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP + + (Stream1:7, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP + (Stream2:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX + (Stream3:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX + (Stream4:7, pac::USART3, [MemoryToPeripheral]), //USART3_TX:DMA_CHANNEL_7 + (Stream5:7, pac::DAC, [MemoryToPeripheral]), //DAC1 + //(Stream6:7, pac::DAC2, [MemoryToPeripheral]), //DAC2 + (Stream7:7, pac::I2C2, [MemoryToPeripheral]), //I2C2_TX + + (Stream0:0, pac::ADC1, [PeripheralToMemory]), //ADC1 + (Stream2:0, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1 + (Stream2:0, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2 + (Stream2:0, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3 + (Stream4:0, pac::ADC1, [PeripheralToMemory]), //ADC1 + (Stream6:0, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1 + (Stream6:0, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2 + (Stream6:0, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3 + + (Stream1:1, pac::DCMI, [PeripheralToMemory]), //DCMI + (Stream2:1, pac::ADC2, [PeripheralToMemory]), //ADC2 + (Stream3:1, pac::ADC2, [PeripheralToMemory]), //ADC2 + (Stream7:1, pac::DCMI, [PeripheralToMemory]), //DCMI + + (Stream0:2, pac::ADC3, [PeripheralToMemory]), //ADC3 + (Stream1:2, pac::ADC3, [PeripheralToMemory]), //ADC3 + //(Stream7:2, pac::HASH_IN, [MemoryToPeripheral]), //HASH_IN + (Stream0:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX + (Stream2:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX + (Stream3:3, pac::SPI1, [MemoryToPeripheral]), //SPI1_TX + (Stream5:3, pac::SPI1, [MemoryToPeripheral]), //SPI1_TX + + (Stream2:4, pac::USART1, [PeripheralToMemory]), //USART1_RX + (Stream3:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO + (Stream5:4, pac::USART1, [PeripheralToMemory]), //USART1_RX + (Stream6:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO + (Stream7:4, pac::USART1, [MemoryToPeripheral]), //USART1_TX + + (Stream1:5, pac::USART6, [PeripheralToMemory]), //USART6_RX + (Stream2:5, pac::USART6, [PeripheralToMemory]), //USART6_RX + (Stream6:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX + (Stream7:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX + (Stream0:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG + (Stream1:6, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1 + (Stream2:6, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2 + (Stream3:6, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1 + (Stream4:6, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4/TRIG/COM + (Stream4:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4/TRIG/COM + (Stream5:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP + (Stream6:6, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3 + (Stream1:7, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_UP + (Stream2:7, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1 + (Stream3:7, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2 + (Stream4:7, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3 + (Stream7:7, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH4 + (Stream7:7, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_TRIG/COM +} + +#[cfg(feature = "cryp")] +dma_map! { + (Stream5:2, pac::CRYP_OUT, [PeripheralToMemory]), //CRYP_OUT + (Stream6:2, pac::CRYP_IN, [MemoryToPeripheral]), //CRYP_IN +} diff --git a/src/dma/traits/f7.rs b/src/dma/traits/f7.rs new file mode 100644 index 00000000..b3f9c4a7 --- /dev/null +++ b/src/dma/traits/f7.rs @@ -0,0 +1,225 @@ +use super::*; + +dma_map! { + (Stream0:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX + (Stream2:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX + (Stream3:0, pac::SPI2, [PeripheralToMemory]), //SPI2_RX + (Stream4:0, pac::SPI2, [MemoryToPeripheral]), //SPI2_TX + (Stream5:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX + (Stream7:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX + + (Stream0:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX + (Stream1:1, pac::I2C3, [PeripheralToMemory]), //I2C3_RX + (Stream2:1, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP + (Stream4:1, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP + (Stream5:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX + (Stream6:1, pac::I2C1, [MemoryToPeripheral]), //I2C1_TX + (Stream7:1, pac::I2C1, [MemoryToPeripheral]), //I2C1_TX + + (Stream0:2, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1 + (Stream3:2, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2 + (Stream6:2, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP + (Stream7:2, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3 + + (Stream1:3, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3 + (Stream1:3, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP + (Stream2:3, pac::I2C3, [PeripheralToMemory]), //I2C3_RX + (Stream4:3, pac::I2C3, [MemoryToPeripheral]), //I2C3_TX + (Stream5:3, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1 + (Stream6:3, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2 + (Stream6:3, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4 + (Stream7:3, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4 + (Stream7:3, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP + + (Stream0:4, pac::UART5, [PeripheralToMemory]), //UART5_RX + (Stream1:4, pac::USART3, [PeripheralToMemory]), //USART3_RX + (Stream2:4, pac::UART4, [PeripheralToMemory]), //UART4_RX + (Stream3:4, pac::USART3, [MemoryToPeripheral]), //USART3_TX + (Stream4:4, pac::UART4, [MemoryToPeripheral]), //UART4_TX + (Stream5:4, pac::USART2, [PeripheralToMemory]), //USART2_RX + (Stream6:4, pac::USART2, [MemoryToPeripheral]), //USART2_TX + (Stream7:4, pac::UART5, [MemoryToPeripheral]), //UART5_TX + + (Stream0:5, pac::UART8, [MemoryToPeripheral]), //UART8_TX + (Stream1:5, pac::UART7, [MemoryToPeripheral]), //UART7_TX + (Stream2:5, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4 + (Stream2:5, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_UP + (Stream3:5, pac::UART7, [PeripheralToMemory]), //UART7_RX + (Stream4:5, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1 + (Stream4:5, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG + (Stream5:5, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2 + (Stream6:5, pac::UART8, [PeripheralToMemory]), //UART8_RX + (Stream7:5, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3 + + (Stream0:6, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3 + (Stream0:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP + (Stream1:6, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4 + (Stream1:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_TRIG + (Stream2:6, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH1 + (Stream3:6, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4 + (Stream3:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_TRIG + (Stream4:6, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH2 + (Stream6:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP + + (Stream1:7, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP + (Stream2:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX + (Stream3:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX + (Stream4:7, pac::USART3, [MemoryToPeripheral]), //USART3_TX:DMA_CHANNEL_7 + (Stream5:7, pac::DAC, [MemoryToPeripheral]), //DAC1 + //(Stream6:7, pac::DAC2, [MemoryToPeripheral]), //DAC2 + (Stream7:7, pac::I2C2, [MemoryToPeripheral]), //I2C2_TX + + + (Stream0:0, pac::ADC1, [PeripheralToMemory]), //ADC1 + (Stream1:0, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A + (Stream2:0, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1 + (Stream2:0, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2 + (Stream2:0, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3 + (Stream3:0, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A + (Stream4:0, pac::ADC1, [PeripheralToMemory]), //ADC1 + (Stream5:0, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B:DMA_CHANNEL_0 + (Stream6:0, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1 + (Stream6:0, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2 + (Stream6:0, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3 + (Stream7:0, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B:DMA_CHANNEL_0 + + (Stream2:1, pac::ADC2, [PeripheralToMemory]), //ADC2 + (Stream3:1, pac::ADC2, [PeripheralToMemory]), //ADC2 + (Stream4:1, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B + + (Stream0:2, pac::ADC3, [PeripheralToMemory]), //ADC3 + (Stream1:2, pac::ADC3, [PeripheralToMemory]), //ADC3 + (Stream3:2, pac::SPI5, [PeripheralToMemory]), //SPI5_RX + (Stream4:2, pac::SPI5, [MemoryToPeripheral]), //SPI5_TX + + (Stream0:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX + (Stream2:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX + (Stream3:3, pac::SPI1, [MemoryToPeripheral]), //SPI1_TX + (Stream4:3, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_A + (Stream5:3, pac::SPI1, [MemoryToPeripheral]), //SPI1_TX + (Stream6:3, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B + (Stream7:3, pac::QUADSPI, [MemoryToPeripheral | PeripheralToMemory]), //QUADSPI + + (Stream0:4, pac::SPI4, [PeripheralToMemory]), //SPI4_RX + (Stream1:4, pac::SPI4, [MemoryToPeripheral]), //SPI4_TX + (Stream2:4, pac::USART1, [PeripheralToMemory]), //USART1_RX + (Stream3:4, pac::SDMMC1, [MemoryToPeripheral | PeripheralToMemory]), //SDMMC1 + (Stream5:4, pac::USART1, [PeripheralToMemory]), //USART1_RX + (Stream6:4, pac::SDMMC1, [MemoryToPeripheral | PeripheralToMemory]), //SDMMC1 + (Stream7:4, pac::USART1, [MemoryToPeripheral]), //USART1_TX + + (Stream1:5, pac::USART6, [PeripheralToMemory]), //USART6_RX + (Stream2:5, pac::USART6, [PeripheralToMemory]), //USART6_RX + (Stream3:5, pac::SPI4, [PeripheralToMemory]), //SPI4_RX:DMA_CHANNEL_5 + (Stream4:5, pac::SPI4, [MemoryToPeripheral]), //SPI4_TX:DMA_CHANNEL_5 + (Stream6:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX + (Stream7:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX + + (Stream0:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG + (Stream1:6, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1 + (Stream2:6, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2 + (Stream3:6, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1 + (Stream4:6, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4 + (Stream4:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG/COM + (Stream5:6, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP + (Stream6:6, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3 + + (Stream1:7, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_UP + (Stream2:7, timer::CCR1, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1 + (Stream3:7, timer::CCR2, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2 + (Stream4:7, timer::CCR3, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3 + (Stream5:7, pac::SPI5, [PeripheralToMemory]), //SPI5_RX:DMA_CHANNEL_7 + (Stream6:7, pac::SPI5, [MemoryToPeripheral]), //SPI5_TX:DMA_CHANNEL_7 + (Stream7:7, timer::CCR4, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH4 + (Stream7:7, timer::DMAR, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_COM/TRIG +} + +#[cfg(feature = "spdifrx")] +dma_map!( + (Stream1:0, pac::SPDIFRX, [PeripheralToMemory]), //SPDIF_RX_DT + //(Stream6:0, SPDIFRX_CS, [PeripheralToMemory]), //SPDIF_RX_CS +); + +#[cfg(feature = "i2c4")] +dma_map!( + (Stream2:2, pac::I2C4, [PeripheralToMemory]), //I2C4_RX + (Stream5:2, pac::I2C4, [PeripheralToMemory]), //I2C4_RX +); + +#[cfg(feature = "sdmmc2")] +dma_map!( + (Stream0:11, pac::SDMMC2, [MemoryToPeripheral | PeripheralToMemory]), //SDMMC2 + (Stream5:11, pac::SDMMC2, [MemoryToPeripheral | PeripheralToMemory]), //SDMMC2 +); + +#[cfg(feature = "dcmi")] +dma_map!( + (Stream1:1, pac::DCMI, [PeripheralToMemory]), //DCMI + (Stream7:1, pac::DCMI, [PeripheralToMemory]), //DCMI +); +#[cfg(feature = "dcmi")] +address!((pac::DCMI, dr, u32),); + +#[cfg(feature = "spi6")] +dma_map!( + (Stream5:1, pac::SPI6, [MemoryToPeripheral]), //SPI6_TX + (Stream6:1, pac::SPI6, [PeripheralToMemory]), //SPI6_RX +); + +#[cfg(feature = "spi6")] +address!((pac::SPI6, dr, u8),); + +#[cfg(feature = "aes")] +dma_map!( + (Stream6:2, AES_IN, [MemoryToPeripheral]), //AES_IN + (Stream5:2, AES_OUT, [PeripheralToMemory]), //AES_OUT +); + +#[cfg(feature = "cryp")] +dma_map!( + (Stream6:2, CRYP_IN, [MemoryToPeripheral]), //CRYP_IN + (Stream5:2, CRYP_OUT, [PeripheralToMemory]), //CRYP_OUT +); + +/*#[cfg(feature = "hash")] +dma_map!( + (Stream7:2, HASH_IN, [MemoryToPeripheral]), //HASH_IN +);*/ + +#[cfg(feature = "gpio-f76x")] +#[cfg(not(feature = "stm32f765"))] +use crate::pac::DFSDM; +#[cfg(feature = "stm32f765")] +use crate::pac::DFSDM1 as DFSDM; +#[cfg(feature = "gpio-f76x")] +dma_map!( + (Stream0:8, pac::I2C3, [MemoryToPeripheral]), //I2C3_TX + (Stream1:8, pac::I2C4, [PeripheralToMemory]), //I2C4_RX + (Stream4:8, pac::I2C2, [MemoryToPeripheral]), //I2C2_TX + (Stream6:8, pac::I2C4, [MemoryToPeripheral]), //I2C4_TX + (Stream1:9, pac::SPI2, [PeripheralToMemory]), //SPI2_RX + (Stream6:9, pac::SPI2, [MemoryToPeripheral]), //SPI2_TX + + + (Stream0:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT0 + (Stream1:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT1 + (Stream2:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT2 + (Stream3:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT3 + (Stream4:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT0 + (Stream5:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT1 + (Stream6:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT2 + (Stream7:8, FLT, [PeripheralToMemory]), //DFSDM1_FLT3 + + //(Stream0:9, FLT, [MemoryToPeripheral]), //JPEG_IN + //(Stream1:9, FLT, [PeripheralToMemory]), //JPEG_OUT + //(Stream3:9, FLT, [MemoryToPeripheral]), //JPEG_IN + //(Stream4:9, FLT, [PeripheralToMemory]), //JPEG_OUT + + (Stream0:10, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_B + (Stream1:10, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_B + (Stream2:10, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI2_A + (Stream6:10, SAICH, [MemoryToPeripheral | PeripheralToMemory]), //SAI1_A + + (Stream2:11, pac::QUADSPI, [MemoryToPeripheral | PeripheralToMemory]), //QUADSPI + +); diff --git a/src/dma/traits/g4.rs b/src/dma/traits/g4.rs new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/src/dma/traits/g4.rs @@ -0,0 +1 @@ + diff --git a/src/dma/traits/l4.rs b/src/dma/traits/l4.rs new file mode 100644 index 00000000..4563e55b --- /dev/null +++ b/src/dma/traits/l4.rs @@ -0,0 +1 @@ +use super::*; diff --git a/src/flash.rs b/src/flash/f4.rs similarity index 100% rename from src/flash.rs rename to src/flash/f4.rs diff --git a/src/flash/f7.rs b/src/flash/f7.rs new file mode 100644 index 00000000..15870742 --- /dev/null +++ b/src/flash/f7.rs @@ -0,0 +1,301 @@ +//! Flash memory + +use crate::pac::FLASH; +use nb::block; + +/// Base address of flash memory on AXIM interface. +const FLASH_BASE: *mut u8 = 0x800_0000 as *mut u8; + +/// The last valid flash address in any STM32F7 device +const MAX_FLASH_ADDRESS: *mut u8 = 0x81F_FFFF as *mut u8; + +/// Flash programming error. +#[derive(Debug, PartialEq, Eq)] +pub enum Error { + Busy, + Locked, + EraseSequence, + ProgrammingParallelism, + ProgrammingAlignment, + WriteProtection, +} + +/// Embedded flash memory. +pub struct Flash { + registers: FLASH, +} + +impl Flash { + /// Creates a new Flash instance. + pub fn new(flash: FLASH) -> Self { + Self { registers: flash } + } + + /// Unlocks the flash memory. + pub fn unlock(&mut self) { + if !self.is_locked() { + // don't try to unlock the flash if it's already unlocked, because + // trying to unlock the flash twice causes a HardFault + return; + } + + self.registers.keyr().write(|w| w.key().set(0x45670123)); + self.registers.keyr().write(|w| w.key().set(0xCDEF89AB)); + } + + /// Locks the flash memory. + pub fn lock(&mut self) { + self.registers.cr().modify(|_, w| w.lock().set_bit()); + } + + /// Returns `true` if the flash memory is locked. + fn is_locked(&self) -> bool { + self.registers.cr().read().lock().is_locked() + } + + /// Returns `true` if a flash operation is in progress. + fn is_busy(&self) -> bool { + self.registers.sr().read().bsy().bit_is_set() + } + + /// Starts a sector erase sequence. + /// + /// The returned `EraseSequence` object can be used to wait for the completion of the + /// erase sequence by blocking on the `wait` method. + pub fn erase_sector(&mut self, sector_number: u8) -> Result, Error> { + EraseSequence::new_erase_sector(self, sector_number) + } + + /// Erases a flash sector. + /// + /// This method blocks until the sector is erased or an error occurred. + pub fn blocking_erase_sector(&mut self, sector_number: u8) -> Result<(), Error> { + let mut sequence = self.erase_sector(sector_number)?; + block!(sequence.wait()) + } + + /// Starts a mass erases of the flash memory. + /// + /// The returned `EraseSequence` object can be used to wait for the completion of the + /// erase sequence by blocking on the `wait` method. + pub fn mass_erase(&mut self) -> Result, Error> { + EraseSequence::new_mass_erase(self) + } + + /// Mass erases the flash memory. + /// + /// This method blocks until the flash is erased or an error occurred. + pub fn blocking_mass_erase(&mut self) -> Result<(), Error> { + let mut sequence = self.mass_erase()?; + block!(sequence.wait()) + } + + /// Starts a programming sequence. + /// + /// Note that you must block on the `wait` method in the returned `ProgrammingSequence` object + /// in order to program all bytes. + pub fn program<'a, 'b>( + &'a mut self, + start_offset: usize, + data: &'b [u8], + ) -> Result, Error> { + ProgrammingSequence::new(self, start_offset, data) + } + + /// Programs a block of flash memory. + /// + /// This method blocks until the block is programed or an error occurred. + pub fn blocking_program(&mut self, start_offset: usize, data: &[u8]) -> Result<(), Error> { + let mut sequence = self.program(start_offset, data)?; + block!(sequence.wait()) + } + + /// Releases the flash peripheral. + pub fn free(self) -> FLASH { + self.registers + } + + /// Returns an error if the flash is locked or busy. + fn check_locked_or_busy(&self) -> Result<(), Error> { + if self.is_locked() { + Err(Error::Locked) + } else if self.is_busy() { + Err(Error::Busy) + } else { + Ok(()) + } + } + + /// Checks the error flags. + fn check_errors(&self) -> Result<(), Error> { + let sr = self.registers.sr().read(); + + if sr.erserr().bit_is_set() { + Err(Error::EraseSequence) + } else if sr.pgperr().bit_is_set() { + Err(Error::ProgrammingParallelism) + } else if sr.pgaerr().bit_is_set() { + Err(Error::ProgrammingAlignment) + } else if sr.wrperr().bit_is_set() { + Err(Error::WriteProtection) + } else { + Ok(()) + } + } + + /// Clears all error flags. + fn clear_errors(&mut self) { + self.registers.sr().write(|w| { + w.erserr().clear_bit_by_one(); + w.pgperr().clear_bit_by_one(); + w.pgaerr().clear_bit_by_one(); + w.wrperr().clear_bit_by_one() + }); + } +} + +/// Erase sequence. +pub struct EraseSequence<'a> { + flash: &'a mut Flash, +} + +impl<'a> EraseSequence<'a> { + /// Creates a sector erase sequence. + fn new_erase_sector(flash: &'a mut Flash, sector_number: u8) -> Result { + flash.check_locked_or_busy()?; + flash.clear_errors(); + + //TODO: This should check if sector_number is valid for this device + + flash.registers.cr().modify(|_, w| unsafe { + #[cfg(any( + feature = "stm32f765", + feature = "stm32f767", + feature = "stm32f769", + feature = "stm32f777", + feature = "stm32f778", + feature = "stm32f779", + ))] + w.mer1().clear_bit().mer2().clear_bit(); + #[cfg(not(any( + feature = "stm32f765", + feature = "stm32f767", + feature = "stm32f769", + feature = "stm32f777", + feature = "stm32f778", + feature = "stm32f779", + )))] + w.mer().clear_bit(); + w.ser().set_bit(); + w.snb().bits(sector_number) + }); + flash.registers.cr().modify(|_, w| w.strt().start()); + + Ok(Self { flash }) + } + + /// Creates a mass erase sequence. + fn new_mass_erase(flash: &'a mut Flash) -> Result { + flash.check_locked_or_busy()?; + flash.clear_errors(); + + flash.registers.cr().modify(|_, w| { + #[cfg(any( + feature = "stm32f765", + feature = "stm32f767", + feature = "stm32f769", + feature = "stm32f777", + feature = "stm32f778", + feature = "stm32f779", + ))] + w.mer1().set_bit().mer2().set_bit(); + #[cfg(not(any( + feature = "stm32f765", + feature = "stm32f767", + feature = "stm32f769", + feature = "stm32f777", + feature = "stm32f778", + feature = "stm32f779", + )))] + w.mer().clear_bit(); + w.ser().clear_bit() + }); + + flash.registers.cr().modify(|_, w| w.strt().start()); + + Ok(Self { flash }) + } + + /// Waits until the erase sequence is finished. + pub fn wait(&mut self) -> nb::Result<(), Error> { + self.flash.check_errors().map_err(nb::Error::from)?; + + if self.flash.is_busy() { + Err(nb::Error::WouldBlock) + } else { + Ok(()) + } + } +} + +/// Programming sequence. +pub struct ProgrammingSequence<'a, 'b> { + flash: &'a mut Flash, + data: &'b [u8], + address: *mut u8, +} + +impl<'a, 'b> ProgrammingSequence<'a, 'b> { + /// Creates a programming sequence. + fn new(flash: &'a mut Flash, start_offset: usize, data: &'b [u8]) -> Result { + flash.check_locked_or_busy()?; + flash.clear_errors(); + + flash + .registers + .cr() + .modify(|_, w| w.psize().psize8().pg().set_bit()); + + let address = unsafe { FLASH_BASE.add(start_offset) }; + + Ok(Self { + flash, + data, + address, + }) + } + + /// Waits until the programming sequence is finished. + pub fn wait(&mut self) -> nb::Result<(), Error> { + if self.flash.is_busy() { + return Err(nb::Error::WouldBlock); + } + + if let Err(error) = self.flash.check_errors() { + // make sure programing mode is disabled when an error occurred + self.flash.registers.cr().modify(|_, w| w.pg().clear_bit()); + + return Err(error.into()); + } + + if let Some((first, rest)) = self.data.split_first() { + if self.address >= FLASH_BASE && self.address <= MAX_FLASH_ADDRESS { + unsafe { + core::ptr::write_volatile(self.address, *first); + } + } + + // ensure data is written byte by byte to prevent programming parallelism errors + cortex_m::asm::dmb(); + + self.address = unsafe { self.address.add(1) }; + self.data = rest; + + Err(nb::Error::WouldBlock) + } else { + self.flash.registers.cr().modify(|_, w| w.pg().clear_bit()); + + Ok(()) + } + } +} diff --git a/src/flash/l4.rs b/src/flash/l4.rs new file mode 100644 index 00000000..0e791bc2 --- /dev/null +++ b/src/flash/l4.rs @@ -0,0 +1,397 @@ +//! Flash memory module +//! +//! Example usage of flash programming interface: +//! +//! ``` +//! fn program_region(mut flash: flash::Parts) -> Result<(), flash::Error> { +//! // Unlock the flashing module +//! let mut prog = flash.keyr.unlock_flash(&mut flash.sr, &mut flash.cr)?; +//! +//! let page = flash::FlashPage(5); +//! +//! // Perform the erase and programing operation +//! prog.erase_page(page)?; +//! let data = [ +//! 0x1111_1112_1113_1114, +//! 0x2221_2222_2223_2224, +//! 0x3331_3332_3333_3334, +//! ]; +//! prog.write_native(page.to_address(), &data)?; +//! +//! // Check result (not needed, but done for this example) +//! let addr = page.to_address() as *const u64; +//! assert!(unsafe { core::ptr::read(addr) } == data[0]); +//! assert!(unsafe { core::ptr::read(addr.offset(1)) } == data[1]); +//! assert!(unsafe { core::ptr::read(addr.offset(2)) } == data[2]); +//! +//! Ok(()) +//! } +//! ``` + +use crate::pac::{flash, FLASH}; +use core::convert::TryInto; +use core::{mem, ops::Drop, ptr}; + +/// Flash page representation where each flash page represents a region of 2048 bytes. The flash +/// controller can only erase on a page basis. +#[derive(Copy, Clone, Debug)] +pub struct FlashPage(pub usize); + +/// Flash operation error +#[derive(Copy, Clone, Debug)] +pub enum Error { + /// Flash controller is not done yet + Busy, + /// Error detected (by command execution, or because no command could be executed) + Illegal, + /// Set during read if ECC decoding logic detects correctable or uncorrectable error + EccError, + /// Page number is out of range + PageOutOfRange, + /// (Legal) command failed + Failure, +} + +/// A type alias for the result of a Flash operation. +pub type FResult = core::result::Result<(), Error>; + +pub trait Read { + /// Native type of the flash for reading with the correct alignment of the memory and size + /// + /// Can be `u8`, `u16`, `u32`, ..., or any user defined type + type NativeType; + + /// Read from the flash memory using the native interface + fn read_native(&self, address: usize, array: &mut [Self::NativeType]); + + /// Read a buffer of bytes from memory + fn read(&self, address: usize, buf: &mut [u8]); +} + +pub trait WriteErase { + /// Native type of the flash for writing with the correct alignment and size + /// + /// Can be `u8`, `u16`, `u32`, ..., or any user defined type + type NativeType; + + /// check flash status + fn status(&self) -> FResult; + + /// Erase specified flash page. + fn erase_page(&mut self, page: FlashPage) -> FResult; + + /// The smallest possible write, depends on platform + fn write_native(&mut self, address: usize, array: &[Self::NativeType]) -> FResult; + + /// Read a buffer of bytes to memory, this uses the native writes internally and if it's not + /// the same length and a set of native writes the write will be padded to fill a native write. + fn write(&mut self, address: usize, data: &[u8]) -> FResult; +} + +/// Extension trait to constrain the FLASH peripheral +pub trait FlashExt { + /// Constrains the FLASH peripheral to play nicely with the other abstractions + fn constrain(self) -> Parts; +} + +impl FlashExt for FLASH { + fn constrain(self) -> Parts { + Parts { + acr: ACR {}, + pdkeyr: PDKEYR {}, + keyr: KEYR {}, + optkeyr: OPTKEYR {}, + sr: SR {}, + cr: CR {}, + eccr: ECCR {}, + pcrop1sr: PCROP1SR {}, + pcrop1er: PCROP1ER {}, + wrp1ar: WRP1AR {}, + wrp1br: WRP1BR {}, + } + } +} + +/// Constrained FLASH peripheral +pub struct Parts { + /// Opaque ACR register + pub acr: ACR, + /// Opaque PDKEYR register + pub pdkeyr: PDKEYR, + /// Opaque KEYR register + pub keyr: KEYR, + /// Opaque OPTKEYR register + pub optkeyr: OPTKEYR, + /// Opaque SR register + pub sr: SR, + /// Opaque SR register + pub cr: CR, + /// Opaque ECCR register + pub eccr: ECCR, + /// Opaque PCROP1SR register + pub pcrop1sr: PCROP1SR, + /// Opaque PCROP1ER register + pub pcrop1er: PCROP1ER, + /// Opaque WRP1AR register + pub wrp1ar: WRP1AR, + /// Opaque WRP1BR register + pub wrp1br: WRP1BR, +} + +macro_rules! generate_register { + ($a:ident, $b:ident, $name:expr) => { + #[doc = "Opaque "] + #[doc = $name] + #[doc = " register"] + pub struct $a; + + impl $a { + #[allow(unused)] + pub(crate) fn $b(&mut self) -> &flash::$a { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*FLASH::ptr()).$b } + } + } + }; + + ($a:ident, $b:ident) => { + generate_register!($a, $b, stringify!($a)); + }; +} + +generate_register!(ACR, acr); +generate_register!(PDKEYR, pdkeyr); +generate_register!(KEYR, keyr); +generate_register!(OPTKEYR, optkeyr); +generate_register!(SR, sr); +generate_register!(CR, cr); +generate_register!(ECCR, eccr); +generate_register!(PCROP1SR, pcrop1sr); +generate_register!(PCROP1ER, pcrop1er); +generate_register!(WRP1AR, wrp1ar); +generate_register!(WRP1BR, wrp1br); + +const FLASH_KEY1: u32 = 0x4567_0123; +const FLASH_KEY2: u32 = 0xCDEF_89AB; + +impl KEYR { + /// Unlock the flash registers via KEYR to access the flash programming + pub fn unlock_flash<'a>( + &'a mut self, + sr: &'a mut SR, + cr: &'a mut CR, + ) -> Result, Error> { + let keyr = self.keyr(); + unsafe { + keyr.write(|w| w.bits(FLASH_KEY1)); + keyr.write(|w| w.bits(FLASH_KEY2)); + } + + if cr.cr().read().lock().bit_is_clear() { + Ok(FlashProgramming { sr, cr }) + } else { + Err(Error::Failure) + } + } +} + +impl FlashPage { + /// This gives the starting address of a flash page in physical address + pub const fn to_address(&self) -> usize { + 0x0800_0000 + self.0 * 2048 + } +} + +/// Flash programming interface +pub struct FlashProgramming<'a> { + sr: &'a mut SR, + cr: &'a mut CR, +} + +impl<'a> Drop for FlashProgramming<'a> { + fn drop(&mut self) { + // Lock on drop + self.lock(); + } +} + +impl<'a> Read for FlashProgramming<'a> { + type NativeType = u8; + + #[inline] + fn read_native(&self, address: usize, array: &mut [Self::NativeType]) { + let mut address = address as *const Self::NativeType; + + for data in array { + unsafe { + *data = ptr::read(address); + address = address.add(1); + } + } + } + + #[inline] + fn read(&self, address: usize, buf: &mut [u8]) { + self.read_native(address, buf); + } +} + +impl<'a> WriteErase for FlashProgramming<'a> { + type NativeType = u64; + + fn status(&self) -> FResult { + let sr = unsafe { &(*FLASH::ptr()).sr }.read(); + + if sr.bsy().bit_is_set() { + Err(Error::Busy) + } else if sr.pgaerr().bit_is_set() || sr.progerr().bit_is_set() || sr.wrperr().bit_is_set() + { + Err(Error::Illegal) + } else { + Ok(()) + } + } + + fn erase_page(&mut self, page: FlashPage) -> FResult { + match page.0 { + 0..=255 => { + self.cr.cr().modify(|_, w| unsafe { + w.bker() + .clear_bit() + .pnb() + .bits(page.0 as u8) + .per() + .set_bit() + }); + } + 256..=511 => { + self.cr.cr().modify(|_, w| unsafe { + w.bker() + .set_bit() + .pnb() + .bits((page.0 - 256) as u8) + .per() + .set_bit() + }); + } + _ => { + return Err(Error::PageOutOfRange); + } + } + + self.cr.cr().modify(|_, w| w.start().set_bit()); + + let res = self.wait(); + + self.cr.cr().modify(|_, w| w.per().clear_bit()); + + res + } + + fn write_native(&mut self, address: usize, array: &[Self::NativeType]) -> FResult { + // NB: The check for alignment of the address, and that the flash is erased is made by the + // flash controller. The `wait` function will return the proper error codes. + let mut address = address as *mut u32; + + self.cr.cr().modify(|_, w| w.pg().set_bit()); + + for dword in array { + unsafe { + ptr::write_volatile(address, *dword as u32); + ptr::write_volatile(address.add(1), (*dword >> 32) as u32); + + address = address.add(2); + } + + self.wait()?; + + if self.sr.sr().read().eop().bit_is_set() { + self.sr.sr().modify(|_, w| w.eop().clear_bit()); + } + } + + self.cr.cr().modify(|_, w| w.pg().clear_bit()); + + Ok(()) + } + + fn write(&mut self, address: usize, data: &[u8]) -> FResult { + let address_offset = address % mem::align_of::(); + let unaligned_size = (mem::size_of::() - address_offset) + % mem::size_of::(); + + if unaligned_size > 0 { + let unaligned_data = &data[..unaligned_size]; + // Handle unaligned address data, make it into a native write + let mut data = 0xffff_ffff_ffff_ffffu64; + for b in unaligned_data { + data = (data >> 8) | ((*b as Self::NativeType) << 56); + } + + let unaligned_address = address - address_offset; + let native = &[data]; + self.write_native(unaligned_address, native)?; + } + + // Handle aligned address data + let aligned_data = &data[unaligned_size..]; + let mut aligned_address = if unaligned_size > 0 { + address - address_offset + mem::size_of::() + } else { + address + }; + + let mut chunks = aligned_data.chunks_exact(mem::size_of::()); + + while let Some(exact_chunk) = chunks.next() { + // Write chunks + let native = &[Self::NativeType::from_ne_bytes( + exact_chunk.try_into().unwrap(), + )]; + self.write_native(aligned_address, native)?; + aligned_address += mem::size_of::(); + } + + let rem = chunks.remainder(); + + if !rem.is_empty() { + let mut data = 0xffff_ffff_ffff_ffffu64; + // Write remainder + for b in rem.iter().rev() { + data = (data << 8) | *b as Self::NativeType; + } + + let native = &[data]; + self.write_native(aligned_address, native)?; + } + + Ok(()) + } +} + +impl<'a> FlashProgramming<'a> { + /// Lock the flash memory controller + fn lock(&mut self) { + self.cr.cr().modify(|_, w| w.lock().set_bit()); + } + + /// Wait till last flash operation is complete + fn wait(&mut self) -> FResult { + while self.sr.sr().read().bsy().bit_is_set() {} + + self.status() + } + + /// Erase all flash pages, note that this will erase the current running program if it is not + /// called from a program running in RAM. + pub fn erase_all_pages(&mut self) -> FResult { + self.cr.cr().modify(|_, w| w.mer1().set_bit()); + self.cr.cr().modify(|_, w| w.start().set_bit()); + + let res = self.wait(); + + self.cr.cr().modify(|_, w| w.mer1().clear_bit()); + + res + } +} diff --git a/src/fmc.rs b/src/fmc.rs new file mode 100644 index 00000000..b2f3a00b --- /dev/null +++ b/src/fmc.rs @@ -0,0 +1,202 @@ +//! HAL for Flexible memory controller (FMC) +//! +//! See the stm32-fmc [usage guide](https://github.com/stm32-rs/stm32-fmc#usage) + +// From stm32_fmc + +use stm32_fmc::FmcPeripheral; +use stm32_fmc::{AddressPinSet, PinsSdram, Sdram, SdramChip, SdramPinSet, SdramTargetBank}; + +use crate::pac; +use crate::rcc::{BusClock, Clocks, Enable, Reset}; +use fugit::HertzU32 as Hertz; + +use crate::gpio::alt::fmc as alt; + +/// Storage type for Flexible Memory Controller and its clocks +pub struct FMC { + pub fmc: pac::FMC, + hclk: Hertz, +} + +/// Extension trait for FMC controller +pub trait FmcExt: Sized { + fn fmc(self, clocks: &Clocks) -> FMC; + + /// A new SDRAM memory via the Flexible Memory Controller + fn sdram< + BANK: SdramPinSet, + ADDR: AddressPinSet, + PINS: PinsSdram, + CHIP: SdramChip, + >( + self, + pins: PINS, + chip: CHIP, + clocks: &Clocks, + ) -> Sdram { + let fmc = self.fmc(clocks); + Sdram::new(fmc, pins, chip) + } + + /// A new SDRAM memory via the Flexible Memory Controller + fn sdram_unchecked>( + self, + bank: BANK, + chip: CHIP, + clocks: &Clocks, + ) -> Sdram { + let fmc = self.fmc(clocks); + Sdram::new_unchecked(fmc, bank, chip) + } +} + +impl FmcExt for pac::FMC { + /// New FMC instance + fn fmc(self, clocks: &Clocks) -> FMC { + FMC { + fmc: self, + hclk: pac::FMC::clock(clocks), + } + } +} + +unsafe impl FmcPeripheral for FMC { + const REGISTERS: *const () = pac::FMC::ptr() as *const (); + + fn enable(&mut self) { + // TODO : change it to something safe ... + unsafe { + // Enable FMC + pac::FMC::enable_unchecked(); + // Reset FMC + pac::FMC::reset_unchecked(); + } + } + + fn source_clock_hz(&self) -> u32 { + // FMC block is clocked by HCLK + self.hclk.raw() + } +} + +macro_rules! pins { + ($($F:ident: $P:ident;)+) => { + $( + impl stm32_fmc::$F for alt::$P {} + )+ + } +} + +pins! { + A0: A0; + A1: A1; + A2: A2; + A3: A3; + A4: A4; + A5: A5; + A6: A6; + A7: A7; + A8: A8; + A9: A9; + A10: A10; + A11: A11; + A12: A12; + A13: A13; + A14: A14; + A15: A15; + A16: A16; + A17: A17; + A18: A18; + A19: A19; + A20: A20; + A21: A21; + A22: A22; + A23: A23; + A24: A24; + CLK: Clk; + D0: D0; + D1: D1; + D2: D2; + D3: D3; + D4: D4; + D5: D5; + D6: D6; + D7: D7; + D8: D8; + D9: D9; + D10: D10; + D11: D11; + D12: D12; + D13: D13; + D14: D14; + D15: D15; + DA0: Da0; + DA1: Da1; + DA2: Da2; + DA3: Da3; + DA4: Da4; + DA5: Da5; + DA6: Da6; + DA7: Da7; + DA8: Da8; + DA9: Da9; + DA10: Da10; + DA11: Da11; + DA12: Da12; + DA13: Da13; + DA14: Da14; + DA15: Da15; + NBL0: Nbl0; + NBL1: Nbl1; + // NCE: Nce; + NE1: Ne1; + NE2: Ne2; + NE3: Ne3; + NE4: Ne4; + NL: Nl; + NOE: Noe; + NWAIT: Nwait; + NWE: Nwe; +} + +#[cfg(any(feature = "gpio-f427", feature = "gpio-f446", feature = "gpio-f469"))] +pins! { + BA0: Ba0; + BA1: Ba1; + SDCKE0: Sdcke0; + SDCKE1: Sdcke1; + SDCLK: Sdclk; + SDNCAS: Sdncas; + SDNE0: Sdne0; + SDNE1: Sdne1; + SDNRAS: Sdnras; + SDNWE: Sdnwe; +} + +#[cfg(any(feature = "gpio-f427", feature = "gpio-f469"))] +pins! { + D16: D16; + D17: D17; + D18: D18; + D19: D19; + D20: D20; + D21: D21; + D22: D22; + D23: D23; + D24: D24; + D25: D25; + D26: D26; + D27: D27; + D28: D28; + D29: D29; + D30: D30; + D31: D31; + NBL2: Nbl2; + NBL3: Nbl3; +} + +#[cfg(feature = "gpio-f469")] +pins! { + INT: Int; +} diff --git a/src/fmpi2c.rs b/src/fmpi2c.rs index 7040e2bb..57a3aaf2 100644 --- a/src/fmpi2c.rs +++ b/src/fmpi2c.rs @@ -1,19 +1,34 @@ use core::ops::Deref; use crate::gpio; -use crate::i2c::{Error, NoAcknowledgeSource}; +#[cfg(feature = "fmpi2c1")] use crate::pac::fmpi2c1 as i2c1; -use crate::pac::{self, RCC}; -use crate::rcc::{BusClock, Enable, Reset}; +#[cfg(feature = "i2c_v2")] +use crate::pac::i2c1; +use crate::pac::{self, rcc, RCC}; +use crate::rcc::{BusClock, Clocks, Enable, Reset}; use fugit::{HertzU32 as Hertz, RateExtU32}; +use micromath::F32Ext; + +#[path = "i2c/common.rs"] +mod common; +pub use common::{Address, Error, NoAcknowledgeSource}; +use common::{Hal02Operation, Hal1Operation}; // Old names pub use I2c as FmpI2c; pub use Mode as FmpMode; +#[path = "i2c/hal_02.rs"] mod hal_02; +#[path = "i2c/hal_1.rs"] mod hal_1; +#[cfg(feature = "fmpi2c1")] +type I2cSel = rcc::dckcfgr2::FMPI2C1SEL; +#[cfg(feature = "i2c_v2")] +type I2cSel = rcc::dckcfgr2::I2C1SEL; + pub trait Instance: crate::Sealed + crate::Ptr @@ -23,7 +38,7 @@ pub trait Instance: + BusClock + gpio::alt::I2cCommon { - fn clock_hsi(rcc: &crate::pac::rcc::RegisterBlock); + fn set_clock_source(rcc: &rcc::RegisterBlock, source: I2cSel); } macro_rules! i2c { @@ -31,8 +46,8 @@ macro_rules! i2c { pub type $I2Calias = I2c<$I2C>; impl Instance for $I2C { - fn clock_hsi(rcc: &crate::pac::rcc::RegisterBlock) { - rcc.dckcfgr2().modify(|_, w| w.$i2csel().hsi()); + fn set_clock_source(rcc: &rcc::RegisterBlock, source: I2cSel) { + rcc.dckcfgr2().modify(|_, w| w.$i2csel().variant(source)); } } @@ -48,6 +63,17 @@ macro_rules! i2c { #[cfg(feature = "fmpi2c1")] i2c!(pac::FMPI2C1, fmpi2c1sel, FMPI2c1); +#[cfg(feature = "i2c_v2")] +i2c!(pac::I2C1, i2c1sel, I2c1); +#[cfg(feature = "i2c_v2")] +#[cfg(feature = "i2c2")] +i2c!(pac::I2C2, i2c2sel, I2c2); +#[cfg(feature = "i2c_v2")] +#[cfg(feature = "i2c3")] +i2c!(pac::I2C3, i2c3sel, I2c3); +#[cfg(feature = "i2c_v2")] +#[cfg(feature = "i2c4")] +i2c!(pac::I2C4, i2c4sel, I2c4); /// I2C FastMode+ abstraction pub struct I2c { @@ -60,6 +86,7 @@ pub enum Mode { Standard { frequency: Hertz }, Fast { frequency: Hertz }, FastPlus { frequency: Hertz }, + Custom { timing_r: I2cTiming }, } impl Mode { @@ -75,13 +102,13 @@ impl Mode { Self::FastPlus { frequency } } - pub fn get_frequency(&self) -> Hertz { + /*pub fn get_frequency(&self) -> Hertz { match *self { Self::Standard { frequency } => frequency, Self::Fast { frequency } => frequency, Self::FastPlus { frequency } => frequency, } - } + }*/ } impl From for Mode { @@ -98,11 +125,148 @@ impl From for Mode { } } +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ClockSource<'a> { + Apb(&'a Clocks), + Hsi, +} + +impl<'a> From<&'a Clocks> for ClockSource<'a> { + fn from(value: &'a Clocks) -> Self { + Self::Apb(value) + } +} + +// hddat and vddat are removed because SDADEL is always going to be 0 in this implementation so +// condition is always met +struct I2cSpec { + freq_max: Hertz, + sudat_min: u32, + _lscl_min: u32, + _hscl_min: u32, + trise_max: u32, // in ns + _tfall_max: u32, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct I2cTiming { + pub presc: u8, + pub scldel: u8, + pub sdadel: u8, + pub sclh: u8, + pub scll: u8, +} + +// everything is in nano seconds +const I2C_STANDARD_MODE_SPEC: I2cSpec = I2cSpec { + freq_max: Hertz::Hz(102400), + sudat_min: 250, + _lscl_min: 4700, + _hscl_min: 4000, + trise_max: 640, + _tfall_max: 20, +}; +const I2C_FAST_MODE_SPEC: I2cSpec = I2cSpec { + freq_max: Hertz::Hz(409600), + sudat_min: 100, + _lscl_min: 1300, + _hscl_min: 600, + trise_max: 250, + _tfall_max: 100, +}; + +const I2C_FAST_PLUS_MODE_SPEC: I2cSpec = I2cSpec { + freq_max: Hertz::kHz(1024), + sudat_min: 50, + _lscl_min: 500, + _hscl_min: 260, + trise_max: 60, + _tfall_max: 100, +}; + +fn calculate_timing( + spec: I2cSpec, + i2c_freq: Hertz, + scl_freq: Hertz, + an_filter: bool, + dnf: u8, +) -> I2cTiming { + let i2c_freq = i2c_freq.raw(); + // frequency limit check + assert!(scl_freq <= spec.freq_max); + let scl_freq = scl_freq.raw(); + // T_sync or delay introduced in SCL + // generally it is 2-3 clock cycles + // t_sync + dnf delay + let t_dnf = (dnf) as f32 / i2c_freq as f32; + // if analog filter is enabled then it offer about 50 - 70 ns delay + let t_af: f32 = if an_filter { + 40.0 / 1_000_000_000f32 + } else { + 0.0 + }; + // t_sync = 2 to 3 * i2cclk + let t_sync = 2.0 / (i2c_freq as f32); + // fall or rise time + let t_fall: f32 = 50f32 / 1_000_000_000f32; + let t_rise: f32 = 60f32 / 1_000_000_000f32; + let t_delay = t_fall + t_rise + 2.0 * (t_dnf + t_af + t_sync); + // formula is like F_i2cclk/F/F_scl_clk = (scl_h+scl_l+2)*(Presc + 1) + // consider scl_l+scl_h is 256 max. but in that case clock should always + // be 50% duty cycle. lets consider scl_l+scl_h to be 128. so that it can + // be changed later + // (scl_l+scl_h+2)(presc +1 ) ==> as scl_width*presc ==F_i2cclk/F/F_scl_clk + let product: f32 = (1.0 - t_delay * (scl_freq as f32)) * (i2c_freq / scl_freq) as f32; + let scl_l: u8; + let scl_h: u8; + let mut presc: u8; + // if ratio is > (scll+sclh)*presc. that frequancy is not possible to generate. so + // minimum frequancy possible is generated + if product > 8192 as f32 { + // TODO: should we panic or use minimum allowed frequancy + scl_l = 0x7fu8; + scl_h = 0x7fu8; + presc = 0xfu8; + } else { + // smaller the minimum devition less difference between expected vs + // actual scl clock + let mut min_deviation = 16f32; + // TODO: use duty cycle and based on that use precstart + let presc_start = (product / 512.0).ceil() as u8; + presc = presc_start; + for tmp_presc in presc_start..17 { + let deviation = product % tmp_presc as f32; + if min_deviation > deviation { + min_deviation = deviation; + presc = tmp_presc as u8; + } + } + // now that we have optimal prescalar value. optimal scl_l and scl_h + // needs to be calculated + let scl_width = (product / presc as f32) as u16; // it will be always less than 256 + scl_h = (scl_width / 2 - 1) as u8; + scl_l = (scl_width - scl_h as u16 - 1) as u8; // This is to get max precision + presc -= 1; + } + let scldel: u8 = (((spec.trise_max + spec.sudat_min) as f32 / 1_000_000_000.0) + / ((presc + 1) as f32 / i2c_freq as f32) + - 1.0) + .ceil() as u8; + I2cTiming { + presc, + scldel, + sdadel: 0, + sclh: scl_h, + scll: scl_l, + } +} + pub trait I2cExt: Sized + Instance { fn i2c<'a>( self, pins: (impl Into, impl Into), mode: impl Into, + clocks: impl Into>, ) -> I2c; } @@ -111,16 +275,18 @@ impl I2cExt for I2C { self, pins: (impl Into, impl Into), mode: impl Into, + clocks: impl Into>, ) -> I2c { - I2c::new(self, pins, mode) + I2c::new(self, pins, mode, clocks) } } impl I2c { - pub fn new( + pub fn new<'a>( i2c: I2C, pins: (impl Into, impl Into), mode: impl Into, + clocks: impl Into>, ) -> Self { unsafe { // Enable and reset clock. @@ -131,7 +297,7 @@ impl I2c { let pins = (pins.0.into(), pins.1.into()); let i2c = I2c { i2c, pins }; - i2c.i2c_init(mode); + i2c.i2c_init(mode, clocks.into()); i2c } @@ -141,60 +307,98 @@ impl I2c { } impl I2c { - fn i2c_init(&self, mode: impl Into) { + fn i2c_init(&self, mode: impl Into, clocks: ClockSource<'_>) { let mode = mode.into(); - use core::cmp; // Make sure the I2C unit is disabled so we can configure it self.i2c.cr1().modify(|_, w| w.pe().clear_bit()); - // NOTE(unsafe) this reference will only be used for atomic writes with no side effects. - let rcc = unsafe { &(*RCC::ptr()) }; - I2C::clock_hsi(rcc); - - // Calculate settings for I2C speed modes - let presc; - let scldel; - let sdadel; - let sclh; - let scll; - - // We're using the HSI clock to keep things simple so this is going to be always 16 MHz - const FREQ: u32 = 16_000_000; - - // Normal I2C speeds use a different scaling than fast mode below and fast mode+ even more - // below - match mode { - Mode::Standard { frequency } => { - presc = 3; - scll = cmp::max((((FREQ >> presc) >> 1) / frequency.raw()) - 1, 255) as u8; - sclh = scll - 4; - sdadel = 2; - scldel = 4; - } - Mode::Fast { frequency } => { - presc = 1; - scll = cmp::max((((FREQ >> presc) >> 1) / frequency.raw()) - 1, 255) as u8; - sclh = scll - 6; - sdadel = 2; - scldel = 3; + let cr1 = self.i2c.cr1().read(); + let an_filter: bool = cr1.anfoff().is_enabled(); + let dnf = cr1.dnf().bits(); + + let i2c_timingr = match clocks { + ClockSource::Apb(clocks) => { + // NOTE(unsafe) this reference will only be used for atomic writes with no side effects. + unsafe { + let rcc = &(*RCC::ptr()); + I2C::set_clock_source(rcc, I2cSel::Apb); + } + let pclk = I2C::clock(clocks); + match mode { + Mode::Standard { frequency } => { + calculate_timing(I2C_STANDARD_MODE_SPEC, pclk, frequency, an_filter, dnf) + } + Mode::Fast { frequency } => { + calculate_timing(I2C_FAST_MODE_SPEC, pclk, frequency, an_filter, dnf) + } + Mode::FastPlus { frequency } => { + calculate_timing(I2C_FAST_PLUS_MODE_SPEC, pclk, frequency, an_filter, dnf) + } + Mode::Custom { timing_r } => timing_r, + } } - Mode::FastPlus { frequency } => { - presc = 0; - scll = cmp::max((((FREQ >> presc) >> 1) / frequency.raw()) - 4, 255) as u8; - sclh = scll - 2; - sdadel = 0; - scldel = 2; + ClockSource::Hsi => { + // NOTE(unsafe) this reference will only be used for atomic writes with no side effects. + unsafe { + let rcc = &(*RCC::ptr()); + I2C::set_clock_source(rcc, I2cSel::Hsi); + } + + use core::cmp; + // We're using the HSI clock to keep things simple so this is going to be always 16 MHz + const FREQ: u32 = 16_000_000; + // Normal I2C speeds use a different scaling than fast mode below and fast mode+ even more + // below + match mode { + Mode::Standard { frequency } => { + let presc = 3; + let scll = + cmp::max((((FREQ >> presc) >> 1) / frequency.raw()) - 1, 255) as u8; + I2cTiming { + presc, + scldel: 4, + sdadel: 2, + sclh: scll - 4, + scll, + } + } + Mode::Fast { frequency } => { + let presc = 1; + let scll = + cmp::max((((FREQ >> presc) >> 1) / frequency.raw()) - 1, 255) as u8; + I2cTiming { + presc, + scldel: 3, + sdadel: 2, + sclh: scll - 6, + scll, + } + } + Mode::FastPlus { frequency } => { + let presc = 0; + let scll = + cmp::max((((FREQ >> presc) >> 1) / frequency.raw()) - 4, 255) as u8; + I2cTiming { + presc, + scldel: 2, + sdadel: 0, + sclh: scll - 2, + scll, + } + } + Mode::Custom { timing_r } => timing_r, + } } - } + }; // Enable I2C signal generator, and configure I2C for configured speed self.i2c.timingr().write(|w| { - w.presc().set(presc); - w.scldel().set(scldel); - w.sdadel().set(sdadel); - w.sclh().set(sclh); - w.scll().set(scll) + w.presc().set(i2c_timingr.presc); + w.scldel().set(i2c_timingr.scldel); + w.sdadel().set(i2c_timingr.sdadel); + w.sclh().set(i2c_timingr.sclh); + w.scll().set(i2c_timingr.scll) }); // Enable the I2C processing @@ -222,6 +426,83 @@ impl I2c { Ok(()) } + /// Sends START and Address for writing + #[inline(always)] + fn prepare_write(&self, addr: Address, datalen: usize) -> Result<(), Error> { + // Set up current slave address for writing and disable autoending + self.i2c.cr2().modify(|_, w| { + match addr { + Address::Seven(addr) => { + w.add10().clear_bit(); + w.sadd().set(u16::from(addr) << 1); + } + Address::Ten(addr) => { + w.add10().set_bit(); + w.sadd().set(addr); + } + } + w.nbytes().set(datalen as u8); + w.rd_wrn().clear_bit(); + w.autoend().clear_bit() + }); + + // Send a START condition + self.i2c.cr2().modify(|_, w| w.start().set_bit()); + + // Wait until address was sent + while { + let isr = self.i2c.isr().read(); + self.check_and_clear_error_flags(&isr) + .map_err(Error::nack_addr)?; + isr.txis().bit_is_clear() && isr.tc().bit_is_clear() + } {} + + Ok(()) + } + + /// Sends START and Address for reading + fn prepare_read( + &self, + addr: Address, + buflen: usize, + first_transaction: bool, + ) -> Result<(), Error> { + // Set up current address for reading + self.i2c.cr2().modify(|_, w| { + match addr { + Address::Seven(addr) => { + w.add10().clear_bit(); + w.sadd().set(u16::from(addr) << 1); + } + Address::Ten(addr) => { + w.add10().set_bit(); + w.head10r().bit(!first_transaction); + w.sadd().set(addr); + } + } + w.nbytes().set(buflen as u8); + w.rd_wrn().set_bit() + }); + + // Send a START condition + self.i2c.cr2().modify(|_, w| w.start().set_bit()); + + // Send the autoend after setting the start to get a restart + self.i2c.cr2().modify(|_, w| w.autoend().set_bit()); + + Ok(()) + } + + fn write_bytes(&mut self, bytes: impl Iterator) -> Result<(), Error> { + // Send bytes + for c in bytes { + self.send_byte(c)?; + } + + // Fallthrough is success + Ok(()) + } + fn send_byte(&self, byte: u8) -> Result<(), Error> { // Wait until we're ready for sending while { @@ -251,72 +532,38 @@ impl I2c { Ok(value) } - pub fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error> { - // Set up current address for reading - self.i2c.cr2().modify(|_, w| { - w.sadd().set(u16::from(addr) << 1); - w.nbytes().set(buffer.len() as u8); - w.rd_wrn().set_bit() - }); - - // Send a START condition - self.i2c.cr2().modify(|_, w| w.start().set_bit()); - - // Send the autoend after setting the start to get a restart - self.i2c.cr2().modify(|_, w| w.autoend().set_bit()); - - // Now read in all bytes - for c in buffer.iter_mut() { + fn read_bytes(&mut self, buffer: &mut [u8]) -> Result<(), Error> { + // Receive bytes into buffer + for c in buffer { *c = self.recv_byte()?; } - self.end_transaction() + Ok(()) } - pub fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> { - // Set up current slave address for writing and enable autoending - self.i2c.cr2().modify(|_, w| { - w.sadd().set(u16::from(addr) << 1); - w.nbytes().set(bytes.len() as u8); - w.rd_wrn().clear_bit(); - w.autoend().set_bit() - }); - - // Send a START condition - self.i2c.cr2().modify(|_, w| w.start().set_bit()); - - // Send out all individual bytes - for c in bytes { - self.send_byte(*c)?; - } + pub fn read(&mut self, addr: impl Into
, buffer: &mut [u8]) -> Result<(), Error> { + self.prepare_read(addr.into(), buffer.len(), true)?; + self.read_bytes(buffer)?; self.end_transaction() } - pub fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> { - // Set up current slave address for writing and disable autoending - self.i2c.cr2().modify(|_, w| { - w.sadd().set(u16::from(addr) << 1); - w.nbytes().set(bytes.len() as u8); - w.rd_wrn().clear_bit(); - w.autoend().clear_bit() - }); - - // Send a START condition - self.i2c.cr2().modify(|_, w| w.start().set_bit()); + pub fn write(&mut self, addr: impl Into
, bytes: &[u8]) -> Result<(), Error> { + self.prepare_write(addr.into(), bytes.len())?; + self.write_bytes(bytes.iter().cloned())?; - // Wait until the transmit buffer is empty and there hasn't been any error condition - while { - let isr = self.i2c.isr().read(); - self.check_and_clear_error_flags(&isr) - .map_err(Error::nack_addr)?; - isr.txis().bit_is_clear() && isr.tc().bit_is_clear() - } {} + self.end_transaction() + } - // Send out all individual bytes - for c in bytes { - self.send_byte(*c)?; - } + pub fn write_read( + &mut self, + addr: impl Into
, + bytes: &[u8], + buffer: &mut [u8], + ) -> Result<(), Error> { + let addr = addr.into(); + self.prepare_write(addr, bytes.len())?; + self.write_bytes(bytes.iter().cloned())?; // Wait until data was sent while { @@ -326,24 +573,122 @@ impl I2c { isr.tc().bit_is_clear() } {} - // Set up current address for reading - self.i2c.cr2().modify(|_, w| { - w.sadd().set(u16::from(addr) << 1); - w.nbytes().set(buffer.len() as u8); - w.rd_wrn().set_bit() - }); + self.read(addr, buffer) + } - // Send another START condition - self.i2c.cr2().modify(|_, w| w.start().set_bit()); + pub fn transaction<'a>( + &mut self, + addr: impl Into
, + mut ops: impl Iterator>, + ) -> Result<(), Error> { + let addr = addr.into(); + if let Some(mut prev_op) = ops.next() { + // 1. Generate Start for operation + match &prev_op { + Hal1Operation::Read(buf) => self.prepare_read(addr, buf.len(), true)?, + Hal1Operation::Write(data) => self.prepare_write(addr, data.len())?, + }; + + for op in ops { + // 2. Execute previous operations. + match &mut prev_op { + Hal1Operation::Read(rb) => self.read_bytes(rb)?, + Hal1Operation::Write(wb) => self.write_bytes(wb.iter().cloned())?, + }; + // 3. If operation changes type we must generate new start + match (&prev_op, &op) { + (Hal1Operation::Read(_), Hal1Operation::Write(data)) => { + self.prepare_write(addr, data.len())? + } + (Hal1Operation::Write(_), Hal1Operation::Read(buf)) => { + self.prepare_read(addr, buf.len(), false)? + } + _ => {} // No changes if operation have not changed + } + + prev_op = op; + } - // Send the autoend after setting the start to get a restart - self.i2c.cr2().modify(|_, w| w.autoend().set_bit()); + // 4. Now, prev_op is last command use methods variations that will generate stop + match prev_op { + Hal1Operation::Read(rb) => self.read_bytes(rb)?, + Hal1Operation::Write(wb) => self.write_bytes(wb.iter().cloned())?, + }; - // Now read in all bytes - for c in buffer.iter_mut() { - *c = self.recv_byte()?; + self.end_transaction()?; } - self.end_transaction() + // Fallthrough is success + Ok(()) + } + + pub fn transaction_slice( + &mut self, + addr: impl Into
, + ops_slice: &mut [Hal1Operation<'_>], + ) -> Result<(), Error> { + let addr = addr.into(); + transaction_impl!(self, addr, ops_slice, Hal1Operation); + // Fallthrough is success + Ok(()) + } + + fn transaction_slice_hal_02( + &mut self, + addr: impl Into
, + ops_slice: &mut [Hal02Operation<'_>], + ) -> Result<(), Error> { + let addr = addr.into(); + transaction_impl!(self, addr, ops_slice, Hal02Operation); + // Fallthrough is success + Ok(()) } } + +macro_rules! transaction_impl { + ($self:ident, $addr:ident, $ops_slice:ident, $Operation:ident) => { + let i2c = $self; + let addr = $addr; + let mut ops = $ops_slice.iter_mut(); + + if let Some(mut prev_op) = ops.next() { + // 1. Generate Start for operation + match &prev_op { + $Operation::Read(buf) => i2c.prepare_read(addr, buf.len(), true)?, + $Operation::Write(data) => i2c.prepare_write(addr, data.len())?, + }; + + for op in ops { + // 2. Execute previous operations. + match &mut prev_op { + $Operation::Read(rb) => i2c.read_bytes(rb)?, + $Operation::Write(wb) => i2c.write_bytes(wb.iter().cloned())?, + }; + // 3. If operation changes type we must generate new start + match (&prev_op, &op) { + ($Operation::Read(_), $Operation::Write(data)) => { + i2c.prepare_write(addr, data.len())? + } + ($Operation::Write(_), $Operation::Read(buf)) => { + i2c.prepare_read(addr, buf.len(), false)? + } + _ => {} // No changes if operation have not changed + } + + prev_op = op; + } + + // 4. Now, prev_op is last command use methods variations that will generate stop + match prev_op { + $Operation::Read(rb) => i2c.read_bytes(rb)?, + $Operation::Write(wb) => i2c.write_bytes(wb.iter().cloned())?, + }; + + i2c.end_transaction()?; + } + }; +} +use transaction_impl; + +// Note: implementation is from f0xx-hal +// TODO: check error handling. See https://github.com/stm32-rs/stm32f0xx-hal/pull/95/files diff --git a/src/fmpi2c/hal_02.rs b/src/fmpi2c/hal_02.rs deleted file mode 100644 index 0cfa55df..00000000 --- a/src/fmpi2c/hal_02.rs +++ /dev/null @@ -1,28 +0,0 @@ -mod blocking { - use super::super::{Error, I2c, Instance}; - use embedded_hal_02::blocking::i2c::{Read, Write, WriteRead}; - - impl WriteRead for I2c { - type Error = Error; - - fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> { - self.write_read(addr, bytes, buffer) - } - } - - impl Read for I2c { - type Error = Error; - - fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error> { - self.read(addr, buffer) - } - } - - impl Write for I2c { - type Error = Error; - - fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> { - self.write(addr, bytes) - } - } -} diff --git a/src/fmpi2c/hal_1.rs b/src/fmpi2c/hal_1.rs deleted file mode 100644 index ad556c57..00000000 --- a/src/fmpi2c/hal_1.rs +++ /dev/null @@ -1,39 +0,0 @@ -use embedded_hal::i2c::ErrorType; - -use super::Instance; - -impl ErrorType for super::I2c { - type Error = super::Error; -} - -mod blocking { - use super::super::{I2c, Instance}; - use embedded_hal::i2c::Operation; - - impl embedded_hal::i2c::I2c for I2c { - fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> { - self.read(addr, buffer) - } - - fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> { - self.write(addr, bytes) - } - - fn write_read( - &mut self, - addr: u8, - bytes: &[u8], - buffer: &mut [u8], - ) -> Result<(), Self::Error> { - self.write_read(addr, bytes, buffer) - } - - fn transaction( - &mut self, - _addr: u8, - _operations: &mut [Operation<'_>], - ) -> Result<(), Self::Error> { - todo!() - } - } -} diff --git a/src/fsmc_lcd/pins.rs b/src/fsmc_lcd/pins.rs index 6e30341a..ac27e84b 100644 --- a/src/fsmc_lcd/pins.rs +++ b/src/fsmc_lcd/pins.rs @@ -17,7 +17,7 @@ use core::marker::PhantomData; -use crate::gpio::alt::fsmc as alt; +use crate::gpio::alt::fmc as alt; use super::sealed; use super::{Lcd, SubBank1, Word}; diff --git a/src/gpio.rs b/src/gpio.rs index 5b8a8143..977a12d8 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -618,13 +618,96 @@ macro_rules! gpio { } use gpio; +#[cfg(feature = "c0")] +mod c0; +#[cfg(feature = "c0")] +pub use c0::*; + +#[cfg(feature = "f0")] +mod f0; +#[cfg(feature = "f0")] +pub use f0::*; + +#[cfg(feature = "f2")] +mod f2; +#[cfg(feature = "f2")] +pub use f2::*; + +#[cfg(feature = "f3")] +mod f3; +#[cfg(feature = "f3")] +pub use f3::*; + +#[cfg(feature = "f4")] mod f4; +#[cfg(feature = "f4")] pub use f4::*; +#[cfg(feature = "f7")] +mod f7; +#[cfg(feature = "f7")] +pub use f7::*; + +#[cfg(feature = "g0")] +mod g0; +#[cfg(feature = "g0")] +pub use g0::*; + +#[cfg(feature = "g4")] +mod g4; +#[cfg(feature = "g4")] +pub use g4::*; + +#[cfg(feature = "h7")] +mod h7; +#[cfg(feature = "h7")] +pub use h7::*; + +#[cfg(feature = "l0")] +mod l0; +#[cfg(feature = "l0")] +pub use l0::*; + +#[cfg(feature = "l1")] +mod l1; +#[cfg(feature = "l1")] +pub use l1::*; + +#[cfg(feature = "l4x")] +mod l4; +#[cfg(feature = "l4x")] +pub use l4::*; + +#[cfg(feature = "l4p")] +mod l4p; +#[cfg(feature = "l4p")] +pub use l4p::*; + +#[cfg(feature = "l5")] +mod l5; +#[cfg(feature = "l5")] +pub use l5::*; + +#[cfg(feature = "u5")] +mod u5; +#[cfg(feature = "u5")] +pub use u5::*; + +#[cfg(feature = "wl")] +mod wl; +#[cfg(feature = "wl")] +pub use wl::*; + +#[cfg(feature = "wb")] +mod wb; +#[cfg(feature = "wb")] +pub use wb::*; + const fn gpiox() -> *const crate::pac::gpioa::RegisterBlock { match P { 'A' => crate::pac::GPIOA::ptr(), 'B' => crate::pac::GPIOB::ptr() as _, + #[cfg(feature = "gpioc")] 'C' => crate::pac::GPIOC::ptr() as _, #[cfg(feature = "gpiod")] 'D' => crate::pac::GPIOD::ptr() as _, @@ -634,6 +717,7 @@ const fn gpiox() -> *const crate::pac::gpioa::RegisterBlock { 'F' => crate::pac::GPIOF::ptr() as _, #[cfg(feature = "gpiog")] 'G' => crate::pac::GPIOG::ptr() as _, + #[cfg(feature = "gpioh")] 'H' => crate::pac::GPIOH::ptr() as _, #[cfg(feature = "gpioi")] 'I' => crate::pac::GPIOI::ptr() as _, diff --git a/src/gpio/alt.rs b/src/gpio/alt.rs index 25b91f92..87dd1472 100644 --- a/src/gpio/alt.rs +++ b/src/gpio/alt.rs @@ -1,6 +1,88 @@ +#[cfg(feature = "c0")] +mod c0; +#[cfg(feature = "c0")] +pub use c0::*; + +#[cfg(feature = "f0")] +mod f0; +#[cfg(feature = "f0")] +pub use f0::*; + +#[cfg(feature = "f2")] +mod f2; +#[cfg(feature = "f2")] +pub use f2::*; + +#[cfg(feature = "f3")] +mod f3; +#[cfg(feature = "f3")] +pub use f3::*; + +#[cfg(feature = "f4")] mod f4; +#[cfg(feature = "f4")] pub use f4::*; +#[cfg(feature = "f7")] +mod f7; +#[cfg(feature = "f7")] +pub use f7::*; + +#[cfg(feature = "g0")] +mod g0; +#[cfg(feature = "g0")] +pub use g0::*; + +#[cfg(feature = "g4")] +mod g4; +#[cfg(feature = "g4")] +pub use g4::*; + +#[cfg(feature = "h7")] +mod h7; +#[cfg(feature = "h7")] +pub use h7::*; + +#[cfg(feature = "l0")] +mod l0; +#[cfg(feature = "l0")] +pub use l0::*; + +#[cfg(feature = "l1")] +mod l1; +#[cfg(feature = "l1")] +pub use l1::*; + +#[cfg(feature = "l4x")] +mod l4; +#[cfg(feature = "l4x")] +pub use l4::*; + +#[cfg(feature = "l4p")] +mod l4p; +#[cfg(feature = "l4p")] +pub use l4p::*; + +#[cfg(feature = "l5")] +mod l5; +#[cfg(feature = "l5")] +pub use l5::*; + +#[cfg(feature = "u5")] +mod u5; +#[cfg(feature = "u5")] +pub use u5::*; + +#[cfg(feature = "wl")] +mod wl; +#[cfg(feature = "wl")] +pub use wl::*; + +#[cfg(feature = "wb")] +mod wb; +#[cfg(feature = "wb")] +pub use wb::*; + macro_rules! extipin { ($( $(#[$attr:meta])* $PX:ident,)*) => { fn make_interrupt_source(&mut self, _syscfg: &mut $crate::syscfg::SysCfg) { @@ -64,6 +146,67 @@ macro_rules! extipin { } use extipin; +#[allow(unused)] +macro_rules! analog { + ( $($(#[$docs:meta])* <$name:ident> for $(no: $NoPin:ident,)? [$( + $(#[$attr:meta])* $PX:ident<$A:literal>, + )*],)*) => { + $( + #[derive(Debug)] + $(#[$docs])* + pub enum $name { + $( + None($NoPin<$Otype>), + )? + + $( + $(#[$attr])* + $PX(gpio::$PX), + )* + } + + impl crate::Sealed for $name { } + + $( + impl From<$NoPin<$Otype>> for $name { + fn from(p: $NoPin<$Otype>) -> Self { + Self::None(p) + } + } + )? + + $( + $(#[$attr])* + impl From> for $name + { + fn from(p: gpio::$PX) -> Self { + Self::$PX(p.into_mode()) + } + } + + $(#[$attr])* + #[allow(irrefutable_let_patterns)] + impl TryFrom<$name> for gpio::$PX + where + MODE: PinMode, + { + type Error = (); + + fn try_from(a: $name) -> Result { + if let $name::$PX(p) = a { + Ok(p.into_mode()) + } else { + Err(()) + } + } + } + )* + )* + }; +} +#[allow(unused)] +use analog; + macro_rules! pin { ( $($(#[$docs:meta])* <$name:ident, $Otype:ident> for $(no: $NoPin:ident,)? [$( $(#[$attr:meta])* $PX:ident<$A:literal $(, Speed::$Speed:ident)?>, diff --git a/src/gpio/alt/c0.rs b/src/gpio/alt/c0.rs new file mode 100644 index 00000000..2590dd99 --- /dev/null +++ b/src/gpio/alt/c0.rs @@ -0,0 +1,838 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod debug { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA13<0>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PA9<6>, + + PB6<6>, + + PB7<14>, + + #[cfg(feature = "gpio-c0xx_453")] + PB8<6>, + ], + + for [ + PA10<6>, + + PB7<6>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<6>, + + PC14<14>, + ], + + for [ + PA1<6>, + + #[cfg(feature = "gpio-c0xx_453")] + PB5<6>, + + PB6<7>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PA12<5>, + ], + } +} + +pub mod i2s1 { + use super::*; + + pin! { + for [ + PA1<0>, + + PA5<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<0>, + + PB6<10>, + ], + + for no:NoPin, [ + PA6<0>, + + PA11<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB4<0>, + + PB6<9>, + ], + + for [ + PA2<0>, + + PA7<0>, + + PA12<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB5<0>, + + PB6<8>, + ], + + for [ + PA4<0>, + + PA8<8>, + + PA14<8>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB0<0>, + ], + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<0>, + + PC14<8>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + + PA9<0>, + + PF2<0>, + ], + + for [ + PA8<15>, + + PA10<3>, + + PA14<11>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<3>, + + #[cfg(feature = "gpio-c0xx_453")] + PB2<3>, + ], + + for [ + PC15<0>, + ], + + for [ + PC15<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PF1<0>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<0>, + + PA11<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB4<0>, + + PB6<9>, + ], + + for no:NoPin, [ + PA2<0>, + + PA7<0>, + + PA12<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB5<0>, + + PB6<8>, + ], + + for [ + PA4<0>, + + PA8<8>, + + PA14<8>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB0<0>, + ], + + for no:NoPin, [ + PA1<0>, + + PA5<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<0>, + + PB6<10>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PA9<4>, + ], + + for no:NoPin, [ + PA10<0>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA0<5>, + + PA5<5>, + + PA8<2>, + + PA14<10>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<2>, + ], + + default:PushPull for [ + PA3<2>, + + PA7<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PB13<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PD2<2>, + ], + + default:PushPull for [ + PA1<5>, + + PA9<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<1>, + + PB6<11>, + ], + + default:PushPull for [ + PA4<2>, + + PA8<9>, + + #[cfg(feature = "gpio-c0xx_453")] + PB0<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PB1<5>, + + #[cfg(feature = "gpio-c0xx_453")] + PB14<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PD3<2>, + ], + + default:PushPull for [ + PA2<5>, + + PA10<2>, + + PB6<1>, + ], + + default:PushPull for [ + PA5<2>, + + PA8<10>, + + #[cfg(feature = "gpio-c0xx_453")] + PB1<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PB15<2>, + ], + + default:PushPull for [ + PA3<5>, + + PA11<2>, + + PB7<1>, + + PF2<1>, + ], + } + + pin! { + for [ + PA6<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PB12<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PC13<2>, + ], + + for [ + PA11<5>, + + #[cfg(feature = "gpio-c0xx_453")] + PB12<1>, + + PC14<2>, + ], + + for [ + PA12<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PC13<1>, + + PC14<1>, + + PC15<2>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB4<1>, + + PB6<12>, + + PB7<11>, + + #[cfg(feature = "gpio-c0xx_453")] + PB8<3>, + + #[cfg(feature = "gpio-c0xx_453")] + PC6<1>, + ], + + default:PushPull for [ + PA7<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<3>, + + #[cfg(feature = "gpio-c0xx_453")] + PB5<1>, + + PB6<13>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<3>, + + #[cfg(feature = "gpio-c0xx_453")] + PC7<1>, + + PC14<11>, + ], + + default:PushPull for [ + PA8<11>, + + #[cfg(feature = "gpio-c0xx_453")] + PB0<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB5<3>, + + PB6<3>, + + PC15<3>, + ], + + default:PushPull for [ + PA8<12>, + + #[cfg(feature = "gpio-c0xx_453")] + PB1<1>, + + PB7<3>, + ], + } + + pin! { + for [ + PA2<3>, + + PA9<3>, + + PA13<3>, + + #[cfg(feature = "gpio-c0xx_453")] + PD2<1>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA4<4>, + + PA7<4>, + + PA8<13>, + + #[cfg(feature = "gpio-c0xx_453")] + PB1<0>, + + #[cfg(feature = "gpio-c0xx_453")] + PF0<2>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim15 { + use super::*; + + pin! { + for [ + PA9<5>, + ], + } + + use crate::pac::TIM15 as TIM; +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PA6<5>, + + PB7<10>, + + #[cfg(feature = "gpio-c0xx_453")] + PB8<2>, + + #[cfg(feature = "gpio-c0xx_453")] + PD0<2>, + ], + + default:PushPull for [ + PA2<2>, + + PB6<2>, + ], + } + + pin! { + for [ + #[cfg(feature = "gpio-c0xx_453")] + PB5<2>, + + PB6<14>, + ], + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA1<2>, + + PA7<5>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<2>, + + PC14<10>, + + #[cfg(feature = "gpio-c0xx_453")] + PD1<2>, + ], + + default:PushPull for [ + PA4<5>, + + PB7<2>, + ], + } + + pin! { + for [ + PA10<5>, + ], + + for [ + PA10<5>, + + #[cfg(feature = "gpio-c0xx_453")] + PB4<5>, + + PB6<15>, + ], + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA12<1>, + + PA14<12>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<4>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<4>, + + PB6<4>, + ], + + for [ + PA11<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB4<4>, + + PB6<5>, + ], + + for [ + PA12<1>, + + PA14<12>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<4>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<4>, + + PB6<4>, + ], + + for [ + PA11<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB4<4>, + + PB6<5>, + ], + + for [ + PA12<1>, + + PA14<12>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<4>, + + #[cfg(feature = "gpio-c0xx_453")] + PB3<4>, + + PB6<4>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<4>, + + PA8<14>, + + PA10<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB2<0>, + + PB7<0>, + ], + + default:PushPull for no:NoPin, [ + PA0<4>, + + PA9<1>, + + PB6<0>, + + PC14<0>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA1<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<1>, + + PC14<9>, + ], + + for [ + PA0<1>, + + PB7<9>, + + #[cfg(feature = "gpio-c0xx_453")] + PB8<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PD3<0>, + ], + + for [ + PA1<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<1>, + + PC14<9>, + ], + + for [ + PA0<1>, + + PB7<9>, + + #[cfg(feature = "gpio-c0xx_453")] + PB8<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PD3<0>, + ], + + for [ + PA1<1>, + + #[cfg(feature = "gpio-c0xx_453")] + PB9<1>, + + PC14<9>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<1>, + + PA5<1>, + + PA13<4>, + + PA14<9>, + + #[cfg(feature = "gpio-c0xx_453")] + PA15<1>, + ], + + default:PushPull for no:NoPin, [ + PA2<1>, + + PA4<1>, + + PA8<1>, + + PA14<1>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} diff --git a/src/gpio/alt/f0.rs b/src/gpio/alt/f0.rs new file mode 100644 index 00000000..ee866197 --- /dev/null +++ b/src/gpio/alt/f0.rs @@ -0,0 +1,1598 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +#[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] +pub mod can { + use super::*; + + pin! { + for no:NoPin, [ + PA11<4>, + + PB8<4>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD0<0>, + ], + + for no:NoPin, [ + PA12<4>, + + PB9<4>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD1<0>, + ], + } + impl CanCommon for crate::pac::CAN { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] +pub mod comp1 { + use super::*; + + analog! { + for [ + #[cfg(feature = "gpio-f051")] + PA0<7>, + + #[cfg(feature = "gpio-f051")] + PA4<7>, + + #[cfg(feature = "gpio-f051")] + PA5<7>, + ], + + for [ + #[cfg(feature = "gpio-f051")] + PA1<7>, + ], + } + + pin! { + for [ + PA0<7>, + + PA6<7>, + + PA11<7>, + ], + } +} + +#[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] +pub mod comp2 { + use super::*; + + analog! { + for [ + #[cfg(feature = "gpio-f051")] + PA2<7>, + + #[cfg(feature = "gpio-f051")] + PA4<7>, + + #[cfg(feature = "gpio-f051")] + PA5<7>, + ], + + for [ + #[cfg(feature = "gpio-f051")] + PA3<7>, + ], + } + + pin! { + for [ + PA2<7>, + + PA7<7>, + + PA12<7>, + ], + } +} + +/*#[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] +pub mod crs { + use super::*; + + pin! { + for [ + PA8<4>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD15<0>, + + PF0<0>, + ], + } +}*/ + +#[cfg(feature = "gpio-f031")] +pub mod hdmi_cec { + use super::*; + + pin! { + for [ + PA5<1>, + + PB8<2>, + + PB10<2>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-f031", feature = "gpio-f042", feature = "gpio-f091"))] + PA9<4>, + + #[cfg(feature = "gpio-f042")] + PA11<5>, + + PB6<1>, + + PB8<1>, + + #[cfg(any(feature = "gpio-f031", feature = "gpio-f042"))] + PB10<1>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f091"))] + PF1<1>, + ], + + for [ + #[cfg(any(feature = "gpio-f031", feature = "gpio-f042", feature = "gpio-f091"))] + PA10<4>, + + #[cfg(feature = "gpio-f042")] + PA12<5>, + + PB7<1>, + + PB9<1>, + + #[cfg(any(feature = "gpio-f031", feature = "gpio-f042"))] + PB11<1>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f091"))] + PF0<1>, + ], + + for [ + PB5<3>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f091")] + PA11<5>, + + #[cfg(any( + feature = "gpio-f031", + feature = "gpio-f051", + feature = "gpio-f052", + feature = "gpio-f091" + ))] + PB10<1>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] + PB13<5>, + ], + + for [ + #[cfg(feature = "gpio-f091")] + PA12<5>, + + #[cfg(any( + feature = "gpio-f031", + feature = "gpio-f051", + feature = "gpio-f052", + feature = "gpio-f091" + ))] + PB11<1>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] + PB14<5>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s1 { + use super::*; + + pin! { + for [ + PA5<0>, + + PB3<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE13<1>, + ], + + for no:NoPin, [ + PA6<0>, + + PB4<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE14<1>, + ], + + for [ + PA7<0>, + + PB5<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE15<1>, + ], + + for [ + PA4<0>, + + PA15<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE12<1>, + ], + } +} + +#[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] +pub mod i2s2 { + use super::*; + + pin! { + for [ + PB10<5>, + + PB13<0>, + + PD1<1>, + ], + + for no:NoPin, [ + PB14<0>, + + PC2<1>, + + PD3<1>, + ], + + for [ + PB15<0>, + + PC3<1>, + + PD4<1>, + ], + + for [ + PB9<5>, + + PB12<0>, + + PD0<1>, + ], + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + PB9<0>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f091"))] + PA9<5>, + ], + } +} + +#[cfg(any(feature = "gpio-f031", feature = "gpio-f051"))] +pub mod rtc { + use super::*; + + pin! { + for [ + PB15<0>, + ], + + for [ + PA0<0>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<0>, + + PB4<0>, + + #[cfg(feature = "gpio-f031")] + PB14<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE14<1>, + ], + + for no:NoPin, [ + PA7<0>, + + PB5<0>, + + #[cfg(feature = "gpio-f031")] + PB15<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE15<1>, + ], + + for [ + PA4<0>, + + PA15<0>, + + #[cfg(feature = "gpio-f031")] + PB12<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE12<1>, + ], + + for no:NoPin, [ + PA5<0>, + + PB3<0>, + + #[cfg(feature = "gpio-f031")] + PB13<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE13<1>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PC2<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD3<1>, + ], + + for no:NoPin, [ + PB15<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PC3<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD4<1>, + ], + + for [ + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] + PB9<5>, + + PB12<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD0<1>, + ], + + for no:NoPin, [ + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] + PB10<5>, + + PB13<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD1<1>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f052")] + PC15<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC14<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC14<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PD8<4>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC0<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC13<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PD4<4>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PD3<4>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC1<7>, + ], + + for [ + PA14<0>, + ], + + for [ + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] + PA13<0>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC3<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC6<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC9<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC10<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC11<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC12<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC7<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC8<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC5<7>, + ], + + for [ + #[cfg(feature = "gpio-f052")] + PC2<7>, + ], + + for [ + #[cfg(any(feature = "gpio-f031", feature = "gpio-f051"))] + PA0<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE9<0>, + ], + + default:PushPull for [ + PA7<2>, + + PB13<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE8<0>, + ], + + default:PushPull for [ + PA9<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE11<0>, + ], + + default:PushPull for [ + PB0<2>, + + PB14<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE10<0>, + ], + + default:PushPull for [ + PA10<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE13<0>, + ], + + default:PushPull for [ + PB1<2>, + + PB15<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE12<0>, + ], + + default:PushPull for [ + PA11<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE14<0>, + ], + } + + pin! { + for [ + PA6<2>, + + PB12<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE15<0>, + ], + + for [ + PA12<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE7<0>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PA5<2>, + + PA15<2>, + ], + + default:PushPull for [ + PA1<2>, + + PB3<2>, + ], + + default:PushPull for [ + PA2<2>, + + PB10<2>, + ], + + default:PushPull for [ + PA3<2>, + + PB11<2>, + ], + } + + pin! { + for [ + PA0<2>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<1>, + + PB4<1>, + + #[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] + PC6<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE3<0>, + ], + + default:PushPull for [ + PA7<1>, + + PB5<1>, + + #[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] + PC7<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE4<0>, + ], + + default:PushPull for [ + PB0<1>, + + #[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] + PC8<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE5<0>, + ], + + default:PushPull for [ + PB1<1>, + + #[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] + PC9<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE6<0>, + ], + } + + pin! { + for [ + #[cfg(any(feature = "gpio-f051", feature = "gpio-f052", feature = "gpio-f091"))] + PD2<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE2<0>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA4<4>, + + PA7<4>, + + PB1<0>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +#[cfg(any( + feature = "gpio-f031", + feature = "gpio-f051", + feature = "gpio-f052", + feature = "gpio-f091" +))] +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<0>, + + PB14<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PF9<0>, + ], + + default:PushPull for [ + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PA1<5>, + + PB15<3>, + ], + + default:PushPull for [ + PA3<0>, + + PB15<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PF10<0>, + ], + } + + pin! { + for [ + PA9<0>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PB12<5>, + ], + + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<5>, + + PB8<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE0<0>, + ], + + default:PushPull for [ + PB6<2>, + ], + } + + pin! { + for [ + PB5<2>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<5>, + + PB9<2>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PE1<0>, + ], + + default:PushPull for [ + PB7<2>, + ], + } + + pin! { + for [ + PA10<0>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] + PB4<5>, + ], + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tsc { + use super::*; + + pin! { + for [ // Low speed + PB8<3>, + + PB10<3>, + ], + } + + pin! { + default:PushPull for [ + PA0<3>, + ], + + default:PushPull for [ + PA1<3>, + ], + + default:PushPull for [ + PA2<3>, + ], + + default:PushPull for [ + PA3<3>, + ], + + default:PushPull for [ + PA4<3>, + ], + + default:PushPull for [ + PA5<3>, + ], + + default:PushPull for [ + PA6<3>, + ], + + default:PushPull for [ + PA7<3>, + ], + + default:PushPull for [ + PB0<3>, + ], + + default:PushPull for [ + PB1<3>, + ], + + default:PushPull for [ + PB2<3>, + ], + + default:PushPull for [ + PA9<3>, + ], + + default:PushPull for [ + PA10<3>, + ], + + default:PushPull for [ + PA11<3>, + ], + + default:PushPull for [ + PA12<3>, + ], + + default:PushPull for [ + PB3<3>, + ], + + default:PushPull for [ + PB4<3>, + ], + + default:PushPull for [ + PB6<3>, + ], + + default:PushPull for [ + PB7<3>, + ], + } + + #[cfg(any( + feature = "gpio-f031", + feature = "gpio-f051", + feature = "gpio-f052", + feature = "gpio-f091" + ))] + pin! { + default:PushPull for [ + PB11<3>, + ], + + default:PushPull for [ + PB12<3>, + ], + + default:PushPull for [ + PB13<3>, + ], + + default:PushPull for [ + PB14<3>, + ], + } + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + pin! { + default:PushPull for [ + PC5<0>, + ], + + default:PushPull for [ + PE2<1>, + ], + + default:PushPull for [ + PE3<1>, + ], + + default:PushPull for [ + PE4<1>, + ], + + default:PushPull for [ + PE5<1>, + ], + + default:PushPull for [ + PD12<1>, + ], + + default:PushPull for [ + PD13<1>, + ], + + default:PushPull for [ + PD14<1>, + ], + + default:PushPull for [ + PD15<1>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f031")] + PA4<1>, + + PA8<1>, + ], + + for [ + #[cfg(feature = "gpio-f031")] + PA0<1>, + + PA11<1>, + ], + + for [ + #[cfg(feature = "gpio-f031")] + PA1<1>, + + PA12<1>, + ], + + for [ + #[cfg(feature = "gpio-f031")] + PA1<1>, + + PA12<1>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f031")] + PA3<1>, + + PA10<1>, + + #[cfg(feature = "gpio-f031")] + PA15<1>, + + PB7<0>, + ], + + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f031")] + PA2<1>, + + PA9<1>, + + #[cfg(feature = "gpio-f031")] + PA14<1>, + + PB6<0>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD7<0>, + ], + + for [ + PA0<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD3<0>, + ], + + for [ + PA1<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD4<0>, + ], + + for [ + PA1<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD4<0>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<1>, + + PA15<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD6<0>, + ], + + default:PushPull for no:NoPin, [ + PA2<1>, + + PA14<1>, + + #[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] + PD5<0>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] +pub mod usart3 { + use super::*; + + pin! { + for [ + PB0<4>, + + PB12<4>, + + PC12<1>, + + PD10<0>, + ], + + for [ + PA6<4>, + + PB13<4>, + + PD11<0>, + ], + + for [ + PB1<4>, + + PB14<4>, + + PD2<1>, + + PD12<0>, + ], + + for [ + PB1<4>, + + PB14<4>, + + PD2<1>, + + PD12<0>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<4>, + + PC5<1>, + + PC11<1>, + + PD9<0>, + ], + + default:PushPull for no:NoPin, [ + PB10<4>, + + PC4<1>, + + PC10<1>, + + PD8<0>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-f052", feature = "gpio-f091"))] +pub mod usart4 { + use super::*; + + pin! { + for [ + PC12<0>, + ], + + for [ + PB7<4>, + ], + + for [ + PA15<4>, + ], + + for [ + PA15<4>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<4>, + + PC11<0>, + + #[cfg(feature = "gpio-f091")] + PE9<1>, + ], + + default:PushPull for no:NoPin, [ + PA0<4>, + + PC10<0>, + + #[cfg(feature = "gpio-f091")] + PE8<1>, + ], + } + use crate::pac::USART4 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-f091")] +pub mod usart5 { + use super::*; + + pin! { + for [ + PB5<4>, + + PE7<1>, + ], + + for [ + PB5<4>, + + PE7<1>, + ], + + for [ + PB5<4>, + + PE7<1>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB4<4>, + + PD2<2>, + + PE11<1>, + ], + + default:PushPull for no:NoPin, [ + PB3<4>, + + PC12<2>, + + PE10<1>, + ], + } + use crate::pac::USART5 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } +} + +#[cfg(feature = "gpio-f091")] +pub mod usart6 { + use super::*; + + pin! { + for [ + PF3<2>, + ], + + for [ + PF3<2>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA5<5>, + + PC1<2>, + + PF10<1>, + ], + + default:PushPull for no:NoPin, [ + PA4<5>, + + PC0<2>, + + PF9<1>, + ], + } + use crate::pac::USART6 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } +} + +#[cfg(feature = "gpio-f091")] +pub mod usart7 { + use super::*; + + pin! { + for [ + PD15<2>, + + PF2<2>, + ], + + for [ + PD15<2>, + + PF2<2>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC1<1>, + + PC7<1>, + + PF3<1>, + ], + + default:PushPull for no:NoPin, [ + PC0<1>, + + PC6<1>, + + PF2<1>, + ], + } + use crate::pac::USART7 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } +} + +#[cfg(feature = "gpio-f091")] +pub mod usart8 { + use super::*; + + pin! { + for [ + PD12<2>, + ], + + for [ + PD12<2>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC3<2>, + + PC9<1>, + + PD14<0>, + ], + + default:PushPull for no:NoPin, [ + PC2<2>, + + PC8<1>, + + PD13<0>, + ], + } + use crate::pac::USART8 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } +} + +#[cfg(any(feature = "gpio-f042", feature = "gpio-f052", feature = "gpio-f091"))] +pub mod usb { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f042")] + PA4<2>, + + #[cfg(any(feature = "gpio-f042", feature = "gpio-f052"))] + PA13<2>, + + #[cfg(feature = "gpio-f042")] + PA15<5>, + ], + + for [ + #[cfg(feature = "gpio-f091")] + PA13<2>, + ], + } +} diff --git a/src/gpio/alt/f2.rs b/src/gpio/alt/f2.rs new file mode 100644 index 00000000..6cd38ed5 --- /dev/null +++ b/src/gpio/alt/f2.rs @@ -0,0 +1,1905 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod can1 { + use super::*; + + pin! { + for no:NoPin, [ + PA11<9>, + + PB8<9>, + + PD0<9>, + + PI9<9>, + ], + + for no:NoPin, [ + PA12<9>, + + PB9<9>, + + PD1<9>, + + PH13<9>, + ], + } + impl CanCommon for crate::pac::CAN1 { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod can2 { + use super::*; + + pin! { + for no:NoPin, [ + PB5<9>, + + PB12<9>, + ], + + for no:NoPin, [ + PB6<9>, + + PB13<9>, + ], + } + impl CanCommon for crate::pac::CAN2 { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod dcmi { + use super::*; + + pin! { + for [ + PA9<13>, + + PC6<13>, + + PH9<13>, + ], + + for [ + PA10<13>, + + PC7<13>, + + PH10<13>, + ], + + for [ + PB5<13>, + + PI3<13>, + ], + + for [ + PD2<13>, + + PH15<13>, + ], + + for [ + PF11<13>, + ], + + for [ + PG15<13>, + + PI0<13>, + ], + + for [ + PC8<13>, + + PE0<13>, + + PH11<13>, + ], + + for [ + PC9<13>, + + PE1<13>, + + PH12<13>, + ], + + for [ + PC11<13>, + + PE4<13>, + + PH14<13>, + ], + + for [ + PB6<13>, + + PI4<13>, + ], + + for [ + PB8<13>, + + PE5<13>, + + PI6<13>, + ], + + for [ + PB9<13>, + + PE6<13>, + + PI7<13>, + ], + + for [ + PC10<13>, + + PI1<13>, + ], + + for [ + PC12<13>, + + PI2<13>, + ], + + for [ + PA4<13>, + + PH8<13>, + ], + + for [ + PA6<13>, + ], + + for [ + PB7<13>, + + PI5<13>, + ], + } +} + +pub mod eth { + use super::*; + + pin! { + for [ + PA3<11>, + + PH3<11>, + ], + + for [ + PA0<11>, + + PH2<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PC1<11>, + ], + + for [ + PA2<11>, + ], + + for [ + PB5<11>, + + PG8<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PB10<11>, + + PI10<11>, + ], + + for [ + PC4<11>, + ], + + for [ + PC5<11>, + ], + + for [ + PB0<11>, + + PH6<11>, + ], + + for [ + PB1<11>, + + PH7<11>, + ], + + for [ + PC3<11>, + ], + + for [ + PB11<11>, + + PG11<11>, + ], + + for [ + PB12<11>, + + PG13<11>, + ], + + for [ + PB13<11>, + + PG14<11>, + ], + + for [ + PC2<11>, + ], + + for [ + PB8<11>, + + PE2<11>, + ], + } +} + +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PF9<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PG6<12, Speed::VeryHigh>, + ], + + for [ + PG7<12, Speed::VeryHigh>, + ], + + for [ + PF10<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG11<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PF6<12, Speed::VeryHigh>, + ], + + for [ + PF8<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PF7<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + ], + + for [ + PB7<4>, + + PB9<4>, + ], + + for [ + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PF1<4>, + + PH4<4>, + ], + + for [ + PB11<4>, + + PF0<4>, + + PH5<4>, + ], + + for [ + PB12<4>, + + PF2<4>, + + PH6<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA8<4>, + + PH7<4>, + ], + + for [ + PC9<4>, + + PH8<4>, + ], + + for [ + PA9<4>, + + PH9<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PC9<5>, + ], + } +} + +pub mod i2s2 { + use super::*; + + pin! { + for no:NoPin, [ + PC6<5>, + ], + + for [ + PB10<5>, + + PB13<5>, + + PI1<5>, + ], + + for [ + PB15<5>, + + PC3<5>, + + PI3<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + PI0<5>, + ], + } +} + +pub mod i2s3 { + use super::*; + + pin! { + for no:NoPin, [ + PC7<6>, + ], + + for [ + PB3<6>, + + PC10<6>, + ], + + for [ + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + + for [ + PC9<0>, + ], + + for [ + PC14<0>, + ], + + for [ + PC15<0>, + ], + + for [ + PH0<0>, + ], + + for [ + PH1<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PC13<0>, + ], + + for [ + PB15<0>, + ], + } +} + +pub mod sdio { + use super::*; + + pin! { + for [ + PC12<12, Speed::VeryHigh>, + ], + + for [ + PD2<12, Speed::VeryHigh>, + ], + + for [ + PC8<12, Speed::VeryHigh>, + ], + + for [ + PC9<12, Speed::VeryHigh>, + ], + + for [ + PC10<12, Speed::VeryHigh>, + ], + + for [ + PC11<12, Speed::VeryHigh>, + ], + + for [ + PB8<12, Speed::VeryHigh>, + ], + + for [ + PB9<12, Speed::VeryHigh>, + ], + + for [ + PC6<12, Speed::VeryHigh>, + ], + + for [ + PC7<12, Speed::VeryHigh>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PB4<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PB5<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + ], + + for no:NoPin, [ + PA5<5>, + + PB3<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + PI2<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC3<5>, + + PI3<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + PI0<5>, + ], + + for no:NoPin, [ + PB10<5>, + + PB13<5>, + + PI1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + PE2<0>, + ], + + for [ + PE3<0>, + ], + + for [ + PE4<0>, + ], + + for [ + PE5<0>, + ], + + for [ + PE6<0>, + ], + + for [ + PA0<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + PE9<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + PE8<1>, + ], + + default:PushPull for [ + PA9<1>, + + PE11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + PE10<1>, + ], + + default:PushPull for [ + PA10<1>, + + PE13<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + PE12<1>, + ], + + default:PushPull for [ + PA11<1>, + + PE14<1>, + ], + } + + pin! { + for [ + PA6<1>, + + PB12<1>, + + PE15<1>, + ], + + for [ + PA12<1>, + + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + ], + } + + pin! { + for [ + PD2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PH10<2>, + ], + + default:PushPull for [ + PA1<2>, + + PH11<2>, + ], + + default:PushPull for [ + PA2<2>, + + PH12<2>, + ], + + default:PushPull for [ + PA3<2>, + + PI0<2>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + + PI5<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + + PH13<3>, + ], + + default:PushPull for [ + PC7<3>, + + PI6<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + + PH14<3>, + ], + + default:PushPull for [ + PC8<3>, + + PI7<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + + PH15<3>, + ], + + default:PushPull for [ + PC9<3>, + + PI2<3>, + ], + } + + pin! { + for [ + PA6<3>, + + PI4<3>, + ], + + for [ + PA0<3>, + + PI3<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim9 { + use super::*; + + pin! { + default:PushPull for [ + PA2<3>, + + PE5<3>, + ], + + default:PushPull for [ + PA3<3>, + + PE6<3>, + ], + } + + use crate::pac::TIM9 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim10 { + use super::*; + + pin! { + default:PushPull for [ + PB8<3>, + + PF6<3>, + ], + } + + use crate::pac::TIM10 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim11 { + use super::*; + + pin! { + default:PushPull for [ + PB9<3>, + + PF7<3>, + ], + } + + use crate::pac::TIM11 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim12 { + use super::*; + + pin! { + default:PushPull for [ + PB14<9>, + + PH6<9>, + ], + + default:PushPull for [ + PB15<9>, + + PH9<9>, + ], + } + + use crate::pac::TIM12 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim13 { + use super::*; + + pin! { + default:PushPull for [ + PA6<9>, + + PF8<9>, + ], + } + + use crate::pac::TIM13 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA7<9>, + + PF9<9>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod uart4 { + use super::*; + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + PC11<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + PC10<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod uart5 { + use super::*; + + pin! { + default:PushPull for no:NoPin, [ + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart6 { + use super::*; + + pin! { + for [ + PC8<8>, + + PG7<8>, + ], + + for [ + PG13<8>, + + PG15<8>, + ], + + for [ + PG8<8>, + + PG12<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC7<8>, + + PG9<8>, + ], + + default:PushPull for no:NoPin, [ + PC6<8>, + + PG14<8>, + ], + } + use crate::pac::USART6 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod otg_fs { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA10<10>, + ], + + for [ + PA8<10>, + ], + } +} + +pub mod otg_hs { + use super::*; + + pin! { + for [ + PB14<12>, + ], + + for [ + PB15<12>, + ], + + for [ + PB12<12>, + ], + + for [ + PA4<12>, + ], + + for [ + PA5<10, Speed::VeryHigh>, + ], + + for [ + PA3<10, Speed::VeryHigh>, + ], + + for [ + PB0<10, Speed::VeryHigh>, + ], + + for [ + PB1<10, Speed::VeryHigh>, + ], + + for [ + PB10<10, Speed::VeryHigh>, + ], + + for [ + PB11<10, Speed::VeryHigh>, + ], + + for [ + PB12<10, Speed::VeryHigh>, + ], + + for [ + PB13<10, Speed::VeryHigh>, + ], + + for [ + PB5<10, Speed::VeryHigh>, + ], + + for [ + PC2<10, Speed::VeryHigh>, + + PI11<10, Speed::VeryHigh>, + ], + + for [ + PC3<10, Speed::VeryHigh>, + + PH4<10, Speed::VeryHigh>, + ], + + for [ + PC0<10, Speed::VeryHigh>, + ], + + for [ + PB13<12, Speed::VeryHigh>, + ], + } +} diff --git a/src/gpio/alt/f3.rs b/src/gpio/alt/f3.rs new file mode 100644 index 00000000..13362ec2 --- /dev/null +++ b/src/gpio/alt/f3.rs @@ -0,0 +1,2712 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod can { + use super::*; + + pin! { + for no:NoPin, [ + PA11<9>, + + PB8<9>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD0<7>, + ], + + for no:NoPin, [ + PA12<9>, + + PB9<9>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD1<7>, + ], + } + impl CanCommon for crate::pac::CAN { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] +pub mod comp1 { + use super::*; + + pin! { + for [ + PA0<8>, + + PA6<8>, + + PA11<8>, + + PB8<8>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PF4<2>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PA2<8>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f373"))] + PA7<8>, + + PA12<8>, + + PB9<8>, + ], + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod comp3 { + use super::*; + + pin! { + for [ + PA8<8>, + + PC8<7>, + ], + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" +))] +pub mod comp4 { + use super::*; + + pin! { + for [ + PB1<8>, + ], + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod comp5 { + use super::*; + + pin! { + for [ + PA9<8>, + + PC7<7>, + ], + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" +))] +pub mod comp6 { + use super::*; + + pin! { + for [ + PA10<8>, + + PC6<7>, + ], + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod comp7 { + use super::*; + + pin! { + for [ + PC2<3>, + ], + } +} + +#[cfg(feature = "gpio-f303e")] +pub mod fmc { + use super::*; + + pin! { + for [ + PH0<12, Speed::VeryHigh>, + ], + + for [ + PH1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PF9<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PG6<12, Speed::VeryHigh>, + ], + + for [ + PG7<12, Speed::VeryHigh>, + ], + + for [ + PF10<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG11<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PF6<12, Speed::VeryHigh>, + ], + + for [ + PF8<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PF7<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +#[cfg(feature = "gpio-f333")] +pub mod hrtim1 { + use super::*; + + pin! { + for [ // High speed + PA8<13>, + ], + + for [ + PA9<13>, + ], + + for [ + PA10<13>, + ], + + for [ + PA11<13>, + ], + + for [ + PB12<13>, + ], + + for [ + PB13<13>, + ], + + for [ + PB14<13>, + ], + + for [ + PB15<13>, + ], + + for [ + PC8<3>, + ], + + for [ + PC9<3>, + ], + + for [ // Low speed + PC12<3>, + ], + + for [ + PC6<3>, + ], + + for [ + PC11<3>, + ], + + for [ + PB7<13>, + ], + + for [ + PB6<13>, + ], + + for [ + PB9<13>, + ], + + for [ + PB5<13>, + ], + + for [ + PB4<13>, + ], + + for [ + PB8<13>, + ], + + for [ + PB3<13>, + ], + + for [ + PA12<13>, + ], + + for [ + PA15<13>, + ], + + for [ + PB10<13>, + ], + + for [ + PB11<13>, + ], + + for [ + PC7<3>, + ], + + for [ + PB2<13>, + + PB6<12>, + ], + } + + pin! { + default:PushPull for [ // High speed + PB1<13>, + + PB3<12>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PA15<4>, + + PB6<4>, + + PB8<4>, + ], + + for [ + PA14<4>, + + PB7<4>, + + PB9<4>, + ], + + for [ + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f373" +))] +pub mod i2c2 { + use super::*; + + pin! { + for [ + PA9<4>, + + PF1<4>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PF6<4>, + ], + + for [ + PA10<4>, + + PF0<4>, + + #[cfg(feature = "gpio-f373")] + PF7<4>, + ], + + for [ + PA8<4>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB12<4>, + + #[cfg(feature = "gpio-f373")] + PF2<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA8<3>, + ], + + for [ + PB5<8>, + + PC9<3>, + ], + + for [ + PA9<2>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod i2s { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PA12<5>, + + PC9<5>, + ], + } +} + +#[cfg(feature = "gpio-f373")] +pub mod i2s1 { + use super::*; + + pin! { + for [ + PA5<5>, + + PA12<6>, + + PB3<5>, + + PC7<5>, + ], + + for no:NoPin, [ + PA6<5>, + + PA13<6>, + + PB4<5>, + + PC8<5>, + ], + + for [ + PA7<5>, + + PB0<5>, + + PB5<5>, + + PC9<5>, + + PF6<5>, + ], + + for [ + PA4<5>, + + PA11<6>, + + PA15<5>, + + PC6<5>, + ], + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f373" +))] +pub mod i2s2 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f373")] + PA8<5>, + + #[cfg(feature = "gpio-f373")] + PB8<5>, + + #[cfg(feature = "gpio-f373")] + PB10<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB13<5>, + + #[cfg(feature = "gpio-f373")] + PD7<5>, + + #[cfg(feature = "gpio-f373")] + PD8<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PF1<5>, + ], + + for [ + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PA10<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB14<5>, + ], + + for no:NoPin, [ + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PA8<5>, + + #[cfg(feature = "gpio-f373")] + PA9<5>, + + #[cfg(feature = "gpio-f373")] + PB14<5>, + + #[cfg(feature = "gpio-f373")] + PC2<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PC6<6>, + + #[cfg(feature = "gpio-f373")] + PD3<5>, + ], + + for [ + #[cfg(feature = "gpio-f373")] + PA10<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PA11<5>, + + PB15<5>, + + #[cfg(feature = "gpio-f373")] + PC3<5>, + + #[cfg(feature = "gpio-f373")] + PD4<5>, + ], + + for [ + #[cfg(feature = "gpio-f373")] + PA11<5>, + + #[cfg(feature = "gpio-f373")] + PB9<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB12<5>, + + #[cfg(feature = "gpio-f373")] + PD6<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PF0<5>, + ], + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f373" +))] +pub mod i2s3 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f373")] + PA1<6>, + + PB3<6>, + + PC10<6>, + ], + + for [ + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB4<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PC11<6>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA2<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PA9<5>, + + #[cfg(feature = "gpio-f373")] + PB4<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PC7<6>, + + #[cfg(feature = "gpio-f373")] + PC11<6>, + ], + + for [ + #[cfg(feature = "gpio-f373")] + PA3<6>, + + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<5>, + + PB9<6>, + ], + } +} + +/*#[cfg(feature = "gpio-f333")] +pub mod opamp2 { + use super::*; + + pin! { + for [ + PA6<13>, + ], + } +}*/ + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f373" +))] +pub mod rtc { + use super::*; + + pin! { + for [ + PA1<0>, + + PB15<0>, + ], + } +} + +#[cfg(any( + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333", + feature = "gpio-f373" +))] +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + #[cfg(feature = "gpio-f373")] + PA13<6>, + + PB4<5>, + + #[cfg(feature = "gpio-f373")] + PC8<5>, + ], + + for no:NoPin, [ + PA7<5>, + + #[cfg(feature = "gpio-f373")] + PB0<5>, + + PB5<5>, + + #[cfg(feature = "gpio-f373")] + PC9<5>, + + #[cfg(feature = "gpio-f373")] + PF6<5>, + ], + + for [ + PA4<5>, + + #[cfg(feature = "gpio-f373")] + PA11<6>, + + PA15<5>, + + #[cfg(feature = "gpio-f373")] + PC6<5>, + ], + + for no:NoPin, [ + PA5<5>, + + #[cfg(feature = "gpio-f373")] + PA12<6>, + + PB3<5>, + + #[cfg(feature = "gpio-f373")] + PC7<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f373" +))] +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA9<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PA10<5>, + + PB14<5>, + + #[cfg(feature = "gpio-f373")] + PC2<5>, + + #[cfg(feature = "gpio-f373")] + PD3<5>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA10<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PA11<5>, + + PB15<5>, + + #[cfg(feature = "gpio-f373")] + PC3<5>, + + #[cfg(feature = "gpio-f373")] + PD4<5>, + ], + + for [ + #[cfg(feature = "gpio-f373")] + PA11<5>, + + #[cfg(feature = "gpio-f373")] + PB9<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB12<5>, + + #[cfg(feature = "gpio-f373")] + PD6<5>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PD15<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PF0<5>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA8<5>, + + #[cfg(feature = "gpio-f373")] + PB8<5>, + + #[cfg(feature = "gpio-f373")] + PB10<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303", feature = "gpio-f303e"))] + PB13<5>, + + #[cfg(feature = "gpio-f373")] + PD7<5>, + + #[cfg(feature = "gpio-f373")] + PD8<5>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e"))] + PF1<5>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PF9<5>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PF10<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f373" +))] +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA2<6>, + + PB4<6>, + + PC11<6>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA3<6>, + + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PA1<6>, + + PB3<6>, + + PC10<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(feature = "gpio-f303e")] +pub mod spi4 { + use super::*; + + pin! { + for no:NoPin, [ + PE5<5>, + + PE13<5>, + ], + + for no:NoPin, [ + PE6<5>, + + PE14<5>, + ], + + for [ + PE3<5>, + + PE4<5>, + + PE11<5>, + ], + + for no:NoPin, [ + PE2<5>, + + PE12<5>, + ], + } + impl SpiCommon for crate::pac::SPI4 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE2<0>, + ], + + for [ + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE3<0>, + ], + + for [ + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE4<0>, + ], + + for [ + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE5<0>, + ], + + for [ + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE6<0>, + ], + } +} + +#[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" +))] +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PC0<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE9<2>, + ], + + default:PushPull for [ + PA7<6>, + + PA11<6>, + + PB13<6>, + + PC13<4>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE8<2>, + ], + + default:PushPull for [ + PA9<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PC1<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE11<2>, + ], + + default:PushPull for [ + PA12<6>, + + PB0<6>, + + PB14<6>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE10<2>, + ], + + default:PushPull for [ + PA10<6>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PC2<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE13<2>, + ], + + default:PushPull for [ + PB1<6>, + + PB15<4>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE12<2>, + + PF0<6>, + ], + + default:PushPull for [ + PA11<11>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PC3<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE14<2>, + ], + } + + pin! { + for [ + PA6<6>, + + PA14<6>, + + PA15<9>, + + PB8<12>, + + PB12<6>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE15<2>, + ], + + for [ + PA11<12>, + + PC3<6>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE14<6>, + ], + + for [ + PA12<11>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PC4<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE7<2>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PD3<2>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PD4<2>, + ], + + default:PushPull for [ + PA2<1>, + + PA9<10>, + + PB10<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PD7<2>, + ], + + default:PushPull for [ + PA3<1>, + + PA10<10>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB11<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PD6<2>, + ], + } + + pin! { + for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PD3<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any( + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333", + feature = "gpio-f373" +))] +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE2<2>, + ], + + default:PushPull for [ + PA4<2>, + + PA7<2>, + + #[cfg(feature = "gpio-f373")] + PB0<10>, + + PB5<2>, + + PC7<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE3<2>, + ], + + default:PushPull for [ + PB0<2>, + + #[cfg(feature = "gpio-f373")] + PB6<10>, + + PC8<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE4<2>, + ], + + default:PushPull for [ + PB1<2>, + + PB7<10>, + + PC9<2>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE5<2>, + ], + } + + pin! { + for [ + PB3<10>, + + PD2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PA11<10>, + + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PA12<10>, + + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PA13<10>, + + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + + PF6<2>, + ], + } + + pin! { + for [ + PA8<10>, + + PB3<2>, + + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-f373")] +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PA8<2>, + + PC0<2>, + ], + + default:PushPull for [ + PA1<2>, + + PA11<2>, + + PC1<2>, + ], + + default:PushPull for [ + PA2<2>, + + PA12<2>, + + PC2<2>, + ], + + default:PushPull for [ + PA3<2>, + + PA13<2>, + + PC3<2>, + ], + } + + pin! { + for [ + PA0<2>, + + PA8<2>, + + PC0<2>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PA15<2>, + + PB6<5>, + + PC6<4>, + ], + + default:PushPull for [ + PA7<4>, + + PB3<4>, + + PC10<4>, + ], + + default:PushPull for [ + PA14<5>, + + PB8<10>, + + PC7<4>, + ], + + default:PushPull for [ + PB0<4>, + + PB4<4>, + + PC11<4>, + ], + + default:PushPull for [ + PB9<10>, + + PC8<4>, + ], + + default:PushPull for [ + PB1<4>, + + PB5<3>, + + PC12<4>, + ], + + default:PushPull for [ + PC9<4>, + + PD1<4>, + ], + } + + pin! { + for [ + PA0<9>, + + PA6<4>, + + PA10<11>, + + PB7<5>, + + PD2<4>, + ], + + for [ + PB6<10>, + + PC9<6>, + + PD1<6>, + ], + + for [ + PA0<10>, + + PB6<6>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-f373")] +pub mod tim12 { + use super::*; + + pin! { + default:PushPull for [ + PA4<10>, + + PA14<10>, + + PB14<9>, + ], + + default:PushPull for [ + PA5<10>, + + PA15<10>, + + PB15<9>, + ], + } + + use crate::pac::TIM12 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +#[cfg(feature = "gpio-f373")] +pub mod tim13 { + use super::*; + + pin! { + default:PushPull for [ + PA6<9>, + + PA9<2>, + + PB3<9>, + + PC4<2>, + ], + } + + use crate::pac::TIM13 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +#[cfg(feature = "gpio-f373")] +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA5<9>, + + PA7<9>, + + PA10<9>, + + PF9<2>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<9>, + + #[cfg(feature = "gpio-f373")] + PB6<9>, + + PB14<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PF9<3>, + ], + + default:PushPull for [ + PA1<9>, + + #[cfg(feature = "gpio-f373")] + PB4<9>, + + PB15<2>, + ], + + default:PushPull for [ + PA3<9>, + + #[cfg(feature = "gpio-f373")] + PB7<9>, + + PB15<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PF10<3>, + ], + } + + pin! { + for [ + PA9<9>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PC5<2>, + ], + + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<1>, + + PA12<1>, + + PB4<1>, + + PB8<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE0<4>, + ], + + default:PushPull for [ + PA13<1>, + + PB6<1>, + ], + } + + pin! { + for [ + PB5<1>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<1>, + + PB5<10>, + + PB9<1>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] + PE1<4>, + ], + + default:PushPull for [ + PB7<1>, + ], + } + + pin! { + for [ + PA10<1>, + + PB4<10>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +#[cfg(feature = "gpio-f373")] +pub mod tim19 { + use super::*; + + pin! { + default:PushPull for [ + PA0<11>, + + PB6<11>, + + PC10<2>, + ], + + default:PushPull for [ + PA1<11>, + + PB7<11>, + + PC11<2>, + ], + + default:PushPull for [ + PA2<11>, + + PB8<11>, + + PC12<2>, + ], + + default:PushPull for [ + PA3<11>, + + PB9<11>, + + PD0<2>, + ], + } + + pin! { + for [ + PB5<11>, + + PD1<2>, + ], + } + + use crate::pac::TIM19 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-f303e")] +pub mod tim20 { + use super::*; + + pin! { + default:PushPull for [ + PE2<6>, + + PF12<2>, + + PH0<2>, + ], + + default:PushPull for [ + PE4<6>, + + PF4<3>, + + PG0<2>, + ], + + default:PushPull for [ + PE3<6>, + + PF13<2>, + + PH1<2>, + ], + + default:PushPull for [ + PE5<6>, + + PF5<2>, + + PG1<2>, + ], + + default:PushPull for [ + PF2<2>, + + PF14<2>, + ], + + default:PushPull for [ + PE6<6>, + + PG2<2>, + ], + + default:PushPull for [ + PE1<6>, + + PF3<2>, + + PF15<2>, + ], + } + + pin! { + for [ + PF7<2>, + + PF9<2>, + + PG3<2>, + ], + + for [ + PF8<2>, + + PF10<2>, + + PG4<2>, + ], + + for [ + PE0<6>, + + PF11<2>, + + PG5<2>, + ], + } + + use crate::pac::TIM20 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tsc { + use super::*; + + pin! { + for [ // Low speed + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303e", + feature = "gpio-f333", + feature = "gpio-f373" + ))] + PA15<3>, + + PB8<3>, + + PB10<3>, + ], + } + + pin! { + default:PushPull for [ + PA0<3>, + ], + + default:PushPull for [ + PA1<3>, + ], + + default:PushPull for [ + PA2<3>, + ], + + default:PushPull for [ + PA3<3>, + ], + + default:PushPull for [ + PA4<3>, + ], + + default:PushPull for [ + PA5<3>, + ], + + default:PushPull for [ + PA6<3>, + ], + + default:PushPull for [ + PA7<3>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-f373")] + PC4<3>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PC5<3>, + ], + + default:PushPull for [ + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB0<3>, + + #[cfg(feature = "gpio-f373")] + PC5<3>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-f373")] + PB0<3>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB1<3>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-f373")] + PB1<3>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB2<3>, + ], + + default:PushPull for [ + PA9<3>, + ], + + default:PushPull for [ + PA10<3>, + ], + + default:PushPull for [ + PA13<3>, + ], + + default:PushPull for [ + PA14<3>, + ], + + default:PushPull for [ + PB3<3>, + ], + + default:PushPull for [ + PB4<3>, + ], + + default:PushPull for [ + PB6<3>, + ], + + default:PushPull for [ + PB7<3>, + ], + + default:PushPull for [ + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB11<3>, + + #[cfg(feature = "gpio-f373")] + PB14<3>, + ], + + default:PushPull for [ + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB12<3>, + + #[cfg(feature = "gpio-f373")] + PB15<3>, + ], + + default:PushPull for [ + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB13<3>, + + #[cfg(feature = "gpio-f373")] + PD8<3>, + ], + + default:PushPull for [ + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB14<3>, + + #[cfg(feature = "gpio-f373")] + PD9<3>, + ], + } + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + pin! { + default:PushPull for [ + PE2<3>, + ], + + default:PushPull for [ + PE3<3>, + ], + + default:PushPull for [ + PE4<3>, + ], + + default:PushPull for [ + PE5<3>, + ], + + default:PushPull for [ + PD12<3>, + ], + + default:PushPull for [ + PD13<3>, + ], + + default:PushPull for [ + PD14<3>, + ], + + default:PushPull for [ + PD15<3>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + + for [ + PA12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + PC5<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE1<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + PC4<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE0<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PB5<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD7<7>, + + #[cfg(feature = "gpio-f373")] + PF7<7>, + ], + + for [ + PA0<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD3<7>, + ], + + for [ + PA1<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD4<7>, + ], + + for [ + PA1<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PA15<7>, + + PB4<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PA14<7>, + + PB3<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB12<7>, + + PC12<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD10<7>, + ], + + for [ + PA13<7>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB13<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD11<7>, + ], + + for [ + PB14<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD12<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PF6<7>, + ], + + for [ + PB14<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD12<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PF6<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PB8<7>, + + #[cfg(feature = "gpio-f373")] + PB9<7>, + + #[cfg(any( + feature = "gpio-f302", + feature = "gpio-f303", + feature = "gpio-f303e", + feature = "gpio-f333" + ))] + PB11<7>, + + PC11<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD9<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PE15<7>, + ], + + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f373")] + PB8<7>, + + #[cfg(any(feature = "gpio-f302", feature = "gpio-f303e", feature = "gpio-f333"))] + PB9<7>, + + PB10<7>, + + PC10<7>, + + #[cfg(any(feature = "gpio-f303", feature = "gpio-f303e", feature = "gpio-f373"))] + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod uart4 { + use super::*; + + pin! { + default:PushPull for no:NoPin, [ + PC11<5>, + ], + + default:PushPull for no:NoPin, [ + PC10<5>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f303e"))] +pub mod uart5 { + use super::*; + + pin! { + default:PushPull for no:NoPin, [ + PD2<5>, + ], + + default:PushPull for no:NoPin, [ + PC12<5>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-f303", feature = "gpio-f373"))] +pub mod usb { + use super::*; + + pin! { + for [ + PA11<14>, + ], + + for [ + PA12<14>, + ], + } +} diff --git a/src/gpio/alt/f4.rs b/src/gpio/alt/f4.rs index 3a782395..23214425 100644 --- a/src/gpio/alt/f4.rs +++ b/src/gpio/alt/f4.rs @@ -633,9 +633,12 @@ pub mod eth { } } +#[cfg(any(feature = "fmc", feature = "fsmc"))] +pub use fmc as fsmc; + /// Pins available on all STM32F4 models that have an FSMC/FMC #[cfg(any(feature = "fmc", feature = "fsmc"))] -pub mod fsmc { +pub mod fmc { use super::*; pub use Ne1 as ChipSelect1; @@ -2611,18 +2614,18 @@ pub mod sai1 { use crate::pac::SAI; #[cfg(any(feature = "stm32f427", feature = "stm32f437", feature = "gpio-f446"))] use crate::pac::SAI1 as SAI; - pub use crate::sai::{SAI1A, SAI1B}; + use crate::sai::SAICH; impl SaiChannels for SAI { - type A = SAI1A; - type B = SAI1B; + type A = SAICH; + type B = SAICH; } - impl SaiChannel for SAI1A { + impl SaiChannel for SAICH { type Fs = FsA; type Mclk = MclkA; type Sck = SckA; type Sd = SdA; } - impl SaiChannel for SAI1B { + impl SaiChannel for SAICH { type Fs = FsB; type Mclk = MclkB; type Sck = SckB; @@ -2685,18 +2688,18 @@ pub mod sai2 { } use crate::pac::SAI2 as SAI; - pub use crate::sai::{SAI2A, SAI2B}; + use crate::sai::SAICH; impl SaiChannels for SAI { - type A = SAI2A; - type B = SAI2B; + type A = SAICH; + type B = SAICH; } - impl SaiChannel for SAI2A { + impl SaiChannel for SAICH { type Fs = FsA; type Mclk = MclkA; type Sck = SckA; type Sd = SdA; } - impl SaiChannel for SAI2B { + impl SaiChannel for SAICH { type Fs = FsB; type Mclk = MclkB; type Sck = SckB; diff --git a/src/gpio/alt/f7.rs b/src/gpio/alt/f7.rs new file mode 100644 index 00000000..04ca0020 --- /dev/null +++ b/src/gpio/alt/f7.rs @@ -0,0 +1,3475 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod can1 { + use super::*; + + pin! { + for no:NoPin, [ + PA11<9>, + + PB8<9>, + + PD0<9>, + + #[cfg(any(feature = "gpio-f72x", feature = "gpio-f76x"))] + PH14<9>, + + PI9<9>, + ], + + for no:NoPin, [ + PA12<9>, + + PB9<9>, + + PD1<9>, + + PH13<9>, + ], + } + impl CanCommon for crate::pac::CAN1 { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod can2 { + use super::*; + + pin! { + for no:NoPin, [ + PB5<9>, + + PB12<9>, + ], + + for no:NoPin, [ + PB6<9>, + + PB13<9>, + ], + } + impl CanCommon for crate::pac::CAN2 { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(feature = "gpio-f76x")] +pub mod can3 { + use super::*; + + pin! { + for no:NoPin, [ + PA8<11>, + + PB3<11>, + ], + + for no:NoPin, [ + PA15<11>, + + PB4<11>, + ], + } + impl CanCommon for crate::pac::CAN3 { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod dcmi { + use super::*; + + pin! { + for [ + PA9<13>, + + PC6<13>, + + PH9<13>, + ], + + for [ + PA10<13>, + + PC7<13>, + + PH10<13>, + ], + + for [ + PB5<13>, + + PD6<13>, + + PI3<13>, + ], + + for [ + PD2<13>, + + PF10<13>, + + PH15<13>, + ], + + for [ + PF11<13>, + + PG6<13>, + ], + + for [ + PG7<13>, + + PG15<13>, + + PI0<13>, + ], + + for [ + PC8<13>, + + PE0<13>, + + PG10<13>, + + PH11<13>, + ], + + for [ + PC9<13>, + + PE1<13>, + + PG11<13>, + + PH12<13>, + ], + + for [ + PC11<13>, + + PE4<13>, + + PH14<13>, + ], + + for [ + PB6<13>, + + PD3<13>, + + PI4<13>, + ], + + for [ + PB8<13>, + + PE5<13>, + + PI6<13>, + ], + + for [ + PB9<13>, + + PE6<13>, + + PI7<13>, + ], + + for [ + PC10<13>, + + PH6<13>, + + PI1<13>, + ], + + for [ + PC12<13>, + + PH7<13>, + + PI2<13>, + ], + + for [ + PA4<13>, + + PH8<13>, + ], + + for [ + PA6<13>, + ], + + for [ + PB7<13>, + + PG9<13>, + + PI5<13>, + ], + } +} + +#[cfg(feature = "gpio-f76x")] +pub mod dfsdm1 { + use super::*; + + pin! { + for [ + PC0<3>, + + PD4<6>, + ], + + for [ + PB2<10>, + + PB13<6>, + + PC2<3>, + + PD7<6>, + ], + + for [ + PB15<6>, + + PC4<3>, + + PE8<6>, + ], + + for [ + PC6<7>, + + PD8<3>, + + PE5<10>, + ], + + for [ + PC1<10>, + + PD6<3>, + + PE11<6>, + ], + + for [ + PB7<6>, + + PC10<3>, + + PE13<6>, + ], + + for [ + PD0<3>, + + PF14<6>, + ], + + for [ + PB8<6>, + + PB11<6>, + + PD1<6>, + ], + + for [ + PB0<6>, + + PC2<6>, + + PD3<3>, + + PD10<3>, + + PE9<6>, + ], + + for [ + PC1<3>, + + PD3<6>, + ], + + for [ + PB1<6>, + + PB12<6>, + + PC3<3>, + + PD6<10>, + ], + + for [ + PB14<6>, + + PC5<3>, + + PE7<6>, + ], + + for [ + PC7<7>, + + PD9<3>, + + PE4<10>, + ], + + for [ + PC0<6>, + + PD7<3>, + + PE10<6>, + ], + + for [ + PB6<6>, + + PC11<3>, + + PE12<6>, + ], + + for [ + PD1<3>, + + PF13<6>, + ], + + for [ + PB9<6>, + + PB10<6>, + + PD0<6>, + ], + } + + #[cfg(not(feature = "stm32f765"))] + use crate::pac::DFSDM; + #[cfg(feature = "stm32f765")] + use crate::pac::DFSDM1 as DFSDM; + impl DfsdmBasic for DFSDM { + type Ckin0 = Ckin0; + type Ckin1 = Ckin1; + type Ckout = Ckout; + type Datin0 = Datin0; + type Datin1 = Datin1; + } + impl DfsdmGeneral for DFSDM { + type Ckin2 = Ckin2; + type Ckin3 = Ckin3; + type Datin2 = Datin2; + type Datin3 = Datin3; + } + + impl DfsdmAdvanced for DFSDM { + type Ckin4 = Ckin4; + type Ckin5 = Ckin5; + type Ckin6 = Ckin6; + type Ckin7 = Ckin7; + type Datin4 = Datin4; + type Datin5 = Datin5; + type Datin6 = Datin6; + type Datin7 = Datin7; + } +} + +#[cfg(feature = "gpio-f76x")] +pub mod dsihost { + use super::*; + + pin! { + for [ + PB11<13>, + + PJ2<13>, + ], + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod eth { + use super::*; + + pin! { + for [ + PA3<11>, + + PH3<11>, + ], + + for [ + PA0<11>, + + PH2<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PC1<11>, + ], + + for [ + PA2<11>, + ], + + for [ + PB5<11>, + + PG8<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PB10<11>, + + PI10<11>, + ], + + for [ + PC4<11>, + ], + + for [ + PC5<11>, + ], + + for [ + PB0<11>, + + PH6<11>, + ], + + for [ + PB1<11>, + + PH7<11>, + ], + + for [ + PC3<11>, + ], + + for [ + PB11<11>, + + PG11<11>, + ], + + for [ + PB12<11>, + + PG13<11>, + ], + + for [ + PB13<11>, + + PG14<11>, + ], + + for [ + PC2<11>, + ], + + for [ + PB8<11>, + + PE2<11>, + ], + } +} + +pub mod fmc { + use super::*; + + // TODO: replace this with `Ax` + pin! { + /// A pin that can be used as one bit of the memory address + /// + /// This is used to switch between data and command mode. + for [ + PD11<12, Speed::VeryHigh>, + PD12<12, Speed::VeryHigh>, + PD13<12, Speed::VeryHigh>, + PE2<12, Speed::VeryHigh>, + PE3<12, Speed::VeryHigh>, + PE4<12, Speed::VeryHigh>, + PE5<12, Speed::VeryHigh>, + PE6<12, Speed::VeryHigh>, + PF0<12, Speed::VeryHigh>, + PF1<12, Speed::VeryHigh>, + PF2<12, Speed::VeryHigh>, + PF3<12, Speed::VeryHigh>, + PF4<12, Speed::VeryHigh>, + PF5<12, Speed::VeryHigh>, + PF12<12, Speed::VeryHigh>, + PF13<12, Speed::VeryHigh>, + PF14<12, Speed::VeryHigh>, + PF15<12, Speed::VeryHigh>, + PG0<12, Speed::VeryHigh>, + PG1<12, Speed::VeryHigh>, + PG2<12, Speed::VeryHigh>, + PG3<12, Speed::VeryHigh>, + PG4<12, Speed::VeryHigh>, + PG5<12, Speed::VeryHigh>, + PG13<12, Speed::VeryHigh>, + ], + } + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PH8<12, Speed::VeryHigh>, + ], + + for [ + PH9<12, Speed::VeryHigh>, + ], + + for [ + PH10<12, Speed::VeryHigh>, + ], + + for [ + PH11<12, Speed::VeryHigh>, + ], + + for [ + PH12<12, Speed::VeryHigh>, + ], + + for [ + PH13<12, Speed::VeryHigh>, + ], + + for [ + PH14<12, Speed::VeryHigh>, + ], + + for [ + PH15<12, Speed::VeryHigh>, + ], + + for [ + PI0<12, Speed::VeryHigh>, + ], + + for [ + PI1<12, Speed::VeryHigh>, + ], + + for [ + PI2<12, Speed::VeryHigh>, + ], + + for [ + PI3<12, Speed::VeryHigh>, + ], + + for [ + PI6<12, Speed::VeryHigh>, + ], + + for [ + PI7<12, Speed::VeryHigh>, + ], + + for [ + PI9<12, Speed::VeryHigh>, + ], + + for [ + PI10<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PG7<12, Speed::VeryHigh>, + + #[cfg(feature = "gpio-f72x")] + PG11<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PI4<12, Speed::VeryHigh>, + ], + + for [ + PI5<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PC8<9, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PC7<9, Speed::VeryHigh>, + + PD7<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PC8<9, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PG6<12, Speed::VeryHigh>, + + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PC6<9, Speed::VeryHigh>, + + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + + for [ + PC3<12, Speed::VeryHigh>, + + PC5<12, Speed::VeryHigh>, + + PH2<12, Speed::VeryHigh>, + ], + + for [ + PB5<12, Speed::VeryHigh>, + + PH7<12, Speed::VeryHigh>, + ], + + for [ + PG8<12, Speed::VeryHigh>, + ], + + for [ + PG15<12, Speed::VeryHigh>, + ], + + for [ + PC2<12, Speed::VeryHigh>, + + PC4<12, Speed::VeryHigh>, + + PH3<12, Speed::VeryHigh>, + ], + + for [ + PB6<12, Speed::VeryHigh>, + + PH6<12, Speed::VeryHigh>, + ], + + for [ + PF11<12, Speed::VeryHigh>, + ], + + for [ + PA7<12, Speed::VeryHigh>, + + PC0<12, Speed::VeryHigh>, + + PH5<12, Speed::VeryHigh>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + ], + + for [ + PB7<4>, + + PB9<4>, + ], + + for [ + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PF1<4>, + + PH4<4>, + ], + + for [ + PB11<4>, + + PF0<4>, + + PH5<4>, + ], + + for [ + PB12<4>, + + PF2<4>, + + PH6<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA8<4>, + + PH7<4>, + ], + + for [ + PC9<4>, + + PH8<4>, + ], + + for [ + PA9<4>, + + PH9<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod i2c4 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-f76x")] + PB6<11>, + + #[cfg(feature = "gpio-f76x")] + PB8<1>, + + PD12<4>, + + PF14<4>, + + PH11<4>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PB7<11>, + + #[cfg(feature = "gpio-f76x")] + PB9<1>, + + PD13<4>, + + PF15<4>, + + PH12<4>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PB9<11>, + + PD11<4>, + + PF13<4>, + + PH10<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PC9<5>, + ], + } +} + +pub mod i2s1 { + use super::*; + + pin! { + for [ + PA5<5>, + + PB3<5>, + + #[cfg(feature = "gpio-f76x")] + PG11<5>, + ], + + for no:NoPin, [ + PC4<5>, + ], + + for [ + PA7<5>, + + PB5<5>, + + #[cfg(feature = "gpio-f76x")] + PD7<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + #[cfg(feature = "gpio-f76x")] + PG10<5>, + ], + } + + use crate::pac::SPI1 as SPI; + + impl I2sCommon for SPI { + type Ck = Ck; + type Sd = Sd; + type Ws = Ws; + } + impl I2sMaster for SPI { + type Mck = Mck; + } +} + +pub mod i2s2 { + use super::*; + + pin! { + for [ + PA9<5>, + + #[cfg(feature = "gpio-f76x")] + PA12<5>, + + PB10<5>, + + PB13<5>, + + PD3<5>, + + PI1<5>, + ], + + for no:NoPin, [ + PC6<5>, + ], + + for [ + PB15<5>, + + PC1<5>, + + PC3<5>, + + PI3<5>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA11<5>, + + PB4<7>, + + PB9<5>, + + PB12<5>, + + PI0<5>, + ], + } + + use crate::pac::SPI2 as SPI; + + impl I2sCommon for SPI { + type Ck = Ck; + type Sd = Sd; + type Ws = Ws; + } + impl I2sMaster for SPI { + type Mck = Mck; + } +} + +pub mod i2s3 { + use super::*; + + pin! { + for [ + PB3<6>, + + PC10<6>, + ], + + for no:NoPin, [ + PC7<6>, + ], + + for [ + PB2<7>, + + PB5<6>, + + PC12<6>, + + PD6<5>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + } + + use crate::pac::SPI3 as SPI; + + impl I2sCommon for SPI { + type Ck = Ck; + type Sd = Sd; + type Ws = Ws; + } + impl I2sMaster for SPI { + type Mck = Mck; + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PE0<3>, + + PG14<3>, + ], + + for [ + PD12<3>, + + PG12<3>, + ], + + for [ + PE1<3>, + + PH2<3>, + ], + } + + pin! { + default:PushPull for [ + PD13<3>, + + PG13<3>, + ], + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod ltdc { + use super::*; + + pin! { + for [ + PE4<14>, + + PG14<14>, + + PJ12<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA10<14>, + + PG12<14>, + + PJ13<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA3<9>, + + #[cfg(feature = "gpio-f76x")] + PC9<14>, + + PD6<14>, + + PG10<14>, + + PJ14<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA8<13>, + + PD10<14>, + + PG11<14>, + + PJ15<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA10<9>, + + PE12<14>, + + PG12<9>, + + PI4<14>, + + PK3<14>, + ], + + for [ + PA3<14>, + + PI5<14>, + + PK4<14>, + ], + + for [ + PB8<14>, + + PI6<14>, + + PK5<14>, + ], + + for [ + PB9<14>, + + PI7<14>, + + PK6<14>, + ], + + for [ + PE14<14>, + + PG7<14>, + + PI14<14>, + ], + + for [ + PE13<14>, + + PF10<14>, + + PK7<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PB1<14>, + + PE5<14>, + + PJ7<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PB0<14>, + + PE6<14>, + + PJ8<14>, + ], + + for [ + PA6<14>, + + PH13<14>, + + #[cfg(feature = "gpio-f76x")] + PI15<9>, + + PJ9<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PC9<10>, + + PE11<14>, + + PG10<9>, + + PH14<14>, + + PJ10<14>, + + #[cfg(feature = "gpio-f76x")] + PJ12<9>, + ], + + for [ + PB10<14>, + + #[cfg(feature = "gpio-f76x")] + PH4<14>, + + PH15<14>, + + PJ11<14>, + + #[cfg(feature = "gpio-f76x")] + PJ13<9>, + ], + + for [ + PB11<14>, + + #[cfg(feature = "gpio-f76x")] + PH4<9>, + + PI0<14>, + + PK0<14>, + ], + + for [ + PC7<14>, + + PI1<14>, + + #[cfg(feature = "gpio-f76x")] + PI11<9>, + + PK1<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PB5<14>, + + PD3<14>, + + #[cfg(feature = "gpio-f76x")] + PG8<14>, + + PI2<14>, + + PK2<14>, + ], + + for [ + PC6<14>, + + PI10<14>, + + PI12<14>, + ], + + for [ + PG13<14>, + + PH2<14>, + + PI15<14>, + ], + + for [ + PA2<14>, + + PH3<14>, + + PJ0<14>, + ], + + for [ + PA1<14>, + + PC10<14>, + + PH8<14>, + + PJ1<14>, + ], + + for [ + PB0<9>, + + PH9<14>, + + PJ2<14>, + ], + + for [ + PA5<14>, + + PA11<14>, + + PH10<14>, + + PJ3<14>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA9<14>, + + PA12<14>, + + PC0<14>, + + PH11<14>, + + PJ4<14>, + ], + + for [ + PA8<14>, + + PB1<9>, + + PH12<14>, + + PJ5<14>, + ], + + for [ + PE15<14>, + + PG6<14>, + + #[cfg(feature = "gpio-f76x")] + PJ0<9>, + + PJ6<14>, + ], + + for [ + PA4<14>, + + PI9<14>, + + PI13<14>, + ], + } +} + +#[cfg(feature = "gpio-f76x")] +pub mod mdios { + use super::*; + + pin! { + for [ + PA6<12>, + + PC1<12>, + ], + + for [ + PA2<12>, + + PA10<12>, + ], + } +} + +pub mod quadspi { + use super::*; + + pin! { + for [ + PC9<9>, + + PD11<9>, + + PF8<10>, + ], + + for [ + PC10<9>, + + PD12<9>, + + PF9<10>, + ], + + for [ + PE2<9>, + + PF7<9>, + ], + + for [ + PA1<9>, + + PD13<9>, + + PF6<9>, + ], + + for [ + PB6<10>, + + #[cfg(feature = "gpio-f76x")] + PB10<9>, + ], + + for [ + PE7<10>, + + PH2<9>, + ], + + for [ + PE8<10>, + + PH3<9>, + ], + + for [ + PE9<10>, + + PG9<9>, + ], + + for [ + PE10<10>, + + PG14<9>, + ], + + for [ + PC11<9>, + ], + + for [ + PB2<9>, + + #[cfg(feature = "gpio-f76x")] + PF10<9>, + ], + } + + pub struct Bank1; + pub struct Bank2; + + impl QuadSpiBanks for crate::pac::QUADSPI { + type Bank1 = Bank1; + type Bank2 = Bank2; + } + impl QuadSpiBank for Bank1 { + type Io0 = Bk1Io0; + type Io1 = Bk1Io1; + type Io2 = Bk1Io2; + type Io3 = Bk1Io3; + type Ncs = Bk1Ncs; + } + impl QuadSpiBank for Bank2 { + type Io0 = Bk2Io0; + type Io1 = Bk2Io1; + type Io2 = Bk2Io2; + type Io3 = Bk2Io3; + type Ncs = Bk2Ncs; + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + + for [ + PC9<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PB15<0>, + ], + } +} + +pub mod sai1 { + use super::*; + + pin! { + for [ + PE4<6>, + ], + + for [ + PF9<6>, + ], + + for no:NoPin, [ + PE2<6>, + + #[cfg(feature = "gpio-f76x")] + PG7<6>, + ], + + for no:NoPin, [ + PF7<6>, + ], + + for [ + PE5<6>, + ], + + for [ + PF8<6>, + ], + + for [ + PB2<6>, + + PC1<6>, + + PD6<6>, + + PE6<6>, + ], + + for [ + PE3<6>, + + PF6<6>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sai2 { + use super::*; + + pin! { + for [ + PD12<10>, + + PI7<10>, + ], + + for [ + PA12<8>, + + PC0<8>, + + PE13<10>, + + PG9<10>, + ], + + for no:NoPin, [ + PE0<10>, + + PI4<10>, + ], + + for no:NoPin, [ + PA1<10>, + + PE6<10>, + + PE14<10>, + + PH3<10>, + ], + + for [ + PD13<10>, + + PI5<10>, + ], + + for [ + PA2<8>, + + PE12<10>, + + PH2<10>, + ], + + for [ + PD11<10>, + + PI6<10>, + ], + + for [ + PA0<10>, + + PE11<10>, + + PF11<10>, + + PG10<10>, + ], + } + use crate::pac::SAI2 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sdmmc1 { + use super::*; + + pin! { + for [ + PC12<12>, + ], + + for [ + PD2<12>, + ], + + for [ + PC8<12>, + ], + + for [ + PC9<12>, + ], + + for [ + PC10<12>, + ], + + for [ + PC11<12>, + ], + + for [ + PB8<12>, + ], + + for [ + PB9<12>, + ], + + for [ + PC6<12>, + ], + + for [ + PC7<12>, + ], + } +} + +#[cfg(any(feature = "gpio-f72x", feature = "gpio-f76x"))] +pub mod sdmmc2 { + use super::*; + + pin! { + for [ + PD6<11>, + ], + + for [ + PD7<11>, + ], + + for [ + PB14<10>, + + PG9<11>, + ], + + for [ + PB15<10>, + + PG10<11>, + ], + + for [ + PB3<10>, + + PG11<10>, + ], + + for [ + PB4<10>, + + PG12<11>, + ], + + for [ + PB8<10>, + ], + + for [ + PB9<10>, + ], + + for [ + PC6<10>, + ], + + for [ + PC7<10>, + ], + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod spdifrx { + use super::*; + + pin! { + for [ + PD7<8>, + + PG11<7>, + ], + + for [ + PD8<8>, + + PG12<7>, + ], + + for [ + PC4<8>, + + PG8<7>, + ], + + for [ + PC5<8>, + + PG9<7>, + ], + } + + use crate::pac::SPDIFRX; + impl SPdifIn<0> for SPDIFRX { + type In = In0; + } + impl SPdifIn<1> for SPDIFRX { + type In = In1; + } + impl SPdifIn<2> for SPDIFRX { + type In = In2; + } + impl SPdifIn<3> for SPDIFRX { + type In = In3; + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PB4<5>, + + #[cfg(feature = "gpio-f76x")] + PG9<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PB5<5>, + + #[cfg(feature = "gpio-f76x")] + PD7<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + #[cfg(feature = "gpio-f76x")] + PG10<5>, + ], + + for no:NoPin, [ + PA5<5>, + + PB3<5>, + + #[cfg(feature = "gpio-f76x")] + PG11<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + PI2<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC1<5>, + + PC3<5>, + + PI3<5>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA11<5>, + + PB4<7>, + + PB9<5>, + + PB12<5>, + + PI0<5>, + ], + + for no:NoPin, [ + PA9<5>, + + #[cfg(feature = "gpio-f76x")] + PA12<5>, + + PB10<5>, + + PB13<5>, + + PD3<5>, + + PI1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + ], + + for no:NoPin, [ + PB2<7>, + + PB5<6>, + + PC12<6>, + + PD6<5>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi4 { + use super::*; + + pin! { + for no:NoPin, [ + PE5<5>, + + PE13<5>, + ], + + for no:NoPin, [ + PE6<5>, + + PE14<5>, + ], + + for [ + PE4<5>, + + PE11<5>, + ], + + for no:NoPin, [ + PE2<5>, + + PE12<5>, + ], + } + impl SpiCommon for crate::pac::SPI4 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi5 { + use super::*; + + pin! { + for no:NoPin, [ + PF8<5>, + + PH7<5>, + ], + + for no:NoPin, [ + PF9<5>, + + PF11<5>, + ], + + for [ + PF6<5>, + + PH5<5>, + ], + + for no:NoPin, [ + PF7<5>, + + PH6<5>, + ], + } + impl SpiCommon for crate::pac::SPI5 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any(feature = "gpio-f746", feature = "gpio-f76x"))] +pub mod spi6 { + use super::*; + + pin! { + for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PA6<8>, + + #[cfg(feature = "gpio-f76x")] + PB4<8>, + + PG12<5>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PA7<8>, + + #[cfg(feature = "gpio-f76x")] + PB5<8>, + + PG14<5>, + ], + + for [ + #[cfg(feature = "gpio-f76x")] + PA4<8>, + + #[cfg(feature = "gpio-f76x")] + PA15<7>, + + PG8<5>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PA5<8>, + + #[cfg(feature = "gpio-f76x")] + PB3<8>, + + PG13<5>, + ], + } + impl SpiCommon for crate::pac::SPI6 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + PE2<0>, + ], + + for [ + PC1<0>, + + PE3<0>, + + PG13<0>, + ], + + for [ + PC8<0>, + + PE4<0>, + + PG14<0>, + ], + + for [ + PD2<0>, + + PE5<0>, + ], + + for [ + PC12<0>, + + PE6<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + PE9<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + PE8<1>, + ], + + default:PushPull for [ + PA9<1>, + + PE11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + PE10<1>, + ], + + default:PushPull for [ + PA10<1>, + + PE13<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + PE12<1>, + ], + + default:PushPull for [ + PA11<1>, + + PE14<1>, + ], + } + + pin! { + for [ + PA6<1>, + + PB12<1>, + + PE15<1>, + ], + + for [ + PE6<1>, + ], + + for [ + PA12<1>, + + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + ], + } + + pin! { + for [ + PD2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PH10<2>, + ], + + default:PushPull for [ + PA1<2>, + + PH11<2>, + ], + + default:PushPull for [ + PA2<2>, + + PH12<2>, + ], + + default:PushPull for [ + PA3<2>, + + PI0<2>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + + PI5<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + + PH13<3>, + ], + + default:PushPull for [ + PC7<3>, + + PI6<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + + PH14<3>, + ], + + default:PushPull for [ + PC8<3>, + + PI7<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + + PH15<3>, + ], + + default:PushPull for [ + PC9<3>, + + PI2<3>, + ], + } + + pin! { + for [ + PA6<3>, + + PI4<3>, + ], + + for [ + PA8<3>, + + PI1<3>, + ], + + for [ + PA0<3>, + + PI3<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim9 { + use super::*; + + pin! { + default:PushPull for [ + PA2<3>, + + PE5<3>, + ], + + default:PushPull for [ + PA3<3>, + + PE6<3>, + ], + } + + use crate::pac::TIM9 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim10 { + use super::*; + + pin! { + default:PushPull for [ + PB8<3>, + + PF6<3>, + ], + } + + use crate::pac::TIM10 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim11 { + use super::*; + + pin! { + default:PushPull for [ + PB9<3>, + + PF7<3>, + ], + } + + use crate::pac::TIM11 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim12 { + use super::*; + + pin! { + default:PushPull for [ + PB14<9>, + + PH6<9>, + ], + + default:PushPull for [ + PB15<9>, + + PH9<9>, + ], + } + + use crate::pac::TIM12 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim13 { + use super::*; + + pin! { + default:PushPull for [ + PA6<9>, + + PF8<9>, + ], + } + + use crate::pac::TIM13 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA7<9>, + + PF9<9>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + + for [ + PA12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + #[cfg(feature = "gpio-f76x")] + PB15<4>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + #[cfg(feature = "gpio-f76x")] + PB14<4>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart6 { + use super::*; + + pin! { + for [ + PC8<8>, + + PG7<8>, + ], + + for [ + PG13<8>, + + PG15<8>, + ], + + for [ + PG8<8>, + + PG12<8>, + ], + + for [ + PG8<8>, + + PG12<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC7<8>, + + PG9<8>, + ], + + default:PushPull for no:NoPin, [ + PC6<8>, + + PG14<8>, + ], + } + use crate::pac::USART6 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart4 { + use super::*; + + pin! { + for [ + PB0<8>, + + #[cfg(feature = "gpio-f76x")] + PB15<8>, + ], + + for [ + PA15<8>, + + #[cfg(feature = "gpio-f76x")] + PB14<8>, + ], + + for [ + PA15<8>, + + #[cfg(feature = "gpio-f76x")] + PB14<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + #[cfg(feature = "gpio-f76x")] + PA11<6>, + + PC11<8>, + + #[cfg(feature = "gpio-f76x")] + PD0<8>, + + #[cfg(any(feature = "gpio-f72x", feature = "gpio-f76x"))] + PH14<8>, + + #[cfg(any(feature = "gpio-f72x", feature = "gpio-f76x"))] + PI9<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + #[cfg(feature = "gpio-f76x")] + PA12<6>, + + PC10<8>, + + #[cfg(feature = "gpio-f76x")] + PD1<8>, + + #[cfg(any(feature = "gpio-f72x", feature = "gpio-f76x"))] + PH13<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart5 { + use super::*; + + pin! { + for [ + PC9<7>, + ], + + for [ + PC8<7>, + ], + + for [ + PC8<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PB5<1>, + + #[cfg(feature = "gpio-f76x")] + PB8<7>, + + #[cfg(feature = "gpio-f76x")] + PB12<8>, + + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PB6<1>, + + #[cfg(feature = "gpio-f76x")] + PB9<7>, + + #[cfg(feature = "gpio-f76x")] + PB13<8>, + + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart7 { + use super::*; + + pin! { + for [ + PE10<8>, + + PF9<8>, + ], + + for [ + PE9<8>, + + PF8<8>, + ], + + for [ + PE9<8>, + + PF8<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PA8<12>, + + #[cfg(feature = "gpio-f76x")] + PB3<12>, + + PE7<8>, + + PF6<8>, + ], + + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-f76x")] + PA15<12>, + + #[cfg(feature = "gpio-f76x")] + PB4<12>, + + PE8<8>, + + PF7<8>, + ], + } + use crate::pac::UART7 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart8 { + use super::*; + + pin! { + for [ + PD14<8>, + ], + + for [ + PD15<8>, + ], + + for [ + PD15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PE0<8>, + ], + + default:PushPull for no:NoPin, [ + PE1<8>, + ], + } + use crate::pac::UART8 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod otg_fs { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA10<10>, + ], + + for [ + PA8<10>, + ], + } +} + +pub mod otg_hs { + use super::*; + + pin! { + for [ + PB14<12>, + ], + + for [ + PB15<12>, + ], + + for [ + PB12<12>, + ], + + for [ + PA4<12>, + ], + + for [ + PA5<10, Speed::VeryHigh>, + ], + + for [ + PA3<10, Speed::VeryHigh>, + ], + + for [ + PB0<10, Speed::VeryHigh>, + ], + + for [ + PB1<10, Speed::VeryHigh>, + ], + + for [ + PB10<10, Speed::VeryHigh>, + ], + + for [ + PB11<10, Speed::VeryHigh>, + ], + + for [ + PB12<10, Speed::VeryHigh>, + ], + + for [ + PB13<10, Speed::VeryHigh>, + ], + + for [ + PB5<10, Speed::VeryHigh>, + ], + + for [ + PC2<10, Speed::VeryHigh>, + + PI11<10, Speed::VeryHigh>, + ], + + for [ + PC3<10, Speed::VeryHigh>, + + PH4<10, Speed::VeryHigh>, + ], + + for [ + PC0<10, Speed::VeryHigh>, + ], + } +} diff --git a/src/gpio/alt/g0.rs b/src/gpio/alt/g0.rs new file mode 100644 index 00000000..b7ba8245 --- /dev/null +++ b/src/gpio/alt/g0.rs @@ -0,0 +1,2038 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +#[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] +pub mod comp1 { + use super::*; + + pin! { + for [ + PA0<7>, + + PA6<7>, + + PA11<7>, + + PB0<7>, + + PB10<7>, + ], + } +} + +#[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] +pub mod comp2 { + use super::*; + + pin! { + for [ + PA2<7>, + + PA7<7>, + + PA12<7>, + + PB5<7>, + + PB11<7>, + ], + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod comp3 { + use super::*; + + pin! { + for [ + PB1<7>, + + PC0<7>, + + PC2<7>, + ], + } +} + +/*#[cfg(feature = "gpio-g0bx")] +pub mod crs1 { + use super::*; + + pin! { + for [ + PA8<4>, + + PD15<0>, + + PF0<0>, + ], + } +}*/ + +#[cfg(feature = "gpio-g0bx")] +pub mod fdcan1 { + use super::*; + + pin! { + for [ + PA11<3>, + + PB8<3>, + + PC4<3>, + + PD0<3>, + + PD12<3>, + ], + + for [ + PA12<3>, + + PB9<3>, + + PC5<3>, + + PD1<3>, + + PD13<3>, + ], + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod fdcan2 { + use super::*; + + pin! { + for [ + PB0<3>, + + PB5<3>, + + PB12<3>, + + PC2<3>, + + PD14<3>, + ], + + for [ + PB1<3>, + + PB6<3>, + + PB13<3>, + + PC3<3>, + + PD15<3>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA9<6>, + + PB6<6>, + + PB8<6>, + ], + + for [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA10<6>, + + PB7<6>, + + PB9<6>, + ], + + for [ + PA1<6>, + + PB5<6>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-g0bx")] + PA7<8>, + + #[cfg(feature = "gpio-g0bx")] + PA9<8>, + + PA11<6>, + + #[cfg(feature = "gpio-g0bx")] + PB3<8>, + + PB10<6>, + + PB13<6>, + ], + + for [ + #[cfg(feature = "gpio-g0bx")] + PA6<8>, + + #[cfg(feature = "gpio-g0bx")] + PA10<8>, + + PA12<6>, + + #[cfg(feature = "gpio-g0bx")] + PB4<8>, + + PB11<6>, + + PB14<6>, + ], + + for [ + #[cfg(feature = "gpio-g0bx")] + PA8<8>, + + #[cfg(feature = "gpio-g0bx")] + PA15<8>, + + #[cfg(feature = "gpio-g0bx")] + PB12<8>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA7<9>, + + PB3<6>, + + PC0<6>, + ], + + for [ + PA6<9>, + + PB4<6>, + + PC1<6>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PA12<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC9<0>, + ], + } +} + +pub mod i2s1 { + use super::*; + + pin! { + for [ + PA1<0>, + + PA5<0>, + + PB3<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD8<1>, + + #[cfg(feature = "gpio-g0bx")] + PE13<0>, + ], + + for no:NoPin, [ + PA6<0>, + + PA11<0>, + + PB4<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD5<1>, + + #[cfg(feature = "gpio-g0bx")] + PE14<0>, + ], + + for [ + PA2<0>, + + PA7<0>, + + PA12<0>, + + PB5<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD6<1>, + + #[cfg(feature = "gpio-g0bx")] + PE15<0>, + ], + + for [ + PA4<0>, + + PA15<0>, + + PB0<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD9<1>, + + #[cfg(feature = "gpio-g0bx")] + PE12<0>, + ], + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod i2s2 { + use super::*; + + pin! { + for [ + PA0<0>, + + PB8<1>, + + PB10<5>, + + PB13<0>, + + PD1<1>, + ], + + for no:NoPin, [ + PA3<0>, + + PA9<4>, + + PB2<1>, + + PB6<4>, + + PB14<0>, + + PC2<1>, + + PD3<1>, + ], + + for [ + PA4<1>, + + PA10<0>, + + PB7<1>, + + PB11<0>, + + PB15<0>, + + PC3<1>, + + PD4<1>, + ], + + for [ + PA8<1>, + + PB9<5>, + + PB12<0>, + + PD0<1>, + ], + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + PB9<0>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC3<0>, + ], + + for [ + PB5<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC0<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC12<0>, + ], + + for [ + PB7<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC2<0>, + ], + + default:PushPull for [ + PA0<5>, + + PB0<5>, + + PB2<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC1<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD8<2>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA5<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC3<2>, + + #[cfg(feature = "gpio-g0bx")] + PD11<1>, + ], + + for [ + PB1<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC0<2>, + + #[cfg(feature = "gpio-g0bx")] + PD12<1>, + ], + + default:PushPull for [ + PA4<5>, + + PA8<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD6<2>, + + #[cfg(feature = "gpio-g0bx")] + PD13<1>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<6>, + + PB13<1>, + + #[cfg(feature = "gpio-g0bx")] + PF7<1>, + ], + + for [ + PB1<6>, + + PB12<1>, + + #[cfg(feature = "gpio-g0bx")] + PF6<1>, + ], + + for [ + PB1<6>, + + PB12<1>, + + #[cfg(feature = "gpio-g0bx")] + PF6<1>, + ], + + for [ + PA3<6>, + + PB10<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC0<1>, + + #[cfg(feature = "gpio-g0bx")] + PF5<1>, + ], + } + + pin! { + default::PushPull for [ + PA2<6>, + + PB11<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC1<1>, + + #[cfg(feature = "gpio-g0bx")] + PF4<1>, + ], + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod lpuart2 { + use super::*; + + pin! { + for [ + PB0<10>, + + PC8<3>, + + PD14<1>, + ], + + for [ + PB1<10>, + + PC9<3>, + + PD15<1>, + + PF2<3>, + ], + + for [ + PB1<10>, + + PC9<3>, + + PD15<1>, + + PF2<3>, + ], + + for [ + PA13<10>, + + PB7<10>, + + PC1<3>, + + PC7<3>, + + PF3<1>, + ], + } + + pin! { + default:PushPull for [ + PA14<10>, + + PB6<10>, + + PC0<3>, + + PC6<3>, + + PF2<1>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA9<0>, + + #[cfg(feature = "gpio-g0bx")] + PD10<0>, + + PF2<0>, + ], + + for [ + #[cfg(feature = "gpio-g0bx")] + PA10<3>, + + #[cfg(feature = "gpio-g0bx")] + PA15<3>, + + #[cfg(feature = "gpio-g0bx")] + PB2<3>, + + #[cfg(feature = "gpio-g0bx")] + PD7<3>, + ], + + for [ + PC15<0>, + ], + + for [ + PC15<1>, + + PF1<0>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<0>, + + PA11<0>, + + PB4<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD5<1>, + + #[cfg(feature = "gpio-g0bx")] + PE14<0>, + ], + + for no:NoPin, [ + PA2<0>, + + PA7<0>, + + PA12<0>, + + PB5<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD6<1>, + + #[cfg(feature = "gpio-g0bx")] + PE15<0>, + ], + + for [ + PA4<0>, + + PA15<0>, + + PB0<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD9<1>, + + #[cfg(feature = "gpio-g0bx")] + PE12<0>, + ], + + for no:NoPin, [ + PA1<0>, + + PA5<0>, + + PB3<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD8<1>, + + #[cfg(feature = "gpio-g0bx")] + PE13<0>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PA3<0>, + + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA9<4>, + + PB2<1>, + + PB6<4>, + + PB14<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC2<1>, + + PD3<1>, + ], + + for no:NoPin, [ + PA4<1>, + + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA10<0>, + + PB7<1>, + + PB11<0>, + + PB15<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC3<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD4<1>, + ], + + for [ + PA8<1>, + + PB9<5>, + + PB12<0>, + + PD0<1>, + ], + + for no:NoPin, [ + PA0<0>, + + PB8<1>, + + PB10<5>, + + PB13<0>, + + PD1<1>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<9>, + + PC11<4>, + ], + + for no:NoPin, [ + PB5<9>, + + PC12<4>, + ], + + for [ + PA4<9>, + + PA15<9>, + ], + + for no:NoPin, [ + PB3<9>, + + PC10<4>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA13<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC8<2>, + + #[cfg(feature = "gpio-g0bx")] + PE9<1>, + ], + + default:PushPull for [ + PA7<2>, + + PB13<2>, + + PD2<2>, + + #[cfg(feature = "gpio-g0bx")] + PE8<1>, + ], + + default:PushPull for [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA9<2>, + + PB3<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC9<2>, + + #[cfg(feature = "gpio-g0bx")] + PE11<1>, + ], + + default:PushPull for [ + PB0<2>, + + PB14<2>, + + PD3<2>, + + #[cfg(feature = "gpio-g0bx")] + PE10<1>, + ], + + default:PushPull for [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA10<2>, + + PB6<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC10<2>, + + #[cfg(feature = "gpio-g0bx")] + PE13<1>, + ], + + default:PushPull for [ + PB1<2>, + + PB15<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD4<2>, + + #[cfg(feature = "gpio-g0bx")] + PE12<1>, + ], + + default:PushPull for [ + PA11<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC11<2>, + + #[cfg(feature = "gpio-g0bx")] + PE14<1>, + ], + } + + pin! { + for [ + PA6<2>, + + PB12<2>, + + PC13<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD5<2>, + + #[cfg(feature = "gpio-g0bx")] + PE15<1>, + ], + + for [ + PA11<5>, + + PC14<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD9<2>, + + #[cfg(feature = "gpio-g0bx")] + PE14<2>, + ], + + for [ + PA12<2>, + + #[cfg(feature = "gpio-g0bx")] + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PA5<2>, + + PA15<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC4<2>, + ], + + default:PushPull for [ + PA1<2>, + + PB3<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC5<2>, + ], + + default:PushPull for [ + PA2<2>, + + PB10<2>, + + PC6<2>, + ], + + default:PushPull for [ + PA3<2>, + + PB11<2>, + + PC7<2>, + ], + } + + pin! { + for [ + PA0<2>, + + PA5<2>, + + PA15<2>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC4<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<1>, + + PB4<1>, + + PC6<1>, + + #[cfg(feature = "gpio-g0bx")] + PE3<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB5<1>, + + PC7<1>, + + #[cfg(feature = "gpio-g0bx")] + PE4<1>, + ], + + default:PushPull for [ + PB0<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC8<1>, + + #[cfg(feature = "gpio-g0bx")] + PE5<1>, + ], + + default:PushPull for [ + PB1<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC9<1>, + + #[cfg(feature = "gpio-g0bx")] + PE6<1>, + ], + } + + pin! { + for [ + PD2<1>, + + #[cfg(feature = "gpio-g0bx")] + PE2<1>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<9>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<9>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<9>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<9>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA4<4>, + + PA7<4>, + + PB1<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC12<2>, + + PF0<2>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA2<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PB14<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC1<2>, + + #[cfg(feature = "gpio-g0bx")] + PF12<0>, + ], + + default:PushPull for [ + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA1<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PB13<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PB15<4>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PF1<2>, + ], + + default:PushPull for [ + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA3<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PB15<5>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC2<2>, + + #[cfg(feature = "gpio-g0bx")] + PF13<0>, + ], + } + + pin! { + for [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA9<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PB8<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PB12<5>, + + #[cfg(any(feature = "gpio-g05x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC15<2>, + ], + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<5>, + + PB8<2>, + + PD0<2>, + + #[cfg(feature = "gpio-g0bx")] + PE0<0>, + ], + + default:PushPull for [ + PB6<2>, + ], + } + + pin! { + for [ + PB5<2>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<5>, + + PB9<2>, + + PD1<2>, + + #[cfg(feature = "gpio-g0bx")] + PE1<0>, + ], + + default:PushPull for [ + PB7<2>, + ], + } + + pin! { + for [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA10<5>, + + PB4<5>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } +} + +#[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] +pub mod ucpd1 { + use super::*; + + #[cfg(feature = "gpio-g0bx")] + pin! { + for [ + PA2<4>, + + PA5<6>, + + PA7<6>, + + PB0<6>, + + PB14<1>, + + PC6<0>, + + PC12<1>, + ], + + for [ + PA2<4>, + + PA5<6>, + + PA7<6>, + + PB0<6>, + + PB14<1>, + + PC6<0>, + + PC12<1>, + ], + } + + #[cfg(feature = "gpio-g07x")] + pin! { + for [ + PA2<4>, + + PA5<6>, + + PA7<6>, + + PB0<6>, + + PB14<1>, + + PC6<0>, + + PC12<1>, + ], + + for [ + PA5<3>, + + PA6<3>, + + PC6<3>, + + PC8<3>, + + PC9<3>, + + PD0<3>, + + PD1<3>, + + PD8<3>, + ], + + for [ + PA1<3>, + + PA9<3>, + + PB2<3>, + + PB6<3>, + + PB8<3>, + + PB10<3>, + + PB11<3>, + + PC0<3>, + + PC1<3>, + ], + } +} + +#[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] +pub mod ucpd2 { + use super::*; + + #[cfg(feature = "gpio-g0bx")] + pin! { + for [ + PA0<6>, + + PA3<4>, + + PA4<6>, + + PB9<1>, + + PB12<6>, + + PC7<0>, + + PC8<0>, + ], + + for [ + PA0<6>, + + PA3<4>, + + PA4<6>, + + PB9<1>, + + PB12<6>, + + PC7<0>, + + PC8<0>, + ], + } + + #[cfg(feature = "gpio-g07x")] + pin! { + for [ + PA0<6>, + + PA3<4>, + + PA4<6>, + + PB9<1>, + + PB12<6>, + + PC7<0>, + + PC8<0>, + ], + + for [ + PA7<3>, + + PA8<3>, + + PC7<3>, + + PC10<3>, + + PC11<3>, + + PD2<3>, + + PD3<3>, + + PD9<3>, + ], + + for [ + PA3<3>, + + PA10<3>, + + PB4<3>, + + PB9<3>, + + PB13<3>, + + PB14<3>, + + PC2<3>, + + PC3<3>, + + PC5<3>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA12<1>, + + PB3<4>, + ], + + for [ + PA11<1>, + + PB4<4>, + ], + + for [ + PA12<1>, + + PB3<4>, + ], + + for [ + PA11<1>, + + PB4<4>, + ], + + for [ + PA12<1>, + + PB3<4>, + ], + + default:PushPull for no:NoPin, [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA10<1>, + + PB7<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC5<1>, + ], + + default:PushPull for no:NoPin, [ + #[cfg(any(feature = "gpio-g03x", feature = "gpio-g07x", feature = "gpio-g0bx"))] + PA9<1>, + + PB6<0>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PC4<1>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA1<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD4<0>, + ], + + for [ + PA0<1>, + + PD3<0>, + ], + + for [ + PA1<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD4<0>, + ], + + for [ + PA0<1>, + + PD3<0>, + ], + + for [ + PA1<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD4<0>, + ], + + default:PushPull for no:NoPin, [ + PA3<1>, + + PA15<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD6<0>, + ], + + default:PushPull for no:NoPin, [ + PA2<1>, + + PA14<1>, + + #[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] + PD5<0>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] +pub mod usart3 { + use super::*; + + pin! { + for [ + PA15<5>, + + PB1<4>, + + PB14<4>, + + PD2<0>, + + #[cfg(feature = "gpio-g0bx")] + PD12<0>, + ], + + for [ + PA6<4>, + + PB13<4>, + + #[cfg(feature = "gpio-g0bx")] + PD11<0>, + ], + + for [ + PA15<5>, + + PB1<4>, + + PB14<4>, + + PD2<0>, + + #[cfg(feature = "gpio-g0bx")] + PD12<0>, + ], + + for [ + PA6<4>, + + PB13<4>, + + #[cfg(feature = "gpio-g0bx")] + PD11<0>, + ], + + for [ + PA15<5>, + + PB1<4>, + + PB14<4>, + + PD2<0>, + + #[cfg(feature = "gpio-g0bx")] + PD12<0>, + ], + + default:PushPull for no:NoPin, [ + PB0<4>, + + PB9<4>, + + PB11<4>, + + PC5<0>, + + PC11<0>, + + PD9<0>, + ], + + default:PushPull for no:NoPin, [ + PA5<4>, + + PB2<4>, + + PB8<4>, + + PB10<4>, + + PC4<0>, + + PC10<0>, + + PD8<0>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-g07x", feature = "gpio-g0bx"))] +pub mod usart4 { + use super::*; + + pin! { + for [ + PA15<4>, + ], + + for [ + PB7<4>, + ], + + for [ + PA15<4>, + ], + + for [ + PB7<4>, + ], + + for [ + PA15<4>, + ], + + default:PushPull for no:NoPin, [ + PA1<4>, + + PC11<1>, + + #[cfg(feature = "gpio-g0bx")] + PE9<0>, + ], + + default:PushPull for no:NoPin, [ + PA0<4>, + + PC10<1>, + + #[cfg(feature = "gpio-g0bx")] + PE8<0>, + ], + } + use crate::pac::USART4 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod usart5 { + use super::*; + + pin! { + for [ + PB5<8>, + + PD4<3>, + + PE7<3>, + ], + + for [ + PB6<8>, + + PD5<3>, + + PF7<3>, + ], + + for [ + PB5<8>, + + PD4<3>, + + PE7<3>, + ], + + for [ + PB6<8>, + + PD5<3>, + + PF7<3>, + ], + + for [ + PB5<8>, + + PD4<3>, + + PE7<3>, + ], + + default:PushPull for no:NoPin, [ + PB1<8>, + + PB4<3>, + + PD2<3>, + + PE11<3>, + ], + + default:PushPull for no:NoPin, [ + PB0<8>, + + PB3<3>, + + PC12<3>, + + PD3<3>, + + PE10<3>, + ], + } + use crate::pac::USART5 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod usart6 { + use super::*; + + pin! { + for [ + PA7<3>, + + PB14<8>, + + PF3<3>, + + PF11<3>, + ], + + for [ + PA6<3>, + + PB15<8>, + + PF12<3>, + ], + + for [ + PA7<3>, + + PB14<8>, + + PF3<3>, + + PF11<3>, + ], + + for [ + PA6<3>, + + PB15<8>, + + PF12<3>, + ], + + for [ + PA7<3>, + + PB14<8>, + + PF3<3>, + + PF11<3>, + ], + + default:PushPull for no:NoPin, [ + PA5<3>, + + PB9<8>, + + PC1<4>, + + PF10<3>, + ], + + default:PushPull for no:NoPin, [ + PA4<3>, + + PB8<8>, + + PC0<4>, + + PF9<3>, + ], + } + use crate::pac::USART6 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-g0bx")] +pub mod usb { + use super::*; + + pin! { + for [ + PA4<2>, + + PA13<2>, + + PA15<6>, + + PC9<6>, + ], + } +} diff --git a/src/gpio/alt/g4.rs b/src/gpio/alt/g4.rs new file mode 100644 index 00000000..b2ba8d48 --- /dev/null +++ b/src/gpio/alt/g4.rs @@ -0,0 +1,2574 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod comp1 { + use super::*; + + pin! { + for [ + PA0<8>, + + PA6<8>, + + PA11<8>, + + PB8<8>, + + #[cfg(feature = "gpio-g47x")] + PF4<2>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PA2<8>, + + PA7<8>, + + PA12<8>, + + PB9<8>, + ], + } +} + +pub mod comp3 { + use super::*; + + pin! { + for [ + PB7<8>, + + PB15<3>, + + PC2<3>, + ], + } +} + +pub mod comp4 { + use super::*; + + pin! { + for [ + PB1<8>, + + PB6<8>, + + PB14<8>, + ], + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod comp5 { + use super::*; + + pin! { + for [ + PA9<8>, + + PC7<7>, + ], + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod comp6 { + use super::*; + + pin! { + for [ + PA10<8>, + + PC6<7>, + ], + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod comp7 { + use super::*; + + pin! { + for [ + PA8<8>, + + PC8<7>, + ], + } +} + +/*pub mod crs { + use super::*; + + pin! { + for [ + PA10<3>, + + PB3<3>, + ], + } +}*/ + +pub mod fdcan1 { + use super::*; + + pin! { + for [ + PA11<9>, + + PB8<9>, + + PD0<9>, + ], + + for [ + PA12<9>, + + PB9<9>, + + PD1<9>, + ], + } +} + +#[cfg(any(feature = "gpio-g47x", feature = "gpio-g49x"))] +pub mod fdcan2 { + use super::*; + + pin! { + for [ + PB5<9>, + + PB12<9>, + ], + + for [ + PB6<9>, + + PB13<9>, + ], + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod fdcan3 { + use super::*; + + pin! { + for [ + PA8<11>, + + PB3<11>, + ], + + for [ + PA15<11>, + + PB4<11>, + ], + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod fmc { + use super::*; + + pin! { + for [ + PF10<12, Speed::VeryHigh>, + ], + + for [ + PF7<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PF8<12, Speed::VeryHigh>, + ], + + for [ + PF9<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PG6<12, Speed::VeryHigh>, + + PG7<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG8<12, Speed::VeryHigh>, + ], + + for [ + PF11<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod hrtim1 { + use super::*; + + pin! { + for [ // High speed + PA8<13>, + ], + + for [ + PA9<13>, + ], + + for [ + PA10<13>, + ], + + for [ + PA11<13>, + ], + + for [ + PB12<13>, + ], + + for [ + PB13<13>, + ], + + for [ + PB14<13>, + ], + + for [ + PB15<13>, + ], + + for [ + PC8<3>, + ], + + for [ + PC9<3>, + ], + + for [ + PC6<13>, + ], + + for [ + PC7<13>, + ], + + for [ // Low speed + PC12<3>, + ], + + for [ + PC5<13>, + + PC6<3>, + ], + + for [ + PC11<3>, + ], + + for [ + PB7<13>, + ], + + for [ + PB6<13>, + ], + + for [ + PB9<13>, + ], + + for [ + PB5<13>, + ], + + for [ + PB4<13>, + ], + + for [ + PB8<13>, + ], + + for [ + PB3<13>, + ], + + for [ + PA12<13>, + ], + + for [ + PA15<13>, + ], + + for [ + PB10<13>, + ], + + for [ + PB11<13>, + ], + + for [ + PB0<13>, + + PC7<3>, + ], + + for [ + PC10<13>, + ], + + for [ + PB2<13>, + + PB6<12>, + ], + } + + pin! { + default:PushPull for [ // High speed + PB1<13>, + + PB3<12>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PA13<4>, + + PA15<4>, + + PB8<4>, + ], + + for [ + PA14<4>, + + PB7<4>, + + PB9<4>, + ], + + for [ + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PA9<4>, + + PC4<4>, + + #[cfg(feature = "gpio-g47x")] + PF6<4>, + ], + + for [ + PA8<4>, + + PF0<4>, + ], + + for [ + PA10<4>, + + PB12<4>, + + PF2<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA8<2>, + + PC8<8>, + + #[cfg(feature = "gpio-g47x")] + PF3<4>, + + #[cfg(feature = "gpio-g47x")] + PG7<4>, + ], + + for [ + PB5<8>, + + PC9<8>, + + PC11<8>, + + #[cfg(feature = "gpio-g47x")] + PF4<4>, + + #[cfg(feature = "gpio-g47x")] + PG8<4>, + ], + + for [ + PA9<2>, + + PB2<4>, + + #[cfg(feature = "gpio-g47x")] + PG6<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod i2c4 { + use super::*; + + pin! { + for [ + PA13<3>, + + PC6<8>, + + PF14<4>, + + PG3<4>, + ], + + for [ + PB7<3>, + + PC7<8>, + + PF15<4>, + + PG4<4>, + ], + + for [ + PA14<3>, + + PD11<4>, + + PF13<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PA12<5>, + + PC9<5>, + ], + } +} + +pub mod i2s2 { + use super::*; + + pin! { + for [ + PB13<5>, + + PF1<5>, + ], + + for no:NoPin, [ + PA8<5>, + + PC6<6>, + ], + + for [ + PA11<5>, + + PB15<5>, + ], + + for [ + PB12<5>, + + PF0<5>, + ], + } +} + +pub mod i2s3 { + use super::*; + + pin! { + for [ + PB3<6>, + + PC10<6>, + ], + + for no:NoPin, [ + PA9<5>, + + PC7<6>, + ], + + for [ + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<5>, + + PB9<6>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<11>, + + PC3<1>, + ], + + for [ + PB5<11>, + + PC0<1>, + ], + + for [ + PB7<11>, + + PC2<1>, + ], + } + + pin! { + default:PushPull for [ + PA14<1>, + + PB2<1>, + + PC1<1>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<12>, + + PB13<8>, + + #[cfg(feature = "gpio-g47x")] + PG5<8>, + ], + + for [ + PB1<12>, + + PB12<8>, + + #[cfg(feature = "gpio-g47x")] + PG6<8>, + ], + + for [ + PB1<12>, + + PB12<8>, + + #[cfg(feature = "gpio-g47x")] + PG6<8>, + ], + + for [ + PA3<12>, + + PB10<8>, + + PC0<8>, + + #[cfg(feature = "gpio-g47x")] + PG8<8>, + ], + } + + pin! { + default:PushPull for [ + PA2<12>, + + PB11<8>, + + PC1<8>, + + #[cfg(feature = "gpio-g47x")] + PG7<8>, + ], + } +} + +#[cfg(any(feature = "gpio-g47x", feature = "gpio-g49x"))] +pub mod quadspi1 { + use super::*; + + pin! { + for [ + PB1<10>, + + PE12<10>, + + #[cfg(feature = "gpio-g47x")] + PF8<10>, + ], + + for [ + PB0<10>, + + PE13<10>, + + PF9<10>, + ], + + for [ + PA7<10>, + + PE14<10>, + + #[cfg(feature = "gpio-g47x")] + PF7<10>, + ], + + for [ + PA6<10>, + + PE15<10>, + + #[cfg(feature = "gpio-g47x")] + PF6<10>, + ], + + for [ + PA2<10>, + + PB11<10>, + + PE11<10>, + ], + + for [ + PC1<10>, + + PD4<10>, + ], + + for [ + PB2<10>, + + PC2<10>, + + PD5<10>, + ], + + for [ + PC3<10>, + + PD6<10>, + ], + + for [ + PC4<10>, + + PD7<10>, + ], + + for [ + PD3<10>, + ], + + for [ + PA3<10>, + + PB10<10>, + + PE10<10>, + + PF10<10>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + + PG10<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PB2<0>, + ], + + for [ + PA1<0>, + + PB15<0>, + ], + } +} + +pub mod sai1 { + use super::*; + + pin! { + for [ + PA3<3>, + + PB8<3>, + + PE2<3>, + + #[cfg(feature = "gpio-g47x")] + PG7<3>, + ], + + for [ + PA8<12>, + + PE5<3>, + ], + + for [ + PA10<12>, + + PC3<3>, + + PD6<3>, + + PE6<3>, + ], + + for [ + PB9<3>, + + PE4<3>, + ], + + for [ + PC5<3>, + + PF10<13>, + ], + + for [ + PA9<14>, + + PB9<14>, + + PE4<13>, + ], + + for [ + PA4<13>, + + PA14<13>, + + PB6<14>, + + PE9<13>, + + PF9<13>, + ], + + for no:NoPin, [ + PA3<13>, + + PB8<14>, + + PE2<13>, + + #[cfg(feature = "gpio-g47x")] + PG7<13>, + ], + + for no:NoPin, [ + PB4<14>, + + PE10<13>, + + #[cfg(feature = "gpio-g47x")] + PF7<13>, + ], + + for [ + PA8<14>, + + PB10<14>, + + PE5<13>, + ], + + for [ + PB3<14>, + + PE8<13>, + + #[cfg(feature = "gpio-g47x")] + PF8<13>, + ], + + for [ + PA10<14>, + + PC1<13>, + + PC3<13>, + + PD6<13>, + + PE6<13>, + ], + + for [ + PA13<13>, + + PB5<12>, + + PE3<13>, + + PE7<13>, + + #[cfg(feature = "gpio-g47x")] + PF6<3>, + ], + } + use crate::pac::SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PB4<5>, + + #[cfg(feature = "gpio-g47x")] + PG3<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PB5<5>, + + #[cfg(feature = "gpio-g47x")] + PG4<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + #[cfg(feature = "gpio-g47x")] + PG5<5>, + ], + + for no:NoPin, [ + PA5<5>, + + PB3<5>, + + #[cfg(feature = "gpio-g47x")] + PG2<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PA10<5>, + + PB14<5>, + ], + + for no:NoPin, [ + PA11<5>, + + PB15<5>, + ], + + for [ + PB12<5>, + + PD15<6>, + + PF0<5>, + ], + + for no:NoPin, [ + PB13<5>, + + PF1<5>, + + PF9<5>, + + PF10<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + + #[cfg(feature = "gpio-g47x")] + PG9<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod spi4 { + use super::*; + + pin! { + for no:NoPin, [ + PE5<5>, + + PE13<5>, + ], + + for no:NoPin, [ + PE6<5>, + + PE14<5>, + ], + + for [ + PE3<5>, + + PE4<5>, + + PE11<5>, + ], + + for no:NoPin, [ + PE2<5>, + + PE12<5>, + ], + } + impl SpiCommon for crate::pac::SPI4 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + #[cfg(feature = "gpio-g47x")] + PC3<0>, + ], + + for [ + PE2<0>, + ], + + for [ + PE3<0>, + ], + + for [ + PE4<0>, + ], + + for [ + PE5<0>, + ], + + for [ + PE6<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<6>, + + PC0<2>, + + PE9<2>, + ], + + default:PushPull for [ + PA7<6>, + + PA11<6>, + + PB13<6>, + + PC13<4>, + + PE8<2>, + ], + + default:PushPull for [ + PA9<6>, + + PC1<2>, + + PE11<2>, + ], + + default:PushPull for [ + PA12<6>, + + PB0<6>, + + PB14<6>, + + PE10<2>, + ], + + default:PushPull for [ + PA10<6>, + + PC2<2>, + + PE13<2>, + ], + + default:PushPull for [ + PB1<6>, + + PB9<12>, + + PB15<4>, + + PE12<2>, + + PF0<6>, + ], + + default:PushPull for [ + PA11<11>, + + PC3<2>, + + PE14<2>, + ], + + default:PushPull for [ + PC5<6>, + + PE15<6>, + ], + } + + pin! { + for [ + PA6<6>, + + PA14<6>, + + PA15<9>, + + PB8<12>, + + PB10<12>, + + PB12<6>, + + PC13<2>, + + PE15<2>, + ], + + for [ + PA11<12>, + + PC3<6>, + + PE14<6>, + ], + + for [ + PA12<11>, + + PC4<2>, + + PE7<2>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimNCPin<3> for TIM { + type ChN = Ch4N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + + PD3<2>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + + PD4<2>, + ], + + default:PushPull for [ + PA2<1>, + + PA9<10>, + + PB10<1>, + + PD7<2>, + ], + + default:PushPull for [ + PA3<1>, + + PA10<10>, + + PB11<1>, + + PD6<2>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<14>, + + PD3<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE2<2>, + ], + + default:PushPull for [ + PA4<2>, + + PA7<2>, + + PB5<2>, + + PC7<2>, + + PE3<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB1<2>, + + PB7<10>, + + PC9<2>, + + PE5<2>, + ], + } + + pin! { + for [ + PB3<10>, + + PD2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PA11<10>, + + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PA12<10>, + + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PA13<10>, + + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + + #[cfg(feature = "gpio-g47x")] + PF6<2>, + ], + } + + pin! { + for [ + PA8<10>, + + PB3<2>, + + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-g47x")] +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PB2<2>, + + PF6<6>, + ], + + default:PushPull for [ + PA1<2>, + + PC12<1>, + + PF7<6>, + ], + + default:PushPull for [ + PA2<2>, + + PE8<1>, + + PF8<6>, + ], + + default:PushPull for [ + PA3<2>, + + PE9<1>, + + PF9<6>, + ], + } + + pin! { + for [ + PB12<2>, + + PD11<1>, + + PF6<1>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PA15<2>, + + PB6<5>, + + PC6<4>, + ], + + default:PushPull for [ + PA7<4>, + + PB3<4>, + + PC10<4>, + ], + + default:PushPull for [ + PA14<5>, + + PB8<10>, + + PC7<4>, + ], + + default:PushPull for [ + PB0<4>, + + PB4<4>, + + PC11<4>, + ], + + default:PushPull for [ + PB9<10>, + + PC8<4>, + ], + + default:PushPull for [ + PB1<4>, + + PB5<3>, + + PC12<4>, + ], + + default:PushPull for [ + PC9<4>, + + PD1<4>, + ], + + default:PushPull for [ + PC13<6>, + + PD0<6>, + ], + } + + pin! { + for [ + PA0<9>, + + PA6<4>, + + PA10<11>, + + PB7<5>, + + PD2<4>, + ], + + for [ + PB6<10>, + + PC9<6>, + + PD1<6>, + ], + + for [ + PA0<10>, + + PB6<6>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimNCPin<3> for TIM { + type ChN = Ch4N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<9>, + + PB14<1>, + + PF9<3>, + ], + + default:PushPull for [ + PA1<9>, + + PB15<2>, + + #[cfg(feature = "gpio-g47x")] + PG9<14>, + ], + + default:PushPull for [ + PA3<9>, + + PB15<1>, + + PF10<3>, + ], + } + + pin! { + for [ + PA9<9>, + + PC5<2>, + ], + + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<1>, + + PA12<1>, + + PB4<1>, + + PB8<1>, + + PE0<4>, + ], + + default:PushPull for [ + PA13<1>, + + PB6<1>, + ], + } + + pin! { + for [ + PB5<1>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<1>, + + PB5<10>, + + PB9<1>, + + PE1<4>, + ], + + default:PushPull for [ + PB7<1>, + ], + } + + pin! { + for [ + PA10<1>, + + PB4<10>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +#[cfg(any(feature = "gpio-g47x", feature = "gpio-g49x"))] +pub mod tim20 { + use super::*; + + pin! { + default:PushPull for [ + PB2<3>, + + PE2<6>, + + #[cfg(feature = "gpio-g47x")] + PF12<2>, + ], + + default:PushPull for [ + PE4<6>, + + #[cfg(feature = "gpio-g47x")] + PF4<3>, + + #[cfg(feature = "gpio-g47x")] + PG0<2>, + ], + + default:PushPull for [ + PC2<6>, + + PE3<6>, + + #[cfg(feature = "gpio-g47x")] + PF13<2>, + ], + + default:PushPull for [ + PE5<6>, + + #[cfg(feature = "gpio-g47x")] + PF5<2>, + + #[cfg(feature = "gpio-g47x")] + PG1<2>, + ], + + default:PushPull for [ + PC8<6>, + + PF2<2>, + + #[cfg(feature = "gpio-g47x")] + PF14<2>, + ], + + default:PushPull for [ + PE6<6>, + + #[cfg(feature = "gpio-g47x")] + PG2<2>, + ], + + default:PushPull for [ + PE1<6>, + + #[cfg(feature = "gpio-g47x")] + PF3<2>, + + #[cfg(feature = "gpio-g47x")] + PF15<2>, + ], + + default:PushPull for [ + PE0<3>, + + #[cfg(feature = "gpio-g47x")] + PG3<6>, + ], + } + + pin! { + for [ + #[cfg(feature = "gpio-g47x")] + PF7<2>, + + PF9<2>, + + #[cfg(feature = "gpio-g47x")] + PG3<2>, + + #[cfg(feature = "gpio-g47x")] + PG6<2>, + ], + + for [ + #[cfg(feature = "gpio-g47x")] + PF8<2>, + + PF10<2>, + + #[cfg(feature = "gpio-g47x")] + PG4<2>, + ], + + for [ + #[cfg(feature = "gpio-g49x")] + PA15<3>, + + PE0<6>, + + #[cfg(feature = "gpio-g47x")] + PF11<2>, + + #[cfg(feature = "gpio-g47x")] + PG5<2>, + ], + } + + use crate::pac::TIM20 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimNCPin<3> for TIM { + type ChN = Ch4N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod ucpd1 { + use super::*; + + pin! { + for [ + PA2<14>, + + PA5<14>, + + PA7<14>, + + PB0<14>, + + PC12<14>, + ], + + for [ + PA2<14>, + + PA5<14>, + + PA7<14>, + + PB0<14>, + + PC12<14>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + PC5<7>, + + PE1<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + PC4<7>, + + PE0<7>, + + #[cfg(feature = "gpio-g47x")] + PG9<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PB5<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PA15<7>, + + PB4<7>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PA14<7>, + + PB3<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PA13<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + + #[cfg(feature = "gpio-g47x")] + PF6<7>, + ], + + for [ + PA13<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + + #[cfg(feature = "gpio-g47x")] + PF6<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB8<7>, + + PB11<7>, + + PC11<7>, + + PD9<7>, + + PE15<7>, + ], + + default:PushPull for no:NoPin, [ + PB9<7>, + + PB10<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart4 { + use super::*; + + pin! { + for [ + PB7<14>, + ], + + for [ + PA15<8>, + ], + + for [ + PA15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC11<5>, + ], + + default:PushPull for no:NoPin, [ + PC10<5>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-g47x", feature = "gpio-g49x"))] +pub mod uart5 { + use super::*; + + pin! { + for [ + PB5<14>, + ], + + for [ + PB4<8>, + ], + + for [ + PB4<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PD2<5>, + ], + + default:PushPull for no:NoPin, [ + PC12<5>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} diff --git a/src/gpio/alt/h7.rs b/src/gpio/alt/h7.rs new file mode 100644 index 00000000..856283c9 --- /dev/null +++ b/src/gpio/alt/h7.rs @@ -0,0 +1,5265 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +/*#[cfg(feature = "gpio-h747")] +pub mod comp { + use super::*; + + pin! { + for [ + PE15<13>, + ], + } +}*/ + +pub mod comp1 { + use super::*; + + pin! { + for [ + PC5<13>, + + PE12<13>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PE8<13>, + + PE13<13>, + ], + } +} + +/*pub mod crs { + use super::*; + + pin! { + for [ + PB3<10>, + ], + } +}*/ + +pub mod dcmi { + use super::*; + + pin! { + for [ + PA9<13>, + + PC6<13>, + + PH9<13>, + ], + + for [ + PA10<13>, + + PC7<13>, + + PH10<13>, + ], + + for [ + PB5<13>, + + PD6<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI3<13>, + ], + + for [ + PD2<13>, + + PF10<13>, + + PH15<13>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PD12<13>, + + PF11<13>, + + PG6<13>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PD13<13>, + + PG7<13>, + + PG15<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI0<13>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PB13<13>, + + PC8<13>, + + PE0<13>, + + PG10<13>, + + PH11<13>, + ], + + for [ + PC9<13>, + + PE1<13>, + + PG11<13>, + + PH12<13>, + ], + + for [ + PC11<13>, + + PE4<13>, + + PH14<13>, + ], + + for [ + PB6<13>, + + PD3<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI4<13>, + ], + + for [ + PB8<13>, + + PE5<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI6<13>, + ], + + for [ + PB9<13>, + + PE6<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI7<13>, + ], + + for [ + PC10<13>, + + PH6<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<13>, + ], + + for [ + PC12<13>, + + PH7<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI2<13>, + ], + + for [ + PA4<13>, + + PH8<13>, + ], + + for [ + PA6<13>, + ], + + for [ + PB7<13>, + + PG9<13>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI5<13>, + ], + } +} + +pub mod debug { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PE2<0>, + ], + + for [ + PC1<0>, + + PE3<0>, + + PG13<0>, + ], + + for [ + PC8<0>, + + PE4<0>, + + PG14<0>, + ], + + for [ + PD2<0>, + + PE5<0>, + ], + + for [ + PC12<0>, + + PE6<0>, + ], + + for [ + PC7<0>, + ], + } + + #[cfg(feature = "gpio-h72")] + pin! { + for [ + PB4<0>, + ], + } + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + pin! { + for [ + PJ7<0>, + ], + + for [ + PJ12<0>, + ], + } +} + +pub mod dfsdm1 { + use super::*; + + pin! { + for [ + PC0<3>, + ], + + for [ + PB2<4>, + + PB13<6>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC2<3>, + + PD7<6>, + ], + + for [ + PB15<6>, + + PC4<3>, + + PE8<3>, + ], + + for [ + PC6<4>, + + PD8<3>, + + PE5<3>, + ], + + for [ + PC1<4>, + + PD6<3>, + + PE11<3>, + ], + + for [ + PB7<11>, + + PC10<3>, + + PE13<3>, + ], + + for [ + PD0<3>, + + PF14<3>, + ], + + for [ + PB8<3>, + + PB11<6>, + ], + + for [ + PB0<6>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC2<6>, + + PD3<3>, + + PD10<3>, + + PE9<3>, + ], + + for [ + PC1<3>, + ], + + for [ + PB1<6>, + + PB12<6>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC3<3>, + + PD6<4>, + ], + + for [ + PB14<6>, + + PC5<3>, + + PE7<3>, + ], + + for [ + PC7<4>, + + PD9<3>, + + PE4<3>, + ], + + for [ + PC0<6>, + + PD7<3>, + + PE10<3>, + ], + + for [ + PB6<11>, + + PC11<3>, + + PE12<3>, + ], + + for [ + PD1<3>, + + PF13<3>, + ], + + for [ + PB9<3>, + + PB10<6>, + ], + } + + use crate::pac::DFSDM1 as DFSDM; + impl DfsdmBasic for DFSDM { + type Ckin0 = Ckin0; + type Ckin1 = Ckin1; + type Ckout = Ckout; + type Datin0 = Datin0; + type Datin1 = Datin1; + } + impl DfsdmGeneral for DFSDM { + type Ckin2 = Ckin2; + type Ckin3 = Ckin3; + type Datin2 = Datin2; + type Datin3 = Datin3; + } + + impl DfsdmAdvanced for DFSDM { + type Ckin4 = Ckin4; + type Ckin5 = Ckin5; + type Ckin6 = Ckin6; + type Ckin7 = Ckin7; + type Datin4 = Datin4; + type Datin5 = Datin5; + type Datin6 = Datin6; + type Datin7 = Datin7; + } +} + +#[cfg(feature = "gpio-h7a2")] +pub mod dfsdm2 { + use super::*; + + pin! { + for [ + PC10<4>, + ], + + for [ + PA2<6>, + + PB13<4>, + ], + + for [ + PB0<4>, + + PC12<4>, + + PD10<4>, + ], + + for [ + PC11<4>, + ], + + for [ + PA7<4>, + + PB12<11>, + ], + } + + use crate::pac::DFSDM2 as DFSDM; + impl DfsdmBasic for DFSDM { + type Ckin0 = Ckin0; + type Ckin1 = Ckin1; + type Ckout = Ckout; + type Datin0 = Datin0; + type Datin1 = Datin1; + } +} + +#[cfg(feature = "gpio-h747")] +pub mod dsihost { + use super::*; + + pin! { + for [ + PA15<13>, + + PB11<13>, + + PJ2<13>, + ], + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h747"))] +pub mod eth { + use super::*; + + pin! { + for [ + PA3<11>, + + PH3<11>, + ], + + for [ + PA0<11>, + + PH2<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PC1<11>, + ], + + for [ + PA2<11>, + ], + + for [ + PB5<11>, + + PG8<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PB10<11>, + + #[cfg(feature = "gpio-h747")] + PI10<11>, + ], + + for [ + PC4<11>, + ], + + for [ + PC5<11>, + ], + + for [ + PB0<11>, + + PH6<11>, + ], + + for [ + PB1<11>, + + PH7<11>, + ], + + for [ + PB11<11>, + + PG11<11>, + ], + + for [ + PB12<11>, + + PG13<11>, + ], + + for [ + PB13<11>, + + PG12<11>, + + PG14<11>, + ], + + for [ + PB8<11>, + + PE2<11>, + ], + } + + #[cfg(feature = "gpio-h747")] + pin! { + for [ + PC3<11>, + ], + + for [ + PC2<11>, + ], + } + + #[cfg(feature = "gpio-h72")] + pin! { + for [ + PA9<11>, + + PB2<11>, + ], + } +} + +pub mod fdcan1 { + use super::*; + + pin! { + for [ + PA11<9>, + + PB8<9>, + + PD0<9>, + + PH14<9>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI9<9>, + ], + + for [ + PA12<9>, + + PB9<9>, + + PD1<9>, + + PH13<9>, + ], + } +} + +pub mod fdcan2 { + use super::*; + + pin! { + for [ + PB5<9>, + + PB12<9>, + ], + + for [ + PB6<9>, + + PB13<9>, + ], + } +} + +#[cfg(feature = "gpio-h72")] +pub mod fdcan3 { + use super::*; + + pin! { + for [ + PD12<5>, + + PF6<2>, + + PG10<2>, + ], + + for [ + PD13<5>, + + PF7<2>, + + PG9<2>, + ], + } +} + +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA0<12, Speed::VeryHigh>, + + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC4<1, Speed::VeryHigh>, + + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC0<9, Speed::VeryHigh>, + + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PB14<12, Speed::VeryHigh>, + + PE13<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PB15<12, Speed::VeryHigh>, + + PE14<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC0<1, Speed::VeryHigh>, + + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PH8<12, Speed::VeryHigh>, + ], + + for [ + PH9<12, Speed::VeryHigh>, + ], + + for [ + PH10<12, Speed::VeryHigh>, + ], + + for [ + PH11<12, Speed::VeryHigh>, + ], + + for [ + PH12<12, Speed::VeryHigh>, + ], + + for [ + PH13<12, Speed::VeryHigh>, + ], + + for [ + PH14<12, Speed::VeryHigh>, + ], + + for [ + PH15<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC12<1, Speed::VeryHigh>, + + PE9<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PD2<1, Speed::VeryHigh>, + + PE10<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA4<12, Speed::VeryHigh>, + + PE11<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA5<12, Speed::VeryHigh>, + + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PB14<12, Speed::VeryHigh>, + + PE13<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PB15<12, Speed::VeryHigh>, + + PE14<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC0<1, Speed::VeryHigh>, + + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC12<1, Speed::VeryHigh>, + + PE9<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PD2<1, Speed::VeryHigh>, + + PE10<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA4<12, Speed::VeryHigh>, + + PE11<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA5<12, Speed::VeryHigh>, + + PE12<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC8<10, Speed::VeryHigh>, + + PG7<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PC8<9, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + PC7<9, Speed::VeryHigh>, + + PD7<12, Speed::VeryHigh>, + ], + + for [ + PC8<9, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG6<12, Speed::VeryHigh>, + + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PC6<9, Speed::VeryHigh>, + + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC3<12, Speed::VeryHigh>, + + PC5<12, Speed::VeryHigh>, + + PH2<12, Speed::VeryHigh>, + ], + + for [ + PB5<12, Speed::VeryHigh>, + + PH7<12, Speed::VeryHigh>, + ], + + for [ + PG8<12, Speed::VeryHigh>, + ], + + for [ + PG15<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC2<12, Speed::VeryHigh>, + + PC4<12, Speed::VeryHigh>, + + PH3<12, Speed::VeryHigh>, + ], + + for [ + PB6<12, Speed::VeryHigh>, + + PH6<12, Speed::VeryHigh>, + ], + + for [ + PF11<12, Speed::VeryHigh>, + ], + + for [ + PA7<12, Speed::VeryHigh>, + + PC0<12, Speed::VeryHigh>, + + PH5<12, Speed::VeryHigh>, + ], + } + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + pin! { + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PI0<12, Speed::VeryHigh>, + ], + + for [ + PI1<12, Speed::VeryHigh>, + ], + + for [ + PI2<12, Speed::VeryHigh>, + ], + + for [ + PI3<12, Speed::VeryHigh>, + ], + + for [ + PI6<12, Speed::VeryHigh>, + ], + + for [ + PI7<12, Speed::VeryHigh>, + ], + + for [ + PI9<12, Speed::VeryHigh>, + ], + + for [ + PI10<12, Speed::VeryHigh>, + ], + + for [ + PI4<12, Speed::VeryHigh>, + ], + + for [ + PI5<12, Speed::VeryHigh>, + ], + } +} + +#[cfg(feature = "gpio-h747")] +pub mod hrtim { + use super::*; + + pin! { + for [ // High speed + PC6<1>, + ], + + for [ + PC7<1>, + ], + + for [ + PC8<1>, + ], + + for [ + PA8<2>, + ], + + for [ + PA9<2>, + ], + + for [ + PA10<2>, + ], + + for [ + PA11<2>, + ], + + for [ + PA12<2>, + ], + + for [ + PG6<2>, + ], + + for [ + PG7<2>, + ], + + for [ // Low speed + PC10<2>, + ], + + for [ + PG13<2>, + ], + + for [ + PC12<2>, + ], + + for [ + PD5<2>, + ], + + for [ + PG11<2>, + ], + + for [ + PG12<2>, + ], + + for [ + PB4<3>, + ], + + for [ + PB5<3>, + ], + + for [ + PB6<3>, + ], + + for [ + PB7<3>, + ], + + for [ + PA15<2>, + ], + + for [ + PC11<2>, + ], + + for [ + PD4<2>, + ], + + for [ + PB3<2>, + ], + + for [ + PG10<2>, + ], + + for [ + PB11<2>, + + PE0<3>, + ], + } + + pin! { + default:PushPull for [ // High speed + PB10<2>, + + PE1<3>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + ], + + for [ + PB7<4>, + + PB9<4>, + ], + + for [ + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PF1<4>, + + PH4<4>, + ], + + for [ + PB11<4>, + + PF0<4>, + + PH5<4>, + ], + + for [ + PB12<4>, + + PF2<4>, + + PH6<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA8<4>, + + PH7<4>, + ], + + for [ + PC9<4>, + + PH8<4>, + ], + + for [ + PA9<4>, + + PH9<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c4 { + use super::*; + + pin! { + for [ + PB6<6>, + + PB8<6>, + + PD12<4>, + + PF14<4>, + + PH11<4>, + ], + + for [ + PB7<6>, + + PB9<6>, + + PD13<4>, + + PF15<4>, + + PH12<4>, + ], + + for [ + PB5<6>, + + PB9<11>, + + PD11<4>, + + PF13<4>, + + PH10<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(feature = "gpio-h72")] +pub mod i2c5 { + use super::*; + + pin! { + for [ + PA8<6>, + + PC11<4>, + + PF1<6>, + ], + + for [ + PC9<6>, + + PC10<4>, + + PF0<6>, + ], + + for [ + PA9<6>, + + PC12<4>, + + PF2<6>, + ], + } + use crate::pac::I2C5 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PC9<5>, + ], + } +} + +pub mod i2s1 { + use super::*; + + pin! { + for [ + PA5<5>, + + PB3<5>, + + PG11<5>, + ], + + for no:NoPin, [ + PC4<5>, + ], + + for [ + PA6<5>, + + PB4<5>, + + PG9<5>, + ], + + for [ + PA7<5>, + + PB5<5>, + + PD7<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PG10<5>, + ], + } +} + +pub mod i2s2 { + use super::*; + + pin! { + for [ + PA9<5>, + + PA12<5>, + + PB10<5>, + + PB13<5>, + + PD3<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<5>, + ], + + for no:NoPin, [ + PC6<5>, + ], + + for [ + PB14<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC2<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI2<5>, + ], + + for [ + PB15<5>, + + PC1<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC3<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI3<5>, + ], + + for [ + PA11<5>, + + PB4<7>, + + PB9<5>, + + PB12<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI0<5>, + ], + } +} + +pub mod i2s3 { + use super::*; + + pin! { + for [ + PB3<6>, + + PC10<6>, + ], + + for no:NoPin, [ + PC7<6>, + ], + + for [ + PB4<6>, + + PC11<6>, + ], + + for [ + PB2<7>, + + PB5<7>, + + PC12<6>, + + PD6<5>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] +pub mod i2s6 { + use super::*; + + pin! { + for [ + PA5<8>, + + PB3<8>, + + PC12<5>, + + PG13<5>, + ], + + for no:NoPin, [ + PA3<5>, + ], + + for [ + PA6<8>, + + PB4<8>, + + PG12<5>, + ], + + for [ + PA7<8>, + + PB5<8>, + + PG14<5>, + ], + + for [ + PA0<5>, + + PA4<8>, + + PA15<7>, + + PG8<5>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PE0<1>, + + PG14<1>, + ], + + for [ + PD12<1>, + + PG12<1>, + ], + + for [ + PE1<1>, + + PG11<1>, + + PH2<1>, + ], + + default:PushPull for [ + PD13<1>, + + PG13<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PB11<3>, + + PE0<4>, + ], + + for [ + PB10<3>, + + PD12<3>, + ], + + for [ + PD11<3>, + ], + + default:PushPull for [ + PB13<3>, + ], + } +} + +pub mod lptim3 { + use super::*; + + pin! { + default:PushPull for [ + PA1<3>, + ], + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h747"))] +pub mod lptim4 { + use super::*; + + pin! { + default:PushPull for [ + PA2<3>, + ], + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h747"))] +pub mod lptim5 { + use super::*; + + pin! { + default:PushPull for [ + PA3<3>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA11<3>, + ], + + for [ + PA12<3>, + ], + + for [ + PA12<3>, + ], + + for [ + PA10<3>, + + PB7<8>, + ], + } + + pin! { + default:PushPull for [ + PA9<3>, + + PB6<8>, + ], + } +} + +pub mod ltdc { + use super::*; + + pin! { + for [ + PE4<14>, + + PG14<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ12<14>, + ], + + for [ + PA10<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC10<10>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PD0<14>, + + PG12<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ13<14>, + ], + + for [ + PA3<9>, + + PC9<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PD2<14>, + + PD6<14>, + + PG10<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ14<14>, + ], + + for [ + PA8<13>, + + PD10<14>, + + PG11<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ15<14>, + ], + + for [ + PA10<12>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC11<14>, + + PE12<14>, + + PG12<9>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI4<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ13<9>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PK3<14>, + ], + + for [ + PA3<14>, + + #[cfg(feature = "gpio-h72")] + PB5<3>, + + #[cfg(feature = "gpio-h7a2")] + PB5<11>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI5<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PK4<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PA15<14>, + + PB8<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI6<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PK5<14>, + ], + + for [ + PB9<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PD2<9>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI7<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PK6<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PB14<14>, + + PE14<14>, + + PG7<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI14<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC5<14>, + + PE13<14>, + + PF10<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PK7<14>, + ], + + for [ + PB1<14>, + + PE5<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ7<14>, + ], + + for [ + PB0<14>, + + PE6<14>, + + PJ8<14>, + ], + + for [ + PA6<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC0<11>, + + PH13<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI15<9>, + + PJ9<14>, + ], + + for [ + PC9<10>, + + PE11<14>, + + PG10<9>, + + PH14<14>, + + PJ10<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ12<9>, + ], + + for [ + PB10<14>, + + PH4<14>, + + PH15<14>, + + PJ11<14>, + ], + + for [ + PB11<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC1<14>, + + PH4<9>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI0<14>, + + PK0<14>, + ], + + for [ + PC7<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI11<9>, + + PK1<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PB15<14>, + + PD3<14>, + + PG8<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI2<14>, + + PK2<14>, + ], + + for [ + PC6<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI10<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI12<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PE0<14>, + + PG13<14>, + + PH2<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI15<14>, + ], + + for [ + PA2<14>, + + PH3<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ0<14>, + ], + + for [ + PA1<14>, + + PC10<14>, + + PH8<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ1<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PA15<9>, + + PB0<9>, + + PH9<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ2<14>, + ], + + for [ + PA5<14>, + + PA11<14>, + + PH10<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ3<14>, + ], + + for [ + PA9<14>, + + PA12<14>, + + PC0<14>, + + PH11<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ4<14>, + ], + + for [ + PA8<14>, + + PB1<9>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC12<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PE1<14>, + + PH12<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ5<14>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC4<14>, + + PE15<14>, + + PG6<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ0<9>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ6<14>, + ], + + for [ + PA4<14>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PA7<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI9<14>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI13<14>, + ], + } +} + +pub mod mdios { + use super::*; + + pin! { + for [ + PA6<11>, + + PC1<12>, + ], + + for [ + PA2<12>, + + PA10<11>, + ], + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] +pub mod octospim { + use super::*; + + pin! { + for [ // High speed + #[cfg(feature = "gpio-h7a2")] + PA3<3>, + + #[cfg(feature = "gpio-h72")] + PA3<12>, + + PB2<9>, + + PF10<9>, + ], + + for [ + #[cfg(feature = "gpio-h7a2")] + PA1<11>, + + #[cfg(feature = "gpio-h72")] + PA1<12>, + + PB2<10>, + + PC5<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA2<6>, + + #[cfg(feature = "gpio-h72")] + PB1<4>, + + #[cfg(feature = "gpio-h7a2")] + PB1<11>, + + #[cfg(feature = "gpio-h72")] + PB12<12>, + + #[cfg(feature = "gpio-h7a2")] + PC3<9>, + + PC9<9>, + + PD11<9>, + + PF8<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PB0<4>, + + #[cfg(feature = "gpio-h7a2")] + PB0<11>, + + PC10<9>, + + PD12<9>, + + PF9<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA3<6>, + + PA7<10>, + + #[cfg(feature = "gpio-h72")] + PB13<4>, + + #[cfg(feature = "gpio-h7a2")] + PC2<9>, + + PE2<9>, + + PF7<10>, + ], + + for [ + PA1<9>, + + PA6<6>, + + PD13<9>, + + PF6<10>, + ], + + for [ + PC1<10>, + + PD4<10>, + + PE7<10>, + + PH2<9>, + ], + + for [ + #[cfg(feature = "gpio-h7a2")] + PC2<11>, + + PD5<10>, + + PE8<10>, + + PH3<9>, + ], + + for [ + #[cfg(feature = "gpio-h7a2")] + PC3<11>, + + PD6<10>, + + PE9<10>, + + PG9<9>, + ], + + for [ + PD7<10>, + + PE10<10>, + + PG14<9>, + ], + + for [ + PB12<3>, + + PF11<9>, + ], + + for [ + PB6<10>, + + PB10<9>, + + PC11<9>, + + PE11<11>, + + PG6<10>, + ], + + for [ + PF4<9>, + + #[cfg(feature = "gpio-h7a2")] + PI13<3>, + ], + + for [ + PF12<9>, + + PG7<9>, + + PG15<9>, + + #[cfg(feature = "gpio-h7a2")] + PK6<3>, + ], + + for [ + PF0<9>, + + #[cfg(feature = "gpio-h7a2")] + PI9<3>, + ], + + for [ + PF1<9>, + + #[cfg(feature = "gpio-h7a2")] + PI10<3>, + ], + + for [ + PF2<9>, + + #[cfg(feature = "gpio-h7a2")] + PI11<3>, + ], + + for [ + PF3<9>, + + #[cfg(feature = "gpio-h7a2")] + PI12<3>, + ], + + for [ + PG0<9>, + + #[cfg(feature = "gpio-h7a2")] + PJ1<3>, + ], + + for [ + PG1<9>, + + #[cfg(feature = "gpio-h7a2")] + PJ2<3>, + ], + + for [ + PG10<3>, + + #[cfg(feature = "gpio-h7a2")] + PK3<3>, + ], + + for [ + PG11<9>, + + #[cfg(feature = "gpio-h7a2")] + PK4<3>, + ], + + for [ + PF5<9>, + + #[cfg(feature = "gpio-h7a2")] + PI14<3>, + ], + + for [ + PG12<3>, + + #[cfg(feature = "gpio-h7a2")] + PK5<3>, + ], + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] +pub mod pssi { + use super::*; + + pin! { + for [ + PA9<13>, + + PC6<13>, + + PH9<13>, + ], + + for [ + PA10<13>, + + PC7<13>, + + PH10<13>, + ], + + for [ + PB5<13>, + + PD6<13>, + + #[cfg(feature = "gpio-h7a2")] + PI3<13>, + ], + + for [ + PD2<13>, + + PF10<13>, + + PH15<13>, + ], + + for [ + PD12<13>, + + PF11<13>, + + PG6<13>, + ], + + for [ + PD13<13>, + + PG7<13>, + + PG15<13>, + + #[cfg(feature = "gpio-h7a2")] + PI0<13>, + ], + + for [ + PA5<13>, + + PH4<13>, + + #[cfg(feature = "gpio-h7a2")] + PI10<13>, + ], + + for [ + PC5<4>, + + PF10<4>, + + #[cfg(feature = "gpio-h7a2")] + PI11<13>, + ], + + for [ + PB13<13>, + + PC8<13>, + + PE0<13>, + + PG10<13>, + + PH11<13>, + ], + + for [ + PC9<13>, + + PE1<13>, + + PG11<13>, + + PH12<13>, + ], + + for [ + PC11<13>, + + PE4<13>, + + PH14<13>, + ], + + for [ + PB6<13>, + + PD3<13>, + + #[cfg(feature = "gpio-h7a2")] + PI4<13>, + ], + + for [ + PB8<13>, + + PE5<13>, + + #[cfg(feature = "gpio-h7a2")] + PI6<13>, + ], + + for [ + PB9<13>, + + PE6<13>, + + #[cfg(feature = "gpio-h7a2")] + PI7<13>, + ], + + for [ + PC10<13>, + + PH6<13>, + + #[cfg(feature = "gpio-h7a2")] + PI1<13>, + ], + + for [ + PC12<13>, + + PH7<13>, + + #[cfg(feature = "gpio-h7a2")] + PI2<13>, + ], + + for [ + PA4<13>, + + PH8<13>, + ], + + for [ + PA6<13>, + ], + + for [ + PB7<13>, + + PG9<13>, + + #[cfg(feature = "gpio-h7a2")] + PI5<13>, + ], + } +} + +#[cfg(feature = "gpio-h7a2")] +pub mod pwr { + use super::*; + + pin! { + for [ + PC3<0>, + ], + + for [ + PC2<0>, + ], + + for [ + PA5<0>, + ], + } +} + +#[cfg(feature = "gpio-h747")] +pub mod quadspi { + use super::*; + + pin! { + for [ + PC9<9>, + + PD11<9>, + + PF8<10>, + ], + + for [ + PC10<9>, + + PD12<9>, + + PF9<10>, + ], + + for [ + PE2<9>, + + PF7<9>, + ], + + for [ + PA1<9>, + + PD13<9>, + + PF6<9>, + ], + + for [ + PB6<10>, + + PB10<9>, + + PG6<10>, + ], + + for [ + PE7<10>, + + PH2<9>, + ], + + for [ + PE8<10>, + + PH3<9>, + ], + + for [ + PE9<10>, + + PG9<9>, + ], + + for [ + PE10<10>, + + PG14<9>, + ], + + for [ + PC11<9>, + ], + + for [ + PB2<9>, + + PF10<9>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + + for [ + PC9<0>, + ], + } +} + +pub mod rtc { + use super::*; + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h747"))] + pin! { + for [ + PB2<0>, + ], + } + + pin! { + for [ + PB2<0>, + ], + + for [ + PB15<0>, + ], + } +} + +pub mod sai1 { + use super::*; + + pin! { + for [ + PE2<2>, + ], + + for [ + PE5<2>, + ], + + for [ + PB2<2>, + + PC1<2>, + + PD6<2>, + + PE6<2>, + ], + + for [ + PE4<2>, + ], + + for [ + PC5<2>, + + PF10<2>, + ], + + for [ + PE4<6>, + ], + + for [ + PF9<6>, + ], + + for no:NoPin, [ + PE2<6>, + + PG7<6>, + ], + + for no:NoPin, [ + PF7<6>, + ], + + for [ + PE5<6>, + ], + + for [ + PF8<6>, + ], + + for [ + PB2<6>, + + PC1<6>, + + PD6<6>, + + PE6<6>, + ], + + for [ + PE3<6>, + + PF6<6>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +#[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] +pub mod sai2 { + use super::*; + + pin! { + for [ + PD12<10>, + + PI7<10>, + ], + + for [ + PA12<8>, + + PC0<8>, + + PE13<10>, + + PG9<10>, + ], + + for no:NoPin, [ + PE0<10>, + + PI4<10>, + ], + + for no:NoPin, [ + PA1<10>, + + PE6<10>, + + PE14<10>, + + PH3<10>, + ], + + for [ + PD13<10>, + + PI5<10>, + ], + + for [ + PA2<8>, + + PE12<10>, + + PH2<10>, + ], + + for [ + PD11<10>, + + PI6<10>, + ], + + for [ + PA0<10>, + + PE11<10>, + + PF11<10>, + + PG10<10>, + ], + } + use crate::pac::SAI2 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +#[cfg(feature = "gpio-h747")] +pub mod sai3 { + use super::*; + + pin! { + for [ + PD4<6>, + ], + + for [ + PD10<6>, + ], + + for no:NoPin, [ + PD15<6>, + ], + + for no:NoPin, [ + PD14<6>, + ], + + for [ + PD0<6>, + ], + + for [ + PD8<6>, + ], + + for [ + PD1<6>, + ], + + for [ + PD9<6>, + ], + } + use crate::pac::SAI3 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h747"))] +pub mod sai4 { + use super::*; + + pin! { + for [ + PE2<10>, + ], + + for [ + PE5<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PB2<1>, + + #[cfg(feature = "gpio-h747")] + PB2<10>, + + #[cfg(feature = "gpio-h72")] + PC1<1>, + + #[cfg(feature = "gpio-h747")] + PC1<10>, + + #[cfg(feature = "gpio-h72")] + PD6<1>, + + #[cfg(feature = "gpio-h747")] + PD6<10>, + + PE6<9>, + ], + + for [ + PE4<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC5<1>, + + #[cfg(feature = "gpio-h747")] + PC5<10>, + + PF10<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PD12<10>, + + PE4<8>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA12<8>, + + #[cfg(feature = "gpio-h72")] + PC0<8>, + + #[cfg(feature = "gpio-h72")] + PE13<10>, + + PF9<8>, + + #[cfg(feature = "gpio-h72")] + PG9<10>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-h72")] + PE0<10>, + + PE2<8>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-h72")] + PA1<10>, + + #[cfg(feature = "gpio-h72")] + PE6<10>, + + #[cfg(feature = "gpio-h72")] + PE14<10>, + + PF7<8>, + + #[cfg(feature = "gpio-h72")] + PH3<10>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PD13<10>, + + PE5<8>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA2<8>, + + #[cfg(feature = "gpio-h72")] + PE12<10>, + + PF8<8>, + + #[cfg(feature = "gpio-h72")] + PH2<10>, + ], + + for [ + PB2<8>, + + PC1<8>, + + PD6<8>, + + #[cfg(feature = "gpio-h72")] + PD11<10>, + + PE6<8>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA0<10>, + + PE3<8>, + + #[cfg(feature = "gpio-h72")] + PE11<10>, + + PF6<8>, + + #[cfg(feature = "gpio-h72")] + PF11<10>, + + #[cfg(feature = "gpio-h72")] + PG10<10>, + ], + } + use crate::pac::SAI4 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sdmmc1 { + use super::*; + + pin! { + for [ + PB9<7>, + ], + + for [ + PC12<12>, + ], + + for [ + PB8<7>, + ], + + for [ + PD2<12>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PB13<12>, + + PC8<12>, + ], + + for [ + PC6<8>, + ], + + for [ + PC9<12>, + ], + + for [ + PC7<8>, + ], + + for [ + PC10<12>, + ], + + for [ + PC11<12>, + ], + + for [ + PB8<12>, + ], + + for [ + PB9<12>, + ], + + for [ + PC6<12>, + ], + + for [ + PC7<12>, + ], + } +} + +pub mod sdmmc2 { + use super::*; + + #[cfg(feature = "gpio-h72")] + pin! { + for [ + PC4<10>, + ], + } + + pin! { + for [ + PC1<9>, + + PD6<11>, + ], + + for [ + PA0<9>, + + PD7<11>, + ], + + for [ + PB14<9>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PG9<11>, + ], + + for [ + PB15<9>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PG10<11>, + ], + + for [ + PB3<9>, + + PG11<10>, + ], + + for [ + PB4<9>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PG12<10>, + ], + + for [ + PB8<10>, + ], + + for [ + PB9<10>, + ], + + for [ + PC6<10>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PG13<10>, + ], + + for [ + PC7<10>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PG14<10>, + ], + } +} + +#[cfg(feature = "gpio-h7a2")] +pub mod spdifrx { + use super::*; + + pin! { + for [ + PD7<9>, + + PG11<8>, + ], + + for [ + PD8<9>, + + PG12<8>, + ], + + for [ + PC4<9>, + + PG8<8>, + ], + + for [ + PC5<9>, + + PG9<8>, + ], + } + + use crate::pac::SPDIFRX; + impl SPdifIn<0> for SPDIFRX { + type In = In0; + } + impl SPdifIn<1> for SPDIFRX { + type In = In1; + } + impl SPdifIn<2> for SPDIFRX { + type In = In2; + } + impl SPdifIn<3> for SPDIFRX { + type In = In3; + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h747"))] +pub mod spdifrx1 { + use super::*; + + #[cfg(feature = "gpio-h747")] + pin! { + for [ + PD7<9>, + + PG11<8>, + ], + } + + pin! { + for [ + #[cfg(feature = "gpio-h72")] + PD7<9>, + + #[cfg(feature = "gpio-h747")] + PD8<9>, + + #[cfg(feature = "gpio-h72")] + PG11<8>, + + #[cfg(feature = "gpio-h747")] + PG12<8>, + ], + + for [ + #[cfg(feature = "gpio-h747")] + PC4<9>, + + #[cfg(feature = "gpio-h72")] + PD8<9>, + + #[cfg(feature = "gpio-h747")] + PG8<8>, + + #[cfg(feature = "gpio-h72")] + PG12<8>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PC4<9>, + + #[cfg(feature = "gpio-h747")] + PC5<9>, + + #[cfg(feature = "gpio-h72")] + PG8<8>, + + #[cfg(feature = "gpio-h747")] + PG9<8>, + ], + } + + #[cfg(feature = "gpio-h72")] + pin! { + for [ + PC5<9>, + + PG9<8>, + ], + } + + use crate::pac::SPDIFRX; + impl SPdifIn<0> for SPDIFRX { + type In = In0; + } + impl SPdifIn<1> for SPDIFRX { + type In = In1; + } + impl SPdifIn<2> for SPDIFRX { + type In = In2; + } + impl SPdifIn<3> for SPDIFRX { + type In = In3; + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PB4<5>, + + PG9<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PB5<5>, + + PD7<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PG10<5>, + ], + + for no:NoPin, [ + PA5<5>, + + PB3<5>, + + PG11<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC2<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI2<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC1<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC3<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI3<5>, + ], + + for [ + PA11<5>, + + PB4<7>, + + PB9<5>, + + PB12<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI0<5>, + ], + + for no:NoPin, [ + PA9<5>, + + PA12<5>, + + PB10<5>, + + PB13<5>, + + PD3<5>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + ], + + for no:NoPin, [ + PB2<7>, + + PB5<7>, + + PC12<6>, + + PD6<5>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi4 { + use super::*; + + pin! { + for no:NoPin, [ + PE5<5>, + + PE13<5>, + ], + + for no:NoPin, [ + PE6<5>, + + PE14<5>, + ], + + for [ + PE4<5>, + + PE11<5>, + ], + + for no:NoPin, [ + PE2<5>, + + PE12<5>, + ], + } + impl SpiCommon for crate::pac::SPI4 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi5 { + use super::*; + + pin! { + for no:NoPin, [ + PF8<5>, + + PH7<5>, + + PJ11<5>, + ], + + for no:NoPin, [ + PF9<5>, + + PF11<5>, + + PJ10<5>, + ], + + for [ + PF6<5>, + + PH5<5>, + + PK1<5>, + ], + + for no:NoPin, [ + PF7<5>, + + PH6<5>, + + PK0<5>, + ], + } + impl SpiCommon for crate::pac::SPI5 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi6 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<8>, + + PB4<8>, + + PG12<5>, + ], + + for no:NoPin, [ + PA7<8>, + + PB5<8>, + + PG14<5>, + ], + + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PA0<5>, + + PA4<8>, + + PA15<7>, + + PG8<5>, + ], + + for no:NoPin, [ + PA5<8>, + + PB3<8>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC12<5>, + + PG13<5>, + ], + } + impl SpiCommon for crate::pac::SPI6 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod swpmi1 { + use super::*; + + pin! { + for [ + PC8<11>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC10<11>, + ], + + for [ + PC9<11>, + ], + + for [ + PC7<11>, + ], + } +} + +#[cfg(feature = "gpio-h747")] +pub mod sys { + use super::*; + + pin! { + for [ + PB4<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + PE9<1>, + + PK1<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + PE8<1>, + + PK0<1>, + ], + + default:PushPull for [ + PA9<1>, + + PE11<1>, + + PJ11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + PE10<1>, + + PJ10<1>, + ], + + default:PushPull for [ + PA10<1>, + + PE13<1>, + + PJ9<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + PE12<1>, + + PJ8<1>, + ], + + default:PushPull for [ + PA11<1>, + + PE14<1>, + ], + } + + pin! { + for [ + PA6<1>, + + PB12<1>, + + PE15<1>, + + PK2<1>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PA12<12>, + + PE6<1>, + + PG4<1>, + ], + + for [ + PE6<11>, + + PG4<11>, + ], + + for [ + PE6<11>, + + PG4<11>, + ], + + for [ + PA6<12>, + + PB12<13>, + + PE15<13>, + + PK2<11>, + ], + + for [ + PA6<12>, + + PB12<13>, + + PE15<13>, + + PK2<11>, + ], + + for [ + PA12<1>, + + PE7<1>, + + PG5<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + ], + } + + pin! { + for [ + PD2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PH10<2>, + ], + + default:PushPull for [ + PA1<2>, + + PH11<2>, + ], + + default:PushPull for [ + PA2<2>, + + PH12<2>, + ], + + default:PushPull for [ + PA3<2>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI0<2>, + ], + } + + pin! { + for [ + PA4<2>, + + PH8<2>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI5<3>, + + PJ8<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + + PH13<3>, + + PJ9<3>, + ], + + default:PushPull for [ + PC7<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI6<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ6<3>, + + PJ10<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + + PH14<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PJ7<3>, + + PJ11<3>, + ], + + default:PushPull for [ + PC8<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI7<3>, + + PK0<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + + PH15<3>, + + PK1<3>, + ], + + default:PushPull for [ + PC9<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI2<3>, + ], + } + + pin! { + for [ + PA6<3>, + + PG2<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI4<3>, + + PK2<3>, + ], + + for [ + PA8<3>, + + PG3<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<3>, + ], + + for [ + PA8<12>, + + PG3<11>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<11>, + ], + + for [ + PA8<12>, + + PG3<11>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI1<11>, + ], + + for [ + PA6<10>, + + PG2<11>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI4<11>, + + PK2<10>, + ], + + for [ + PA6<10>, + + PG2<11>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI4<11>, + + PK2<10>, + ], + + for [ + PA0<3>, + + PG8<3>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI3<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim12 { + use super::*; + + pin! { + default:PushPull for [ + PB14<2>, + + PH6<2>, + ], + + default:PushPull for [ + PB15<2>, + + PH9<2>, + ], + } + + use crate::pac::TIM12 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim13 { + use super::*; + + pin! { + default:PushPull for [ + PA6<9>, + + PF8<9>, + ], + } + + use crate::pac::TIM13 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim14 { + use super::*; + + pin! { + default:PushPull for [ + PA7<9>, + + PF9<9>, + ], + } + + use crate::pac::TIM14 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<4>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PC12<2>, + + PE5<4>, + ], + + default:PushPull for [ + PA1<4>, + + PE4<4>, + ], + + default:PushPull for [ + PA3<4>, + + PE6<4>, + ], + } + + pin! { + for [ + PA0<4>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PD2<4>, + + PE3<4>, + ], + + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PB8<1>, + + PF6<1>, + ], + + default:PushPull for [ + PB6<1>, + + PF8<1>, + ], + } + + pin! { + for [ + PB4<1>, + + PF10<1>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PB9<1>, + + PF7<1>, + ], + + default:PushPull for [ + PB7<1>, + + PF9<1>, + ], + } + + pin! { + for [ + PB5<1>, + + PG6<1>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +#[cfg(feature = "gpio-h72")] +pub mod tim23 { + use super::*; + + pin! { + default:PushPull for [ + PF0<13>, + + PF6<13>, + + PG12<13>, + ], + + default:PushPull for [ + PF1<13>, + + PF7<13>, + + PG13<13>, + ], + + default:PushPull for [ + PF2<13>, + + PF8<13>, + + PG14<13>, + ], + + default:PushPull for [ + PF3<13>, + + PF9<13>, + ], + } + + pin! { + for [ + PB2<13>, + + PG3<13>, + ], + } + + use crate::pac::TIM23 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-h72")] +pub mod tim24 { + use super::*; + + pin! { + default:PushPull for [ + PF11<14>, + ], + + default:PushPull for [ + PF12<14>, + ], + + default:PushPull for [ + PF13<14>, + ], + + default:PushPull for [ + PF14<14>, + ], + } + + pin! { + for [ + PB3<14>, + + PG2<14>, + ], + } + + use crate::pac::TIM24 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod uart4 { + use super::*; + + pin! { + for [ + PB0<8>, + + PB15<8>, + ], + + for [ + PA15<8>, + + PB14<8>, + ], + + for [ + PA15<8>, + + PB14<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + PA11<6>, + + PB8<8>, + + PC11<8>, + + PD0<8>, + + PH14<8>, + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PI9<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + PA12<6>, + + PB9<8>, + + PC10<8>, + + PD1<8>, + + PH13<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart5 { + use super::*; + + pin! { + for [ + PC9<8>, + ], + + for [ + PC8<8>, + ], + + for [ + PC8<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB5<14>, + + PB12<14>, + + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + PB6<14>, + + PB13<14>, + + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart7 { + use super::*; + + pin! { + for [ + PE10<7>, + + PF9<7>, + ], + + for [ + PE9<7>, + + PF8<7>, + ], + + for [ + PE9<7>, + + PF8<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA8<11>, + + PB3<11>, + + PE7<7>, + + PF6<7>, + ], + + default:PushPull for no:NoPin, [ + PA15<11>, + + PB4<11>, + + PE8<7>, + + PF7<7>, + ], + } + use crate::pac::UART7 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart8 { + use super::*; + + pin! { + for [ + PD14<8>, + ], + + for [ + PD15<8>, + ], + + for [ + PD15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PE0<8>, + + PJ9<8>, + ], + + default:PushPull for no:NoPin, [ + PE1<8>, + + PJ8<8>, + ], + } + use crate::pac::UART8 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] +pub mod uart9 { + use super::*; + + pin! { + for [ + PD0<11>, + + #[cfg(feature = "gpio-h7a2")] + PJ4<11>, + ], + + for [ + PD13<11>, + + #[cfg(feature = "gpio-h7a2")] + PJ3<11>, + ], + + for [ + PD13<11>, + + #[cfg(feature = "gpio-h7a2")] + PJ3<11>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PD14<11>, + + PG0<11>, + ], + + default:PushPull for no:NoPin, [ + PD15<11>, + + PG1<11>, + ], + } + use crate::pac::UART9 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + PB15<4>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + PB14<4>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + ], + + for [ + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart6 { + use super::*; + + pin! { + for [ + PC8<7>, + + PG7<7>, + ], + + for [ + PG13<7>, + + PG15<7>, + ], + + for [ + PG8<7>, + + PG12<7>, + ], + + for [ + PG13<7>, + + PG15<7>, + ], + + for [ + PG8<7>, + + PG12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC7<7>, + + PG9<7>, + ], + + default:PushPull for no:NoPin, [ + PC6<7>, + + PG14<7>, + ], + } + use crate::pac::USART6 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] +pub mod usart10 { + use super::*; + + pin! { + for [ + PE15<11>, + + PG15<11>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PG13<4>, + + #[cfg(feature = "gpio-h7a2")] + PG13<11>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PG14<4>, + + #[cfg(feature = "gpio-h7a2")] + PG14<11>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PG13<4>, + + #[cfg(feature = "gpio-h7a2")] + PG13<11>, + ], + + for [ + #[cfg(feature = "gpio-h72")] + PG14<4>, + + #[cfg(feature = "gpio-h7a2")] + PG14<11>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-h72")] + PE2<4>, + + #[cfg(feature = "gpio-h7a2")] + PE2<11>, + + #[cfg(feature = "gpio-h72")] + PG11<4>, + + #[cfg(feature = "gpio-h7a2")] + PG11<11>, + ], + + default:PushPull for no:NoPin, [ + PE3<11>, + + #[cfg(feature = "gpio-h72")] + PG12<4>, + + #[cfg(feature = "gpio-h7a2")] + PG12<11>, + ], + } + use crate::pac::USART10 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-h747")] +pub mod otg_fs { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA10<10>, + ], + + for [ + PA8<10>, + ], + } +} + +pub mod otg_hs { + use super::*; + + #[cfg(feature = "gpio-h747")] + pin! { + for [ + PB14<12>, + ], + + for [ + PB15<12>, + ], + } + + pin! { + for [ + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PA10<10>, + + #[cfg(feature = "gpio-h747")] + PB12<12>, + ], + + for [ + #[cfg(feature = "gpio-h747")] + PA4<12>, + + #[cfg(any(feature = "gpio-h72", feature = "gpio-h7a2"))] + PA8<10>, + ], + + for [ + PA5<10, Speed::VeryHigh>, + ], + + for [ + PA3<10, Speed::VeryHigh>, + ], + + for [ + PB0<10, Speed::VeryHigh>, + ], + + for [ + PB1<10, Speed::VeryHigh>, + ], + + for [ + PB10<10, Speed::VeryHigh>, + ], + + for [ + PB11<10, Speed::VeryHigh>, + ], + + for [ + PB12<10, Speed::VeryHigh>, + ], + + for [ + PB13<10, Speed::VeryHigh>, + ], + + for [ + PB5<10, Speed::VeryHigh>, + ], + + for [ + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + PC3<10, Speed::VeryHigh>, + + PH4<10, Speed::VeryHigh>, + ], + + for [ + PC0<10, Speed::VeryHigh>, + ], + } + + #[cfg(any(feature = "gpio-h747", feature = "gpio-h7a2"))] + pin! { + for [ + PC2<10, Speed::VeryHigh>, + + PI11<10, Speed::VeryHigh>, + ], + } +} diff --git a/src/gpio/alt/l0.rs b/src/gpio/alt/l0.rs new file mode 100644 index 00000000..97839c75 --- /dev/null +++ b/src/gpio/alt/l0.rs @@ -0,0 +1,1611 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod comp1 { + use super::*; + + pin! { + for [ + PA0<7>, + + PA6<7>, + + #[cfg(feature = "gpio-l021")] + PA9<7>, + + #[cfg(feature = "gpio-l021")] + PA10<7>, + + PA11<7>, + + #[cfg(feature = "gpio-l021")] + PA13<7>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PA2<7>, + + #[cfg(feature = "gpio-l021")] + PA4<7>, + + PA7<7>, + + PA12<7>, + + #[cfg(feature = "gpio-l021")] + PA14<7>, + ], + } +} + +/*#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod crs { + use super::*; + + pin! { + for [ + PA8<2>, + + #[cfg(feature = "gpio-l071")] + PD15<0>, + + PH0<0>, + ], + } +}*/ + +pub mod i2c1 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-l021")] + PA4<3>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA9<1>, + + #[cfg(feature = "gpio-l071")] + PA9<6>, + + PB6<1>, + + PB8<4>, + ], + + for [ + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA10<1>, + + #[cfg(feature = "gpio-l071")] + PA10<6>, + + #[cfg(feature = "gpio-l021")] + PA13<3>, + + PB7<1>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PB9<4>, + ], + + for [ + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA1<3>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA14<3>, + + PB5<3>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<6>, + + PB13<5>, + ], + + for [ + PB11<6>, + + PB14<5>, + ], + + for [ + PB12<5>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(feature = "gpio-l071")] +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA8<7>, + + PC0<7>, + ], + + for [ + PB4<7>, + + PC1<7>, + + PC9<7>, + ], + + for [ + PA9<7>, + + PB2<7>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod i2s2 { + use super::*; + + pin! { + for [ + PB13<0>, + + #[cfg(feature = "gpio-l071")] + PD1<1>, + ], + + for no:NoPin, [ + PB14<0>, + + PC2<2>, + + #[cfg(feature = "gpio-l071")] + PD3<2>, + ], + + for [ + PB15<0>, + + PC3<2>, + + #[cfg(feature = "gpio-l071")] + PD4<1>, + ], + + for [ + PB9<5>, + + PB12<0>, + + #[cfg(feature = "gpio-l071")] + PD0<1>, + ], + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod lcd { + use super::*; + + pin! { + for [ + PA8<1>, + ], + + for [ + PA9<1>, + ], + + for [ + PA10<1>, + ], + + for [ + PB9<1>, + ], + + for [ + PC10<1>, + ], + + for [ + PC11<1>, + ], + + for [ + PC12<1>, + ], + + for [ + PD2<1>, + ], + + for [ + PA1<1>, + ], + + for [ + PA2<1>, + ], + + for [ + PA3<1>, + ], + + for [ + PA6<1>, + ], + + for [ + PA7<1>, + ], + + for [ + PB0<1>, + ], + + for [ + PB1<1>, + ], + + for [ + PB3<1>, + ], + + for [ + PB4<1>, + ], + + for [ + PB5<1>, + ], + + for [ + PB10<1>, + ], + + for [ + PB11<1>, + ], + + for [ + PB12<1>, + ], + + for [ + PB13<1>, + ], + + for [ + PB14<1>, + ], + + for [ + PB15<1>, + ], + + for [ + PB8<1>, + ], + + for [ + PA15<1>, + ], + + for [ + PC0<1>, + ], + + for [ + PC1<1>, + ], + + for [ + PC2<1>, + ], + + for [ + PC3<1>, + ], + + for [ + PC4<1>, + ], + + for [ + PC5<1>, + ], + + for [ + PC6<1>, + ], + + for [ + PC7<1>, + ], + + for [ + PC8<1>, + ], + + for [ + PC9<1>, + ], + + for [ + PC10<1>, + + #[cfg(feature = "gpio-l071")] + PD8<1>, + ], + + for [ + PC11<1>, + + #[cfg(feature = "gpio-l071")] + PD9<1>, + ], + + for [ + PC12<1>, + + #[cfg(feature = "gpio-l071")] + PD10<1>, + ], + + for [ + PD2<1>, + + #[cfg(feature = "gpio-l071")] + PD11<1>, + ], + + for [ + #[cfg(feature = "gpio-l051")] + PC10<1>, + + #[cfg(feature = "gpio-l071")] + PE10<1>, + ], + + for [ + #[cfg(feature = "gpio-l051")] + PC11<1>, + + #[cfg(feature = "gpio-l071")] + PE13<1>, + ], + + for [ + #[cfg(feature = "gpio-l051")] + PC12<1>, + + #[cfg(feature = "gpio-l071")] + PE14<1>, + ], + + for [ + #[cfg(feature = "gpio-l051")] + PD2<1>, + + #[cfg(feature = "gpio-l071")] + PE15<1>, + ], + } + + #[cfg(feature = "gpio-l071")] + pin! { + for [ + PD12<1>, + ], + + for [ + PD13<1>, + ], + + for [ + PD14<1>, + ], + + for [ + PD15<1>, + ], + + for [ + PE0<1>, + ], + + for [ + PE1<1>, + ], + + for [ + PE2<1>, + ], + + for [ + PE3<1>, + ], + + for [ + PD3<1>, + ], + + for [ + PE7<1>, + ], + + for [ + PE8<1>, + ], + + for [ + PE9<1>, + ], + + for [ + PC10<1>, + ], + + for [ + PC11<1>, + ], + + for [ + PC12<1>, + ], + + for [ + PD2<1>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-l021")] + PA4<2>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA6<1>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA13<1>, + + PB6<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC3<0>, + ], + + for [ + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA0<1>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA4<1>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA8<2>, + + #[cfg(feature = "gpio-l021")] + PB1<2>, + + PB5<2>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PC0<0>, + ], + + for [ + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA1<1>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA5<1>, + + PB7<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC2<0>, + ], + + default:PushPull for [ + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA7<1>, + + #[cfg(feature = "gpio-l021")] + PA9<2>, + + #[cfg(feature = "gpio-l021")] + PA11<1>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA14<1>, + + PB2<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC1<0>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<4>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB13<4>, + + #[cfg(feature = "gpio-l031")] + PB13<6>, + + #[cfg(feature = "gpio-l071")] + PD11<0>, + ], + + for [ + PB1<4>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB12<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB14<4>, + + #[cfg(feature = "gpio-l031")] + PB14<6>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PD2<0>, + + #[cfg(feature = "gpio-l071")] + PD12<0>, + ], + + for [ + PB1<4>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB12<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB14<4>, + + #[cfg(feature = "gpio-l031")] + PB14<6>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PD2<0>, + + #[cfg(feature = "gpio-l071")] + PD12<0>, + ], + + for [ + #[cfg(feature = "gpio-l021")] + PA0<6>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031", feature = "gpio-l071"))] + PA3<6>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031", feature = "gpio-l071"))] + PA13<6>, + + #[cfg(feature = "gpio-l021")] + PB7<6>, + + #[cfg(feature = "gpio-l071")] + PB10<7>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB11<4>, + + #[cfg(feature = "gpio-l031")] + PB11<6>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l071"))] + PC0<6>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC5<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC11<0>, + + #[cfg(feature = "gpio-l071")] + PD9<0>, + ], + } + + pin! { + default:PushPull for [ + #[cfg(feature = "gpio-l021")] + PA1<6>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031", feature = "gpio-l071"))] + PA2<6>, + + #[cfg(feature = "gpio-l021")] + PA4<6>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031", feature = "gpio-l071"))] + PA14<6>, + + #[cfg(feature = "gpio-l021")] + PB6<6>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB10<4>, + + #[cfg(feature = "gpio-l031")] + PB10<6>, + + #[cfg(feature = "gpio-l071")] + PB11<7>, + + #[cfg(feature = "gpio-l071")] + PC1<6>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC4<2>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC10<0>, + + #[cfg(feature = "gpio-l071")] + PD8<0>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + + PA9<0>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l071"))] + PB13<2>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PB14<2>, + ], + + for [ + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PB14<2>, + ], + + for [ + #[cfg(feature = "gpio-l021")] + PA10<2>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PB15<2>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<0>, + + PA11<0>, + + #[cfg(feature = "gpio-l021")] + PA14<5>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB0<1>, + + PB4<0>, + + #[cfg(feature = "gpio-l031")] + PB14<0>, + + #[cfg(feature = "gpio-l071")] + PE14<2>, + ], + + for no:NoPin, [ + PA7<0>, + + PA12<0>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB1<1>, + + PB5<0>, + + #[cfg(feature = "gpio-l031")] + PB15<0>, + + #[cfg(feature = "gpio-l071")] + PE15<2>, + ], + + for [ + PA4<0>, + + PA15<0>, + + #[cfg(feature = "gpio-l021")] + PB8<5>, + + #[cfg(feature = "gpio-l031")] + PB12<0>, + + #[cfg(feature = "gpio-l071")] + PE12<2>, + ], + + for no:NoPin, [ + PA5<0>, + + #[cfg(feature = "gpio-l021")] + PA13<5>, + + PB3<0>, + + #[cfg(feature = "gpio-l031")] + PB13<0>, + + #[cfg(feature = "gpio-l071")] + PE13<2>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<0>, + + PC2<2>, + + #[cfg(feature = "gpio-l071")] + PD3<2>, + ], + + for no:NoPin, [ + PB15<0>, + + PC3<2>, + + #[cfg(feature = "gpio-l071")] + PD4<1>, + ], + + for [ + PB9<5>, + + PB12<0>, + + #[cfg(feature = "gpio-l071")] + PD0<1>, + ], + + for no:NoPin, [ + PB10<5>, + + PB13<0>, + + #[cfg(feature = "gpio-l071")] + PD1<1>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA13<0>, + ], + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PA5<5>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA8<5>, + + PA15<5>, + + #[cfg(feature = "gpio-l071")] + PE9<0>, + ], + + default:PushPull for [ + PA1<2>, + + #[cfg(feature = "gpio-l021")] + PB0<2>, + + PB3<2>, + + #[cfg(feature = "gpio-l071")] + PE10<0>, + ], + + default:PushPull for [ + PA2<2>, + + #[cfg(feature = "gpio-l021")] + PA10<5>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB0<5>, + + #[cfg(feature = "gpio-l021")] + PB6<5>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PB10<2>, + + #[cfg(feature = "gpio-l071")] + PE11<0>, + ], + + default:PushPull for [ + PA3<2>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB1<5>, + + #[cfg(feature = "gpio-l021")] + PB7<5>, + + #[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] + PB11<2>, + + #[cfg(feature = "gpio-l071")] + PE12<0>, + ], + } + + pin! { + for [ + PA0<5>, + + #[cfg(feature = "gpio-l021")] + PA4<5>, + + PA5<2>, + + PA15<2>, + + #[cfg(feature = "gpio-l071")] + PE9<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(feature = "gpio-l071")] +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE3<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<4>, + + PC7<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + + PE5<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + + PE6<2>, + ], + } + + pin! { + for [ + PD2<2>, + + PE2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim21 { + use super::*; + + pin! { + default:PushPull for [ + PA2<0>, + + #[cfg(feature = "gpio-l021")] + PA10<0>, + + #[cfg(feature = "gpio-l021")] + PB5<5>, + + #[cfg(feature = "gpio-l031")] + PB6<5>, + + #[cfg(feature = "gpio-l031")] + PB13<5>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB13<6>, + + #[cfg(feature = "gpio-l071")] + PD0<0>, + + #[cfg(feature = "gpio-l071")] + PE5<0>, + ], + + default:PushPull for [ + PA3<0>, + + #[cfg(feature = "gpio-l021")] + PA9<5>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA11<5>, + + #[cfg(feature = "gpio-l031")] + PB14<5>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PB14<6>, + + #[cfg(feature = "gpio-l071")] + PD7<1>, + + #[cfg(feature = "gpio-l071")] + PE6<0>, + ], + } + + pin! { + for [ + PA1<5>, + + #[cfg(feature = "gpio-l021")] + PA7<5>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC9<0>, + ], + } + + use crate::pac::TIM21 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-l031", feature = "gpio-l051", feature = "gpio-l071"))] +pub mod tim22 { + use super::*; + + pin! { + default:PushPull for [ + PA6<5>, + + #[cfg(feature = "gpio-l031")] + PA9<5>, + + PB4<4>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC6<0>, + + #[cfg(feature = "gpio-l071")] + PE3<0>, + ], + + default:PushPull for [ + PA7<5>, + + #[cfg(feature = "gpio-l031")] + PA10<5>, + + PB5<4>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC7<0>, + + #[cfg(feature = "gpio-l071")] + PE4<0>, + ], + } + + pin! { + for [ + PA4<5>, + + #[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] + PC8<0>, + ], + } + + use crate::pac::TIM22 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod tsc { + use super::*; + + pin! { + for [ + PB8<3>, + + PB10<3>, + ], + } + + pin! { + default:PushPull for [ + PA0<3>, + ], + + default:PushPull for [ + PA1<3>, + ], + + default:PushPull for [ + PA2<3>, + ], + + default:PushPull for [ + PA3<3>, + ], + + default:PushPull for [ + PA4<3>, + ], + + default:PushPull for [ + PA5<3>, + ], + + default:PushPull for [ + PA6<3>, + ], + + default:PushPull for [ + PA7<3>, + ], + + default:PushPull for [ + PC5<3>, + ], + + default:PushPull for [ + PB0<3>, + ], + + default:PushPull for [ + PB1<3>, + ], + + default:PushPull for [ + PB2<3>, + ], + + default:PushPull for [ + PA9<3>, + ], + + default:PushPull for [ + PA10<3>, + ], + + default:PushPull for [ + PA11<3>, + ], + + default:PushPull for [ + PA12<3>, + ], + + default:PushPull for [ + PB3<3>, + ], + + default:PushPull for [ + PB4<3>, + ], + + default:PushPull for [ + PB6<3>, + ], + + default:PushPull for [ + PB7<3>, + ], + + default:PushPull for [ + PB11<3>, + ], + + default:PushPull for [ + PB12<3>, + ], + + default:PushPull for [ + PB13<3>, + ], + + default:PushPull for [ + PB14<3>, + ], + + default:PushPull for [ + PC0<3>, + ], + + default:PushPull for [ + PC1<3>, + ], + + default:PushPull for [ + PC2<3>, + ], + + default:PushPull for [ + PC3<3>, + ], + + default:PushPull for [ + PC6<3>, + ], + + default:PushPull for [ + PC7<3>, + ], + + default:PushPull for [ + PC8<3>, + ], + + default:PushPull for [ + PC9<3>, + ], + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<4>, + + #[cfg(feature = "gpio-l071")] + PB5<5>, + ], + + for [ + PA11<4>, + + #[cfg(feature = "gpio-l071")] + PB4<5>, + ], + + for [ + PA12<4>, + + #[cfg(feature = "gpio-l071")] + PB3<5>, + ], + + for [ + PA12<4>, + + #[cfg(feature = "gpio-l071")] + PB3<5>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<4>, + + PB7<0>, + ], + + default:PushPull for no:NoPin, [ + PA9<4>, + + PB6<0>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA8<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB1<0>, + + #[cfg(feature = "gpio-l071")] + PD7<0>, + ], + + for [ + PA0<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA7<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA11<4>, + + #[cfg(feature = "gpio-l071")] + PD3<0>, + ], + + for [ + PA1<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA12<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB0<4>, + + #[cfg(feature = "gpio-l071")] + PD4<0>, + ], + + for [ + PA1<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA12<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB0<4>, + + #[cfg(feature = "gpio-l071")] + PD4<0>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + #[cfg(feature = "gpio-l021")] + PA0<0>, + + PA3<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA10<4>, + + PA15<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB7<0>, + + #[cfg(feature = "gpio-l071")] + PD6<0>, + ], + + default:PushPull for no:NoPin, [ + PA2<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PA9<4>, + + PA14<4>, + + #[cfg(any(feature = "gpio-l021", feature = "gpio-l031"))] + PB6<0>, + + #[cfg(feature = "gpio-l021")] + PB8<0>, + + #[cfg(feature = "gpio-l071")] + PD5<0>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-l071")] +pub mod usart4 { + use super::*; + + pin! { + for [ + PC12<6>, + ], + + for [ + PB7<6>, + ], + + for [ + PA15<6>, + ], + + for [ + PA15<6>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<6>, + + PC11<6>, + + PE9<6>, + ], + + default:PushPull for no:NoPin, [ + PA0<6>, + + PC10<6>, + + PE8<6>, + ], + } + use crate::pac::USART4 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-l071")] +pub mod usart5 { + use super::*; + + pin! { + for [ + PB5<6>, + + PE7<6>, + ], + + for [ + PB5<6>, + + PE7<6>, + ], + + for [ + PB5<6>, + + PE7<6>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB4<6>, + + PD2<6>, + + PE11<6>, + ], + + default:PushPull for no:NoPin, [ + PB3<6>, + + PC12<2>, + + PE10<6>, + ], + } + use crate::pac::USART5 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } +} + +#[cfg(any(feature = "gpio-l051", feature = "gpio-l071"))] +pub mod usb { + use super::*; + + pin! { + for [ + PA13<2>, + + PC9<2>, + ], + } +} diff --git a/src/gpio/alt/l1.rs b/src/gpio/alt/l1.rs new file mode 100644 index 00000000..91f75ee7 --- /dev/null +++ b/src/gpio/alt/l1.rs @@ -0,0 +1,1931 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +#[cfg(feature = "gpio-l162xe")] +pub mod comp1 { + use super::*; + + analog! { + for [ + PA0<14>, + + PA1<14>, + + PA2<14>, + + PA3<14>, + + PA4<14>, + + PA5<14>, + + PA6<14>, + + PA7<14>, + + PB0<14>, + + PB1<14>, + + PB12<14>, + + PB13<14>, + + PB14<14>, + + PB15<14>, + + PC0<14>, + + PC1<14>, + + PC2<14>, + + PC3<14>, + + PC4<14>, + + PC5<14>, + + PE7<14>, + + PE8<14>, + + PE9<14>, + + PE10<14>, + + PF6<14>, + + PF7<14>, + + PF8<14>, + + PF9<14>, + + PF10<14>, + ], + } +} + +#[cfg(feature = "gpio-l162xe")] +pub mod comp2 { + use super::*; + + analog! { + for [ + PB3<14>, + ], + + for [ + PB4<14>, + + PB5<14>, + + PB6<14>, + + PB7<14>, + ], + } +} + +#[cfg(feature = "gpio-l162xd")] +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PH2<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + ], + + for [ + PB7<4>, + + PB9<4>, + ], + + for [ + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + ], + + for [ + PB11<4>, + ], + + for [ + PB12<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" +))] +pub mod i2s2 { + use super::*; + + pin! { + for [ + PB13<5>, + + PD1<5>, + ], + + for no:NoPin, [ + PC6<5>, + ], + + for [ + PB15<5>, + + PD4<5>, + ], + + for [ + PB12<5>, + + PD0<5>, + ], + } +} + +#[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" +))] +pub mod i2s3 { + use super::*; + + pin! { + for [ + PB3<6>, + + PC10<6>, + ], + + for no:NoPin, [ + PC7<6>, + ], + + for [ + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + } +} + +pub mod lcd { + use super::*; + + pin! { + for [ + PA8<11>, + ], + + for [ + PA9<11>, + ], + + for [ + PA10<11>, + ], + + for [ + PB9<11>, + ], + + for [ + PC10<11>, + ], + + for [ + PC11<11>, + ], + + for [ + PC12<11>, + ], + + for [ + PD2<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA2<11>, + ], + + for [ + PB10<11>, + ], + + for [ + PB11<11>, + ], + + for [ + PB12<11>, + ], + + for [ + PB13<11>, + ], + + for [ + PB14<11>, + ], + + for [ + PB15<11>, + ], + + for [ + PB8<11>, + ], + + for [ + PA15<11>, + ], + + for [ + PC0<11>, + ], + + for [ + PC1<11>, + ], + + for [ + PA3<11>, + ], + + for [ + PC2<11>, + ], + + for [ + PC3<11>, + ], + + for [ + PC4<11>, + ], + + for [ + PC5<11>, + ], + + for [ + PC6<11>, + ], + + for [ + PC7<11>, + ], + + for [ + PC8<11>, + ], + + for [ + PC9<11>, + ], + + for [ + PC10<11>, + + PD8<11>, + ], + + for [ + PC11<11>, + + PD9<11>, + ], + + for [ + PA6<11>, + ], + + for [ + PC12<11>, + + PD10<11>, + ], + + for [ + PD2<11>, + + PD11<11>, + ], + + for [ + PD12<11>, + ], + + for [ + PD13<11>, + ], + + for [ + PD14<11>, + ], + + for [ + PD15<11>, + ], + + for [ + PE0<11>, + ], + + for [ + PE1<11>, + ], + + for [ + PE2<11>, + ], + + for [ + PE3<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PC10<11>, + ], + + for [ + PC11<11>, + ], + + for [ + PC12<11>, + ], + + for [ + PD2<11>, + ], + + for [ + PB0<11>, + ], + + for [ + PB1<11>, + ], + + for [ + PB3<11>, + ], + + for [ + PB4<11>, + ], + + for [ + PB5<11>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + + for [ + PC14<0>, + ], + + for [ + PC15<0>, + ], + + for [ + PH0<0>, + ], + + for [ + PH1<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PB15<0>, + ], + + for [ + #[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" + ))] + PA0<0>, + ], + + for [ + #[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" + ))] + PE6<0>, + ], + } +} + +#[cfg(feature = "gpio-l162xd")] +pub mod sdio { + use super::*; + + pin! { + for [ + PC12<12, Speed::VeryHigh>, + ], + + for [ + PD2<12, Speed::VeryHigh>, + ], + + for [ + PC8<12, Speed::VeryHigh>, + ], + + for [ + PC9<12, Speed::VeryHigh>, + ], + + for [ + PC10<12, Speed::VeryHigh>, + ], + + for [ + PC11<12, Speed::VeryHigh>, + ], + + for [ + PB8<12, Speed::VeryHigh>, + ], + + for [ + PB9<12, Speed::VeryHigh>, + ], + + for [ + PC6<12, Speed::VeryHigh>, + ], + + for [ + PC7<12, Speed::VeryHigh>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PA11<5>, + + PB4<5>, + + PE14<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PA12<5>, + + PB5<5>, + + PE15<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PE12<5>, + ], + + for no:NoPin, [ + PA5<5>, + + PB3<5>, + + PE13<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PD3<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PD4<5>, + ], + + for [ + PB12<5>, + + PD0<5>, + ], + + for no:NoPin, [ + PB13<5>, + + PD1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" +))] +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + #[cfg(feature = "gpio-l162xe")] + PB7<14>, + ], + + for [ + PE2<0>, + ], + + for [ + PE3<0>, + ], + + for [ + PE4<0>, + ], + + for [ + PE5<0>, + ], + + for [ + PE6<0>, + ], + + for [ + #[cfg(feature = "gpio-l162xe")] + PB0<14>, + + #[cfg(feature = "gpio-l162xe")] + PB1<14>, + ], + + for [ + PA0<0>, + ], + + for [ + PE6<0>, + ], + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + + PE9<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + + PE10<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + + PE11<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + + PE12<1>, + ], + } + + pin! { + for [ + #[cfg(feature = "gpio-l152x8")] + PA0<1>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE3<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + ], + } + + pin! { + for [ + PD2<2>, + + PE2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" +))] +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF6<2>, + ], + + default:PushPull for [ + PA1<2>, + + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF7<2>, + ], + + default:PushPull for [ + PA2<2>, + + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF8<2>, + ], + + default:PushPull for [ + PA3<2>, + + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF9<2>, + ], + } + + pin! { + for [ + #[cfg(any(feature = "gpio-l152xc", feature = "gpio-l15xxa"))] + PE9<2>, + + #[cfg(feature = "gpio-l162xd")] + PF6<2>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim9 { + use super::*; + + pin! { + default:PushPull for [ + PA2<3>, + + PB13<3>, + + PD0<3>, + + PE5<3>, + ], + + default:PushPull for [ + PA3<3>, + + PB14<3>, + + PD7<3>, + + PE6<3>, + ], + } + + use crate::pac::TIM9 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } +} + +pub mod tim10 { + use super::*; + + pin! { + default:PushPull for [ + PA6<3>, + + PB8<3>, + + PB12<3>, + + PE0<3>, + ], + } + + use crate::pac::TIM10 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +pub mod tim11 { + use super::*; + + pin! { + default:PushPull for [ + PA7<3>, + + PB9<3>, + + PB15<3>, + + PE1<3>, + ], + } + + use crate::pac::TIM11 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } +} + +// TODO check +pub mod timx { + use super::*; + + pin! { + for [ + PA0<14>, + + PA4<14>, + + PA8<14>, + + PA12<14>, + + PC0<14>, + + PC4<14>, + + PC8<14>, + + PC12<14>, + + PD0<14>, + + PD4<14>, + + PD8<14>, + + PD12<14>, + + PE0<14>, + + PE4<14>, + + PE8<14>, + + PE12<14>, + ], + + for [ + PA1<14>, + + PA5<14>, + + PA9<14>, + + PA13<14>, + + PC1<14>, + + PC5<14>, + + PC9<14>, + + PD1<14>, + + PD5<14>, + + PD9<14>, + + PD13<14>, + + PE1<14>, + + PE5<14>, + + PE9<14>, + + PE13<14>, + ], + + for [ + PA2<14>, + + PA6<14>, + + PA10<14>, + + PA14<14>, + + PC2<14>, + + PC6<14>, + + PC10<14>, + + PC14<14>, + + PD2<14>, + + PD6<14>, + + PD10<14>, + + PD14<14>, + + PE2<14>, + + PE6<14>, + + PE10<14>, + + PE14<14>, + ], + + for [ + PA3<14>, + + PA7<14>, + + PA11<14>, + + PA15<14>, + + PC3<14>, + + PC7<14>, + + PC11<14>, + + PC15<14>, + + PD3<14>, + + PD7<14>, + + PD11<14>, + + PD15<14>, + + PE3<14>, + + PE7<14>, + + PE11<14>, + + PE15<14>, + ], + } + + use crate::pac::TIMX as TIM; +} + +pub mod ts { + use super::*; + + analog! { + for [ + PC6<14>, + ], + + for [ + PC7<14>, + ], + + for [ + PC8<14>, + ], + + for [ + PC9<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF6<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF7<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF8<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF9<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF10<14>, + ], + + for [ + PA0<14>, + ], + + for [ + PA1<14>, + ], + + for [ + PA2<14>, + ], + + for [ + PA3<14>, + ], + + for [ + PA6<14>, + ], + + for [ + PA7<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF15<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PG0<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PG1<14>, + ], + + for [ + PB0<14>, + ], + + for [ + PB1<14>, + ], + + for [ + #[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" + ))] + PB2<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF11<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF12<14>, + ], + + for [ + PA8<14>, + ], + + for [ + PA9<14>, + ], + + for [ + PA10<14>, + ], + + for [ + PA13<14>, + ], + + for [ + PA14<14>, + ], + + for [ + PA15<14>, + ], + + for [ + PB4<14>, + ], + + for [ + PB5<14>, + ], + + for [ + #[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" + ))] + PB6<14>, + ], + + for [ + #[cfg(any( + feature = "gpio-l152xc", + feature = "gpio-l15xxa", + feature = "gpio-l162xd", + feature = "gpio-l162xe" + ))] + PB7<14>, + ], + + for [ + PB12<14>, + ], + + for [ + PB13<14>, + ], + + for [ + PB14<14>, + ], + + for [ + PB15<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PG2<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PG3<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PG4<14>, + ], + + for [ + PC0<14>, + ], + + for [ + PC1<14>, + ], + + for [ + PC2<14>, + ], + + for [ + PC3<14>, + ], + + for [ + PC4<14>, + ], + + for [ + PC5<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF13<14>, + ], + + for [ + #[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] + PF14<14>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + ], + + for [ + PA11<7>, + ], + + for [ + PA12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PB13<7>, + + PD11<7>, + ], + + for [ + PB14<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] +pub mod uart4 { + use super::*; + + pin! { + default:PushPull for no:NoPin, [ + PC11<8>, + ], + + default:PushPull for no:NoPin, [ + PC10<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(any(feature = "gpio-l162xd", feature = "gpio-l162xe"))] +pub mod uart5 { + use super::*; + + pin! { + default:PushPull for no:NoPin, [ + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod usb { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + } +} + +#[cfg(feature = "gpio-l162xe")] +pub mod v_ref { + use super::*; + + pin! { + for [ + PB0<0>, + + PB1<0>, + ], + } + + analog! { + for [ + PB7<0>, + ], + } +} diff --git a/src/gpio/alt/l4.rs b/src/gpio/alt/l4.rs new file mode 100644 index 00000000..ecf8aba9 --- /dev/null +++ b/src/gpio/alt/l4.rs @@ -0,0 +1,3579 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +#[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" +))] +pub mod can1 { + use super::*; + + pin! { + for no:NoPin, [ + PA11<9>, + + #[cfg(feature = "gpio-l45x")] + PB5<3>, + + PB8<9>, + + #[cfg(feature = "gpio-l45x")] + PB12<10>, + + PD0<9>, + + #[cfg(feature = "gpio-l49x")] + PI9<9>, + ], + + for no:NoPin, [ + PA12<9>, + + #[cfg(feature = "gpio-l45x")] + PB6<8>, + + PB9<9>, + + #[cfg(feature = "gpio-l45x")] + PB13<10>, + + PD1<9>, + + #[cfg(feature = "gpio-l49x")] + PH13<9>, + ], + } + impl CanCommon for crate::pac::CAN1 { + type Rx = Rx; + type Tx = Tx; + } +} + +#[cfg(feature = "gpio-l49x")] +pub mod can2 { + use super::*; + + pin! { + for no:NoPin, [ + PB5<3>, + + PB12<10>, + ], + + for no:NoPin, [ + PB6<8>, + + PB13<10>, + ], + } + impl CanCommon for crate::pac::CAN2 { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod comp1 { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] + PA0<12>, + + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] + PA6<6>, + + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] + PA11<6>, + + PB0<12>, + + PB10<12>, + ], + } +} + +#[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" +))] +pub mod comp2 { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x"))] + PA2<12>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x"))] + PA7<12>, + + PB5<12>, + + PB11<12>, + ], + } +} + +/*#[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" +))] +pub mod crs { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] + PA10<10>, + + #[cfg(feature = "gpio-l49x")] + PB3<10>, + ], + } +}*/ + +#[cfg(feature = "gpio-l49x")] +pub mod dcmi { + use super::*; + + pin! { + for [ + PA9<5>, + + PC6<10>, + + PH9<10>, + ], + + for [ + PA10<5>, + + PC7<10>, + + PH10<10>, + ], + + for [ + PB5<10>, + + PD6<4>, + + PI3<10>, + ], + + for [ + PD2<10>, + + PF10<10>, + + PH15<10>, + ], + + for [ + PB4<10>, + + PF11<10>, + + PI8<10>, + ], + + for [ + PG15<10>, + + PI0<10>, + ], + + for [ + PC8<10>, + + PE0<10>, + + PH11<10>, + ], + + for [ + PC9<4>, + + PE1<10>, + + PH12<10>, + ], + + for [ + PC11<10>, + + PE4<10>, + + PH14<10>, + ], + + for [ + PB6<10>, + + PD3<4>, + + PI4<10>, + ], + + for [ + PB8<10>, + + PE5<10>, + + PI6<10>, + ], + + for [ + PB9<10>, + + PE6<10>, + + PI7<10>, + ], + + for [ + PC10<10>, + + PH6<10>, + + PI1<10>, + ], + + for [ + PC12<10>, + + PH7<10>, + + PI2<10>, + ], + + for [ + PA4<10>, + + PD8<10>, + + PH8<10>, + ], + + for [ + PA6<4>, + + PD9<10>, + + PH5<10>, + ], + + for [ + PB7<10>, + + PI5<10>, + ], + } +} + +#[cfg(any(feature = "gpio-l45x", feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod dfsdm1 { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-l45x")] + PB0<6>, + + PB2<6>, + + PD4<6>, + ], + + for [ + #[cfg(feature = "gpio-l45x")] + PA8<6>, + + PB13<6>, + + PD7<6>, + ], + + for [ + PB15<6>, + + PE8<6>, + ], + + for [ + PC6<6>, + + PE5<6>, + ], + + for [ + #[cfg(feature = "gpio-l45x")] + PA5<6>, + + PC2<6>, + + PE9<6>, + ], + + for [ + #[cfg(feature = "gpio-l45x")] + PA7<6>, + + PB1<6>, + + PD3<6>, + ], + + for [ + #[cfg(feature = "gpio-l45x")] + PA9<6>, + + PB12<6>, + + PD6<6>, + ], + + for [ + PB14<6>, + + PE7<6>, + ], + + for [ + PC7<6>, + + PE4<6>, + ], + } + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + pin! { + for [ + PC1<6>, + + PE11<6>, + ], + + for [ + PB7<6>, + + PE13<6>, + ], + + for [ + PB9<6>, + + PF14<6>, + ], + + for [ + PB11<6>, + + PD1<6>, + ], + + for [ + PC0<6>, + + PE10<6>, + ], + + for [ + PB6<6>, + + PE12<6>, + ], + + for [ + PB8<6>, + + PF13<6>, + ], + + for [ + PB10<6>, + + PD0<6>, + ], + } + + use crate::pac::DFSDM; + impl DfsdmBasic for DFSDM { + type Ckin0 = Ckin0; + type Ckin1 = Ckin1; + type Ckout = Ckout; + type Datin0 = Datin0; + type Datin1 = Datin1; + } + impl DfsdmGeneral for DFSDM { + type Ckin2 = Ckin2; + type Ckin3 = Ckin3; + type Datin2 = Datin2; + type Datin3 = Datin3; + } + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + impl DfsdmAdvanced for DFSDM { + type Ckin4 = Ckin4; + type Ckin5 = Ckin5; + type Ckin6 = Ckin6; + type Ckin7 = Ckin7; + type Datin4 = Datin4; + type Datin5 = Datin5; + type Datin6 = Datin6; + type Datin7 = Datin7; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PG7<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-l47x")] + PG7<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PG9<12, Speed::VeryHigh>, + ], + + for [ + #[cfg(feature = "gpio-l47x")] + PG9<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] + PA9<4>, + + PB6<4>, + + PB8<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG14<4>, + ], + + for [ + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] + PA10<4>, + + PB7<4>, + + PB9<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG13<4>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA1<4>, + + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA14<4>, + + PB5<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG15<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PB13<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF1<4>, + + #[cfg(feature = "gpio-l49x")] + PH4<4>, + ], + + for [ + PB11<4>, + + PB14<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF0<4>, + + #[cfg(feature = "gpio-l49x")] + PH5<4>, + ], + + for [ + PB12<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF2<4>, + + #[cfg(feature = "gpio-l49x")] + PH6<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA7<4>, + + PC0<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG7<4>, + + #[cfg(feature = "gpio-l49x")] + PH7<4>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PB4<4>, + + PC1<4>, + + #[cfg(feature = "gpio-l49x")] + PC9<6>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG8<4>, + + #[cfg(feature = "gpio-l49x")] + PH8<4>, + ], + + for [ + PB2<4>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG6<4>, + + #[cfg(feature = "gpio-l49x")] + PH9<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-l45x", feature = "gpio-l49x"))] +pub mod i2c4 { + use super::*; + + pin! { + for [ + PB6<5>, + + PB10<3>, + + PC0<2>, + + PD12<4>, + + #[cfg(feature = "gpio-l49x")] + PF14<4>, + ], + + for [ + PB7<5>, + + PB11<3>, + + PC1<2>, + + PD13<4>, + + #[cfg(feature = "gpio-l49x")] + PF15<4>, + ], + + for [ + PA14<5>, + + PD11<4>, + + #[cfg(feature = "gpio-l49x")] + PF13<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + PB9<1>, + ], + } +} + +#[cfg(any(feature = "gpio-l43x", feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod lcd { + use super::*; + + pin! { + for [ + PA8<11>, + ], + + for [ + PA9<11>, + ], + + for [ + PA10<11>, + ], + + for [ + PB9<11>, + ], + + for [ + PC10<11>, + ], + + for [ + PC11<11>, + ], + + for [ + PC12<11>, + ], + + for [ + PD2<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA2<11>, + ], + + for [ + PB10<11>, + ], + + for [ + PB11<11>, + ], + + for [ + PB12<11>, + ], + + for [ + PB13<11>, + ], + + for [ + PB14<11>, + ], + + for [ + PB15<11>, + ], + + for [ + PB8<11>, + ], + + for [ + PA15<11>, + ], + + for [ + PC0<11>, + ], + + for [ + PC1<11>, + ], + + for [ + PA3<11>, + ], + + for [ + PC2<11>, + ], + + for [ + PB7<11>, + ], + + for [ + PC4<11>, + ], + + for [ + PC5<11>, + ], + + for [ + PC6<11>, + ], + + for [ + PC7<11>, + ], + + for [ + PC8<11>, + ], + + for [ + PC9<11>, + ], + + for [ + PC10<11>, + + PD8<11>, + ], + + for [ + PC11<11>, + + PD9<11>, + ], + + for [ + PA6<11>, + ], + + for [ + PC12<11>, + + PD10<11>, + ], + + for [ + PD2<11>, + + PD11<11>, + ], + + for [ + PD12<11>, + ], + + for [ + PD13<11>, + ], + + for [ + PD14<11>, + ], + + for [ + PD15<11>, + ], + + for [ + PE0<11>, + ], + + for [ + PE1<11>, + ], + + for [ + PE2<11>, + ], + + for [ + PE3<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PC10<11>, + ], + + for [ + PC11<11>, + ], + + for [ + PC12<11>, + ], + + for [ + PD2<11>, + ], + + for [ + PB0<11>, + ], + + for [ + PB1<11>, + ], + + for [ + PB3<11>, + ], + + for [ + PB4<11>, + ], + + for [ + PB5<11>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l49x"))] + PB2<11>, + + PC3<11>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<1>, + + PC3<1>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG12<1>, + ], + + for [ + PB5<1>, + + PC0<1>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG10<1>, + ], + + for [ + PB7<1>, + + PC2<1>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG11<1>, + ], + } + + pin! { + default:PushPull for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA14<1>, + + PB2<1>, + + PC1<1>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG15<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA5<14>, + + PC3<14>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD11<14>, + ], + + for [ + PB1<14>, + + PC0<14>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD12<14>, + ], + } + + pin! { + default:PushPull for [ + PA4<14>, + + PA8<14>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD13<14>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA6<8>, + + PB13<8>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG5<8>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PB1<8>, + + PB12<8>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG6<8>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PB1<8>, + + PB12<8>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG6<8>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA3<8>, + + PB10<8>, + + PC0<8>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG8<8>, + ], + } + + pin! { + default:PushPull for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA2<8>, + + PB11<8>, + + PC1<8>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG7<8>, + ], + } +} + +pub mod quadspi { + use super::*; + + pin! { + for [ + PB1<10>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE12<10>, + + #[cfg(feature = "gpio-l49x")] + PF8<10>, + ], + + for [ + PB0<10>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE13<10>, + + #[cfg(feature = "gpio-l49x")] + PF9<10>, + ], + + for [ + PA7<10>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE14<10>, + + #[cfg(feature = "gpio-l49x")] + PF7<10>, + ], + + for [ + PA6<10>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE15<10>, + + #[cfg(feature = "gpio-l49x")] + PF6<10>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA2<10>, + + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PB11<10>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PE11<10>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PC1<10>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PD4<10>, + + #[cfg(feature = "gpio-l49x")] + PH2<3>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PC2<10>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PD5<10>, + + #[cfg(feature = "gpio-l49x")] + PD6<5>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PC3<10>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PD6<10>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PC4<10>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PD7<10>, + ], + + for [ + #[cfg(feature = "gpio-l49x")] + PC11<5>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PD3<10>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA3<10>, + + PB10<10>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE10<10>, + + #[cfg(feature = "gpio-l49x")] + PF10<3>, + ], + + for [ + #[cfg(feature = "gpio-l47x")] + PB11<10>, + + #[cfg(feature = "gpio-l47x")] + PE11<10>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-l41x")] + PB2<0>, + ], + + for [ + PB2<0>, + ], + + for [ + PB2<0>, + ], + + for [ + PB15<0>, + ], + } +} + +#[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" +))] +pub mod sai1 { + use super::*; + + pin! { + for [ + PA0<13>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PB0<13>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PA9<13>, + + PB9<13>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x"))] + PB12<13>, + + PE4<13>, + ], + + for [ + PA4<13>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PA14<13>, + + PB6<13>, + + PE9<13>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF9<13>, + ], + + for no:NoPin, [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PA3<13>, + + PB8<13>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x"))] + PB14<13>, + + PE2<13>, + + #[cfg(feature = "gpio-l49x")] + PG7<13>, + ], + + for no:NoPin, [ + PB4<13>, + + PE10<13>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF7<13>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PA8<13>, + + PB10<13>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x"))] + PB13<13>, + + PE5<13>, + ], + + for [ + PB3<13>, + + PE8<13>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF8<13>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PA10<13>, + + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x"))] + PB15<13>, + + #[cfg(feature = "gpio-l49x")] + PC1<13>, + + PC3<13>, + + PD6<13>, + + PE6<13>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PA13<13>, + + PB5<13>, + + PE3<13>, + + PE7<13>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF6<13>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod sai2 { + use super::*; + + pin! { + for [ + PA2<13>, + + PC9<13>, + ], + + for [ + PB12<13>, + + PD12<13>, + + PG10<13>, + ], + + for [ + PA15<13>, + + PG3<13>, + ], + + for no:NoPin, [ + PB14<13>, + + PC6<13>, + + PD9<13>, + + PG11<13>, + ], + + for no:NoPin, [ + PC7<13>, + + PC11<13>, + + PG4<13>, + ], + + for [ + PB13<13>, + + PD10<13>, + + PG9<13>, + ], + + for [ + PC10<13>, + + PG2<13>, + ], + + for [ + PB15<13>, + + PD11<13>, + + PG12<13>, + ], + + for [ + PC12<13>, + + PG5<13>, + ], + } + use crate::pac::SAI2 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +#[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" +))] +pub mod sdmmc1 { + use super::*; + + pin! { + for [ + PC12<12>, + ], + + for [ + PD2<12>, + ], + + for [ + PC8<12>, + ], + + for [ + PC9<12>, + ], + + for [ + PC10<12>, + ], + + for [ + PC11<12>, + ], + + for [ + PB8<12>, + ], + + for [ + PB9<12>, + ], + + for [ + PC6<12>, + ], + + for [ + PC7<12>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA11<5>, + + PB4<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE14<5>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG3<5>, + ], + + for no:NoPin, [ + PA7<5>, + + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA12<5>, + + PB5<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE15<5>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG4<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PB0<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE12<5>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG5<5>, + ], + + for no:NoPin, [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA1<5>, + + PA5<5>, + + PB3<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE13<5>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG2<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD3<5>, + + #[cfg(feature = "gpio-l49x")] + PI2<5>, + ], + + for no:NoPin, [ + PB15<5>, + + #[cfg(feature = "gpio-l49x")] + PC1<3>, + + PC3<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD4<5>, + + #[cfg(feature = "gpio-l49x")] + PI3<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD0<5>, + + #[cfg(feature = "gpio-l49x")] + PI0<5>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-l49x")] + PA9<3>, + + PB10<5>, + + PB13<5>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD1<5>, + + #[cfg(feature = "gpio-l49x")] + PD3<3>, + + #[cfg(feature = "gpio-l49x")] + PI1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" +))] +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG10<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG11<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG12<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG9<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any(feature = "gpio-l43x", feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod swpmi1 { + use super::*; + + pin! { + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l49x"))] + PA8<12>, + + PB12<12>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l49x"))] + PA14<12>, + + PB14<12>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l49x"))] + PA15<12>, + + PB15<12>, + ], + + for [ + #[cfg(any(feature = "gpio-l43x", feature = "gpio-l49x"))] + PA13<12>, + + PB13<12>, + ], + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + #[cfg(feature = "gpio-l41x")] + PB7<0>, + + #[cfg(feature = "gpio-l41x")] + PC0<0>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE2<0>, + ], + + for [ + #[cfg(feature = "gpio-l41x")] + PB0<0>, + + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PC1<0>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE3<0>, + ], + + for [ + #[cfg(feature = "gpio-l41x")] + PB1<0>, + + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PC10<0>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE4<0>, + ], + + for [ + #[cfg(feature = "gpio-l41x")] + PB5<0>, + + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PD2<0>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE5<0>, + ], + + for [ + #[cfg(feature = "gpio-l41x")] + PB6<0>, + + #[cfg(any(feature = "gpio-l41x", feature = "gpio-l45x", feature = "gpio-l49x"))] + PC12<0>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE6<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE9<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE8<1>, + ], + + default:PushPull for [ + PA9<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE10<1>, + ], + + default:PushPull for [ + PA10<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE13<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE12<1>, + ], + + default:PushPull for [ + PA11<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE14<1>, + ], + } + + pin! { + for [ + PA6<1>, + + PB12<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE15<1>, + ], + + for [ + PA11<2>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE14<2>, + ], + + for [ + PA11<12>, + ], + + for [ + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE14<3>, + ], + + for [ + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE15<3>, + ], + + for [ + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PA6<12>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PB12<3>, + ], + + for [ + PA12<1>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-l45x", feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE3<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + + PE5<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + + PE6<2>, + ], + } + + pin! { + for [ + PD2<2>, + + PE2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PF6<2>, + + #[cfg(feature = "gpio-l49x")] + PH10<2>, + ], + + default:PushPull for [ + PA1<2>, + + PF7<2>, + + #[cfg(feature = "gpio-l49x")] + PH11<2>, + ], + + default:PushPull for [ + PA2<2>, + + PF8<2>, + + #[cfg(feature = "gpio-l49x")] + PH12<2>, + ], + + default:PushPull for [ + PA3<2>, + + PF9<2>, + + #[cfg(feature = "gpio-l49x")] + PI0<2>, + ], + } + + pin! { + for [ + PF6<1>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + + #[cfg(feature = "gpio-l49x")] + PI5<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + + #[cfg(feature = "gpio-l49x")] + PH13<3>, + ], + + default:PushPull for [ + PC7<3>, + + #[cfg(feature = "gpio-l49x")] + PI6<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + + #[cfg(feature = "gpio-l49x")] + PH14<3>, + ], + + default:PushPull for [ + PC8<3>, + + #[cfg(feature = "gpio-l49x")] + PI7<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + + #[cfg(feature = "gpio-l49x")] + PH15<3>, + ], + + default:PushPull for [ + PC9<3>, + + #[cfg(feature = "gpio-l49x")] + PI2<3>, + ], + } + + pin! { + for [ + PA6<3>, + + PB7<3>, + + #[cfg(feature = "gpio-l49x")] + PI4<3>, + ], + + for [ + PB6<3>, + + PC9<1>, + ], + + for [ + PC9<14>, + ], + + for [ + PB6<12>, + ], + + for [ + PB7<13>, + ], + + for [ + PA6<13>, + ], + } + + pin! { + for [ + PA0<3>, + + #[cfg(feature = "gpio-l49x")] + PI3<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<14>, + + PB14<14>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF9<14>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG10<14>, + ], + + default:PushPull for [ + PA1<14>, + + PB13<14>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG9<14>, + ], + + default:PushPull for [ + PA3<14>, + + PB15<14>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PF10<14>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG11<14>, + ], + } + + pin! { + for [ + PA9<14>, + + PB12<14>, + ], + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<14>, + + PB8<14>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PE0<14>, + ], + + default:PushPull for [ + PB6<14>, + ], + } + + pin! { + for [ + PB5<14>, + ], + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<14>, + + PB9<14>, + + PE1<14>, + ], + + default:PushPull for [ + PB7<14>, + ], + } + + pin! { + for [ + PA10<14>, + + PB4<14>, + ], + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tsc { + use super::*; + + pin! { + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PB10<9>, + + PD2<9>, + ], + } + + pin! { + default:PushPull for [ + PB12<9>, + ], + + default:PushPull for [ + PB13<9>, + ], + + default:PushPull for [ + PB14<9>, + ], + + default:PushPull for [ + PB15<9>, + ], + + default:PushPull for [ + PB4<9>, + ], + + default:PushPull for [ + PB5<9>, + ], + + default:PushPull for [ + PB6<9>, + ], + + default:PushPull for [ + PB7<9>, + ], + + default:PushPull for [ + PA15<9>, + ], + + default:PushPull for [ + PC10<9>, + ], + + default:PushPull for [ + PC11<9>, + ], + + default:PushPull for [ + PC12<9>, + ], + + default:PushPull for [ + PC6<9>, + ], + + default:PushPull for [ + PC7<9>, + ], + + default:PushPull for [ + PC8<9>, + ], + + default:PushPull for [ + PC9<9>, + ], + } + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + pin! { + default:PushPull for [ + PE10<9>, + ], + + default:PushPull for [ + PE11<9>, + ], + + default:PushPull for [ + PE12<9>, + ], + + default:PushPull for [ + PE13<9>, + ], + + default:PushPull for [ + PD10<9>, + ], + + default:PushPull for [ + PD11<9>, + ], + + default:PushPull for [ + PD12<9>, + ], + + default:PushPull for [ + PD13<9>, + ], + + default:PushPull for [ + PE2<9>, + ], + + default:PushPull for [ + PE3<9>, + ], + + default:PushPull for [ + PE4<9>, + ], + + default:PushPull for [ + PE5<9>, + ], + } + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + pin! { + default:PushPull for [ + PF14<9>, + ], + + default:PushPull for [ + PF15<9>, + ], + + default:PushPull for [ + PG0<9>, + ], + + default:PushPull for [ + PG1<9>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + + PB5<7>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG13<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG11<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG12<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG10<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + #[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] + PG9<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD7<7>, + ], + + for [ + PA0<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD3<7>, + ], + + for [ + PA1<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD4<7>, + ], + + for [ + PA1<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA15<3>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB0<7>, + + PB12<7>, + + PC12<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD10<7>, + ], + + for [ + PA6<7>, + + PB13<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD11<7>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD12<7>, + ], + + for [ + #[cfg(any( + feature = "gpio-l41x", + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l49x" + ))] + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC5<7>, + + PC11<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC4<7>, + + PC10<7>, + + #[cfg(any( + feature = "gpio-l43x", + feature = "gpio-l45x", + feature = "gpio-l47x", + feature = "gpio-l49x" + ))] + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-l45x", feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod uart4 { + use super::*; + + pin! { + for [ + PB7<8>, + ], + + for [ + PA15<8>, + ], + + for [ + PA15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + PC11<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + PC10<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod uart5 { + use super::*; + + pin! { + for [ + PB5<8>, + ], + + for [ + PB4<8>, + ], + + for [ + PB4<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-l41x", feature = "gpio-l43x", feature = "gpio-l45x"))] +pub mod usb { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA13<10>, + + PC9<10>, + ], + } +} + +#[cfg(any(feature = "gpio-l47x", feature = "gpio-l49x"))] +pub mod otg_fs { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA10<10>, + ], + + for [ + PA13<10>, + + PC9<10>, + ], + + for [ + PA8<10>, + + #[cfg(feature = "gpio-l49x")] + PA14<10>, + ], + } +} diff --git a/src/gpio/alt/l4p.rs b/src/gpio/alt/l4p.rs new file mode 100644 index 00000000..1abf2ee6 --- /dev/null +++ b/src/gpio/alt/l4p.rs @@ -0,0 +1,3254 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod can1 { + use super::*; + + pin! { + for no:NoPin, [ + PA11<9>, + + PB8<9>, + + PD0<9>, + + PI9<9>, + ], + + for no:NoPin, [ + PA12<9>, + + PB9<9>, + + PD1<9>, + + PH13<9>, + ], + } + impl CanCommon for crate::pac::CAN1 { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod comp1 { + use super::*; + + pin! { + for [ + PB0<12>, + + PB10<12>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PB5<12>, + + PB11<12>, + ], + } +} + +/*pub mod crs { + use super::*; + + pin! { + for [ + PB3<10>, + ], + } +}*/ + +pub mod dcmi { + use super::*; + + pin! { + for [ + PA9<5>, + + PC6<10>, + + PH9<10>, + ], + + for [ + PA10<5>, + + PC7<10>, + + PH10<10>, + ], + + for [ + PB5<10>, + + PD6<4>, + + PI3<10>, + ], + + for [ + PD2<10>, + + PF10<10>, + + PH15<10>, + ], + + for [ + PB4<10>, + + PF11<10>, + + PI8<10>, + ], + + for [ + PG15<10>, + + PI0<10>, + ], + + for [ + PC8<10>, + + PC11<4>, + + PE0<10>, + + PH11<10>, + ], + + for [ + PC9<4>, + + PE1<10>, + + PH12<10>, + ], + + for [ + PC11<10>, + + PE4<10>, + + PH14<10>, + ], + + for [ + PB6<10>, + + PD3<4>, + + PI4<10>, + ], + + for [ + PB8<10>, + + PE5<10>, + + PI6<10>, + ], + + for [ + PB9<10>, + + PE6<10>, + + PI7<10>, + ], + + for [ + PC10<10>, + + PH6<10>, + + PI1<10>, + ], + + for [ + PC12<10>, + + PH7<10>, + + PI2<10>, + ], + + for [ + PA4<10>, + + PD8<10>, + + PH8<10>, + ], + + for [ + PA6<4>, + + PD9<10>, + + PH5<10>, + ], + + for [ + PB7<10>, + + #[cfg(feature = "gpio-l4p")] + PC10<4>, + + PI5<10>, + ], + } +} + +pub mod dfsdm1 { + use super::*; + + pin! { + for [ + PB2<6>, + + PD4<6>, + ], + + for [ + PB13<6>, + + PD7<6>, + ], + + for [ + PB15<6>, + + PE8<6>, + ], + + for [ + PC6<6>, + + PE5<6>, + ], + + for [ + PB8<5>, + + PC2<6>, + + PE9<6>, + + PF10<6>, + + PG7<6>, + ], + + for [ + PB1<6>, + + PD3<6>, + ], + + for [ + PB12<6>, + + PD6<6>, + ], + + for [ + PB14<6>, + + PE7<6>, + ], + + for [ + PC7<6>, + + PE4<6>, + ], + } + + #[cfg(feature = "gpio-l4rx")] + pin! { + for [ + PC1<6>, + + PE11<6>, + ], + + for [ + PB7<6>, + + PE13<6>, + ], + + for [ + PB9<6>, + + PF14<6>, + ], + + for [ + PB11<6>, + + PD1<6>, + ], + + for [ + PC0<6>, + + PE10<6>, + ], + + for [ + PB6<6>, + + PE12<6>, + ], + + for [ + PB8<6>, + + PF13<6>, + ], + + for [ + PB10<6>, + + PD0<6>, + ], + } + + use crate::pac::DFSDM1 as DFSDM; + impl DfsdmBasic for DFSDM { + type Ckin0 = Ckin0; + type Ckin1 = Ckin1; + type Ckout = Ckout; + type Datin0 = Datin0; + type Datin1 = Datin1; + } + impl DfsdmGeneral for DFSDM { + type Ckin2 = Ckin2; + type Ckin3 = Ckin3; + type Datin2 = Datin2; + type Datin3 = Datin3; + } + + #[cfg(feature = "gpio-l4rx")] + impl DfsdmAdvanced for DFSDM { + type Ckin4 = Ckin4; + type Ckin5 = Ckin5; + type Ckin6 = Ckin6; + type Ckin7 = Ckin7; + type Datin4 = Datin4; + type Datin5 = Datin5; + type Datin6 = Datin6; + type Datin7 = Datin7; + } +} + +#[cfg(feature = "gpio-l4rx")] +pub mod dsihost { + use super::*; + + pin! { + for [ + PB7<11>, + + PB11<11>, + + PF11<11>, + + PG6<11>, + ], + } +} + +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PG7<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + + PG14<4>, + ], + + for [ + PB7<4>, + + PB9<4>, + + PG13<4>, + ], + + for [ + PA1<4>, + + PA14<4>, + + PB5<4>, + + PG15<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PB13<4>, + + PF1<4>, + + PH4<4>, + ], + + for [ + PB11<4>, + + PB14<4>, + + PF0<4>, + + PH5<4>, + ], + + for [ + PB12<4>, + + PF2<4>, + + PH6<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA7<4>, + + PC0<4>, + + PG7<4>, + + PH7<4>, + ], + + for [ + PB4<4>, + + PC1<4>, + + PC9<6>, + + PG8<4>, + + PH8<4>, + ], + + for [ + PB2<4>, + + PG6<4>, + + PH9<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c4 { + use super::*; + + pin! { + for [ + PB6<5>, + + PB10<3>, + + PD12<4>, + + PF14<4>, + ], + + for [ + PB7<5>, + + PB11<3>, + + PD13<4>, + + PF15<4>, + ], + + for [ + PA14<5>, + + PD11<4>, + + PF13<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + PB9<1>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<1>, + + PC3<1>, + + PG12<1>, + ], + + for [ + PB5<1>, + + PC0<1>, + + PG10<1>, + ], + + for [ + PB7<1>, + + PC2<1>, + + PG11<1>, + ], + } + + pin! { + default:PushPull for [ + PA14<1>, + + PB2<1>, + + PC1<1>, + + PG15<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA5<14>, + + PC3<14>, + + PD11<14>, + ], + + for [ + PB1<14>, + + PC0<14>, + + PD12<14>, + ], + } + + pin! { + default:PushPull for [ + PA4<14>, + + PA8<14>, + + PD13<14>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<8>, + + PB13<8>, + + PG5<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + + PG6<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + + PG6<8>, + ], + + for [ + PA3<8>, + + PB10<8>, + + PC0<8>, + + PG8<8>, + ], + } + + pin! { + default:PushPull for [ + PA2<8>, + + PB11<8>, + + PC1<8>, + + PG7<8>, + ], + } +} + +pub mod ltdc { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-l4rx")] + PE4<11>, + + PF12<11>, + ], + + for [ + #[cfg(feature = "gpio-l4rx")] + PB2<11>, + + #[cfg(feature = "gpio-l4rx")] + PB8<11>, + + PF13<11>, + ], + + for [ + PD14<11>, + ], + + for [ + PD15<11>, + ], + + for [ + PD0<11>, + ], + + for [ + PD1<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB0<11>, + + #[cfg(feature = "gpio-l4p")] + PC7<11>, + + PE7<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA8<11>, + + #[cfg(feature = "gpio-l4p")] + PE4<11>, + + PE8<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA4<11>, + + #[cfg(feature = "gpio-l4p")] + PC5<11>, + + PD3<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA11<11>, + + #[cfg(feature = "gpio-l4p")] + PB8<11>, + + #[cfg(feature = "gpio-l4p")] + PC0<11>, + + PD6<11>, + + PF11<9>, + ], + + for [ + #[cfg(feature = "gpio-l4rx")] + PE5<11>, + + PF14<11>, + ], + + for [ + #[cfg(feature = "gpio-l4rx")] + PE6<11>, + + PF15<11>, + ], + + for [ + PE9<11>, + ], + + for [ + PE10<11>, + ], + + for [ + PE11<11>, + ], + + for [ + PE12<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA10<11>, + + #[cfg(feature = "gpio-l4p")] + PB1<11>, + + #[cfg(feature = "gpio-l4p")] + PE6<11>, + + PE13<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA9<11>, + + #[cfg(feature = "gpio-l4p")] + PC6<11>, + + #[cfg(feature = "gpio-l4p")] + PE5<11>, + + PE14<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA15<11>, + + #[cfg(feature = "gpio-l4p")] + PC2<11>, + + PE0<11>, + ], + + for [ + #[cfg(feature = "gpio-l4rx")] + PC6<11>, + + #[cfg(feature = "gpio-l4rx")] + PE2<11>, + + PG13<11>, + ], + + for [ + #[cfg(feature = "gpio-l4rx")] + PC7<11>, + + #[cfg(feature = "gpio-l4rx")] + PE3<11>, + + PG6<9>, + + PG14<11>, + ], + + for [ + PE15<11>, + ], + + for [ + PD8<11>, + ], + + for [ + PD9<11>, + ], + + for [ + PD10<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB6<11>, + + #[cfg(feature = "gpio-l4p")] + PC12<11>, + + PD11<11>, + + #[cfg(feature = "gpio-l4p")] + PE3<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA5<11>, + + PD12<11>, + + #[cfg(feature = "gpio-l4p")] + PE2<11>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PA12<11>, + + #[cfg(feature = "gpio-l4p")] + PB7<11>, + + #[cfg(feature = "gpio-l4p")] + PB11<11>, + + PE1<11>, + ], + } +} + +pub mod octospim { + use super::*; + + pin! { + for [ // High speed + PA3<10>, + + PB10<10>, + + PE10<10>, + + PF10<3>, + ], + + for [ + PA1<10>, + + PB2<10>, + + PE3<3>, + + PG6<3>, + ], + + for [ + PB1<10>, + + #[cfg(feature = "gpio-l4p")] + PB5<3>, + + PE12<10>, + + PF8<10>, + ], + + for [ + PB0<10>, + + #[cfg(feature = "gpio-l4p")] + PB13<10>, + + PE13<10>, + + PF9<10>, + ], + + for [ + PA7<10>, + + PE14<10>, + + PF7<10>, + ], + + for [ + PA6<10>, + + #[cfg(feature = "gpio-l4p")] + PB10<6>, + + PE15<10>, + + PF6<10>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB3<3>, + + PC1<10>, + + PD4<10>, + + PH2<3>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB4<3>, + + PC2<10>, + + PD5<10>, + + PG11<3>, + + PI0<3>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB14<10>, + + PC3<10>, + + PD6<10>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB15<10>, + + PC4<10>, + + PD7<10>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PB12<10>, + + #[cfg(feature = "gpio-l4p")] + PE9<10>, + + #[cfg(feature = "gpio-l4p")] + PF11<3>, + ], + + for [ + PA2<10>, + + PA4<3>, + + PB11<10>, + + PC11<5>, + + PE11<10>, + ], + + for [ + PF4<5>, + + PH6<5>, + + PI6<5>, + ], + + for [ + PF12<5>, + + PG7<5>, + + PG15<5>, + + PH4<5>, + ], + + for [ + PF0<5>, + + PI11<5>, + ], + + for [ + PF1<5>, + + PI10<5>, + ], + + for [ + PF2<5>, + + PI9<5>, + ], + + for [ + PF3<5>, + + PH8<5>, + ], + + for [ + PG0<5>, + + PH9<5>, + ], + + for [ + PG1<5>, + + PH10<5>, + ], + + for [ + PG9<5>, + + PH11<5>, + + PH15<5>, + ], + + for [ + PG10<5>, + + PH12<5>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PF5<5>, + + #[cfg(feature = "gpio-l4p")] + PH7<5>, + + #[cfg(feature = "gpio-l4p")] + PI7<5>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PC4<5>, + + PD3<10>, + + PG12<5>, + + PI5<5>, + + PI8<5>, + ], + } +} + +#[cfg(feature = "gpio-l4p")] +pub mod pssi { + use super::*; + + pin! { + for [ + PA9<5>, + + PC6<10>, + + PH9<10>, + ], + + for [ + PA10<5>, + + PC7<10>, + + PH10<10>, + ], + + for [ + PB5<10>, + + PD6<4>, + + PI3<10>, + ], + + for [ + PD2<10>, + + PF10<10>, + + PH15<10>, + ], + + for [ + PB4<10>, + + PF11<10>, + + PI8<10>, + ], + + for [ + PG15<10>, + + PI0<10>, + ], + + for [ + PA5<4>, + + PH4<10>, + + PI10<10>, + ], + + for [ + PC5<4>, + + PF10<4>, + + PI11<10>, + ], + + for [ + PC8<10>, + + PC11<4>, + + PE0<10>, + + PH11<10>, + ], + + for [ + PC9<4>, + + PE1<10>, + + PH12<10>, + ], + + for [ + PC11<10>, + + PE4<10>, + + PH14<10>, + ], + + for [ + PB6<10>, + + PD3<4>, + + PI4<10>, + ], + + for [ + PB8<10>, + + PE5<10>, + + PI6<10>, + ], + + for [ + PB9<10>, + + PE6<10>, + + PI7<10>, + ], + + for [ + PC10<10>, + + PH6<10>, + + PI1<10>, + ], + + for [ + PC12<10>, + + PH7<10>, + + PI2<10>, + ], + + for [ + PA4<10>, + + PD8<10>, + + PH8<10>, + ], + + for [ + PA6<4>, + + PD9<10>, + + PH5<10>, + ], + + for [ + PB7<10>, + + PC10<4>, + + PI5<10>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-l4rx")] + PB2<0>, + ], + + for [ + #[cfg(feature = "gpio-l4rx")] + PB2<0>, + ], + + for [ + PB15<0>, + ], + } +} + +pub mod sai1 { + use super::*; + + pin! { + for [ + PA3<3>, + + PB8<3>, + + PE2<3>, + + PG7<3>, + ], + + for [ + PA8<3>, + + PE5<3>, + ], + + for [ + PA10<3>, + + PC3<3>, + + PD6<3>, + + PE6<3>, + ], + + for [ + PB9<3>, + + PE4<3>, + ], + + for [ + PC5<3>, + + PF10<13>, + ], + + for [ + PA0<13>, + + PB0<13>, + ], + + for [ + PA9<13>, + + PB9<13>, + + PE4<13>, + ], + + for [ + PA4<13>, + + PA14<13>, + + PB6<13>, + + PE9<13>, + + PF9<13>, + ], + + for no:NoPin, [ + PA3<13>, + + PB8<13>, + + PE2<13>, + + PG7<13>, + ], + + for no:NoPin, [ + PB4<13>, + + PE10<13>, + + PF7<13>, + ], + + for [ + PA8<13>, + + PB10<13>, + + PE5<13>, + ], + + for [ + PB3<13>, + + PE8<13>, + + PF8<13>, + ], + + for [ + PA10<13>, + + PC1<13>, + + PC3<13>, + + PD6<13>, + + PE6<13>, + ], + + for [ + PA13<13>, + + PB5<13>, + + PE3<13>, + + PE7<13>, + + PF6<13>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sai2 { + use super::*; + + pin! { + for [ + PA2<13>, + + PC9<13>, + ], + + for [ + PB12<13>, + + PC0<13>, + + PD12<13>, + + PG10<13>, + ], + + for [ + PA15<13>, + + PG3<13>, + ], + + for no:NoPin, [ + PB14<13>, + + PC6<13>, + + PD9<13>, + + PG11<13>, + ], + + for no:NoPin, [ + PC7<13>, + + PC11<13>, + + PG4<13>, + ], + + for [ + PB13<13>, + + PD10<13>, + + PG9<13>, + ], + + for [ + PC10<13>, + + PG2<13>, + ], + + for [ + PB15<13>, + + PD11<13>, + + PG12<13>, + ], + + for [ + PC12<13>, + + PG5<13>, + ], + } + use crate::pac::SAI2 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sdmmc1 { + use super::*; + + pin! { + for [ + PB9<8>, + ], + + for [ + PC12<12>, + ], + + for [ + PB8<8>, + ], + + for [ + #[cfg(feature = "gpio-l4p")] + PC0<12>, + + PD2<12>, + ], + + for [ + PC8<12>, + ], + + for [ + PC6<8>, + ], + + for [ + PC9<12>, + ], + + for [ + PC7<8>, + ], + + for [ + PC10<12>, + ], + + for [ + PC11<12>, + ], + + for [ + PB8<12>, + ], + + for [ + PB9<12>, + ], + + for [ + PC6<12>, + ], + + for [ + PC7<12>, + ], + } +} + +#[cfg(feature = "gpio-l4p")] +pub mod sdmmc2 { + use super::*; + + pin! { + for [ + PB12<12>, + + PD6<8>, + ], + + for [ + PC0<7>, + + PD4<8>, + ], + + for [ + PA1<12>, + + PD7<8>, + ], + + for [ + PB14<11>, + + PG9<11>, + ], + + for [ + PB15<11>, + + PG10<11>, + ], + + for [ + PB3<12>, + + PG11<11>, + ], + + for [ + PB4<12>, + + PG12<11>, + ], + + for [ + PB8<7>, + + PG2<11>, + ], + + for [ + PB9<7>, + + PG3<11>, + ], + + for [ + PC6<7>, + + PG4<11>, + ], + + for [ + PC7<7>, + + PG5<11>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PA11<5>, + + PB4<5>, + + PE14<5>, + + PG3<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PA12<5>, + + PB5<5>, + + PE15<5>, + + PG4<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PB0<5>, + + PE12<5>, + + PG5<5>, + ], + + for no:NoPin, [ + PA1<5>, + + PA5<5>, + + PB3<5>, + + PE13<5>, + + PG2<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + PD3<5>, + + PI2<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC1<3>, + + PC3<5>, + + PD4<5>, + + PI3<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + PD0<5>, + + PI0<5>, + ], + + for no:NoPin, [ + PA9<3>, + + PB10<5>, + + PB13<5>, + + PD1<5>, + + PD3<3>, + + PI1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + + PG10<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + + PD6<5>, + + PG11<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + + PG12<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + + PG9<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + PE2<0>, + ], + + for [ + PC1<0>, + + PC9<0>, + + PE3<0>, + ], + + for [ + PC10<0>, + + PE4<0>, + ], + + for [ + PD2<0>, + + PE5<0>, + ], + + for [ + PC12<0>, + + PE6<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + PE9<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + PE8<1>, + ], + + default:PushPull for [ + PA9<1>, + + PE11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + PE10<1>, + ], + + default:PushPull for [ + PA10<1>, + + PE13<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + PE12<1>, + ], + + default:PushPull for [ + PA11<1>, + + PE14<1>, + ], + } + + pin! { + for [ + PA6<12>, + + PB12<3>, + + PE15<3>, + ], + + for [ + PA11<12>, + + PE14<3>, + ], + + for [ + PA12<1>, + + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE3<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + + PE5<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + + PE6<2>, + ], + } + + pin! { + for [ + PD2<2>, + + PE2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PF6<2>, + + PH10<2>, + ], + + default:PushPull for [ + PA1<2>, + + PF7<2>, + + PH11<2>, + ], + + default:PushPull for [ + PA2<2>, + + PF8<2>, + + PH12<2>, + ], + + default:PushPull for [ + PA3<2>, + + PF9<2>, + + PI0<2>, + ], + } + + pin! { + for [ + PF6<1>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + + PI5<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + + PH13<3>, + ], + + default:PushPull for [ + PC7<3>, + + PI6<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + + PH14<3>, + ], + + default:PushPull for [ + PC8<3>, + + PI7<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + + PH15<3>, + ], + + default:PushPull for [ + PC9<3>, + + PI2<3>, + ], + } + + pin! { + for [ + PA6<13>, + + PB7<13>, + + PI4<3>, + ], + + for [ + PB6<12>, + + PC9<14>, + ], + + for [ + PA0<3>, + + PI3<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<14>, + + PB14<14>, + + PF9<14>, + + PG10<14>, + ], + + default:PushPull for [ + PA1<14>, + + PB13<14>, + + PG9<14>, + ], + + default:PushPull for [ + PA3<14>, + + PB15<14>, + + PF10<14>, + + PG11<14>, + ], + } + + pin! { + for [ + PA9<14>, + + PB12<14>, + ], + + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<14>, + + PB8<14>, + + PE0<14>, + ], + + default:PushPull for [ + PB6<14>, + ], + } + + pin! { + for [ + PB5<14>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<14>, + + PB9<14>, + + PE1<14>, + ], + + default:PushPull for [ + PB7<14>, + ], + } + + pin! { + for [ + PA10<14>, + + PB4<14>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tsc { + use super::*; + + pin! { + for [ + PB10<9>, + + PD2<9>, + ], + } + + pin! { + default:PushPull for [ + PB12<9>, + ], + + default:PushPull for [ + PB13<9>, + ], + + default:PushPull for [ + PB14<9>, + ], + + default:PushPull for [ + PB15<9>, + ], + + default:PushPull for [ + PB4<9>, + ], + + default:PushPull for [ + PB5<9>, + ], + + default:PushPull for [ + PB6<9>, + ], + + default:PushPull for [ + PB7<9>, + ], + + default:PushPull for [ + PA15<9>, + ], + + default:PushPull for [ + PC10<9>, + ], + + default:PushPull for [ + PC11<9>, + ], + + default:PushPull for [ + PC12<9>, + ], + + default:PushPull for [ + PC6<9>, + ], + + default:PushPull for [ + PC7<9>, + ], + + default:PushPull for [ + PC8<9>, + ], + + default:PushPull for [ + PC9<9>, + ], + + default:PushPull for [ + PE10<9>, + ], + + default:PushPull for [ + PE11<9>, + ], + + default:PushPull for [ + PE12<9>, + ], + + default:PushPull for [ + PE13<9>, + ], + + default:PushPull for [ + PD10<9>, + ], + + default:PushPull for [ + PD11<9>, + ], + + default:PushPull for [ + PD12<9>, + ], + + default:PushPull for [ + PD13<9>, + ], + + default:PushPull for [ + PE2<9>, + ], + + default:PushPull for [ + PE3<9>, + ], + + default:PushPull for [ + PE4<9>, + ], + + default:PushPull for [ + PE5<9>, + ], + + default:PushPull for [ + PF14<9>, + ], + + default:PushPull for [ + PF15<9>, + ], + + default:PushPull for [ + PG0<9>, + ], + + default:PushPull for [ + PG1<9>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + + PB5<7>, + + PG13<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + + PG11<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + PG12<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + + PG11<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + PG12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + PG10<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + PG9<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PA15<3>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB0<7>, + + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PA6<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + PD12<7>, + ], + + for [ + PA6<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC5<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC4<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart4 { + use super::*; + + pin! { + for [ + PB7<8>, + ], + + for [ + PA15<8>, + ], + + for [ + PA15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + PC11<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + PC10<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart5 { + use super::*; + + pin! { + for [ + PB5<8>, + ], + + for [ + PB4<8>, + ], + + for [ + PB4<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod otg_fs { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA10<10>, + ], + + for [ + PA13<10>, + + PC9<10>, + ], + + for [ + PA8<10>, + + PA14<10>, + ], + } +} diff --git a/src/gpio/alt/l5.rs b/src/gpio/alt/l5.rs new file mode 100644 index 00000000..4e4dc491 --- /dev/null +++ b/src/gpio/alt/l5.rs @@ -0,0 +1,2427 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +pub mod comp1 { + use super::*; + + pin! { + for [ + PB0<12>, + + PB10<12>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PB5<12>, + + PB11<12>, + ], + } +} + +/*pub mod crs { + use super::*; + + pin! { + for [ + PA10<10>, + + PB3<10>, + ], + } +}*/ + +pub mod debug { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + PE2<0>, + ], + + for [ + PC1<0>, + + PC9<0>, + + PE3<0>, + ], + + for [ + PC10<0>, + + PE4<0>, + ], + + for [ + PD2<0>, + + PE5<0>, + ], + + for [ + PC12<0>, + + PE6<0>, + ], + } +} + +pub mod dfsdm1 { + use super::*; + + pin! { + for [ + PB2<6>, + + PD4<6>, + ], + + for [ + PB13<6>, + + PD7<6>, + ], + + for [ + PB15<6>, + + PE8<6>, + ], + + for [ + PC6<6>, + + PE5<6>, + ], + + for [ + PB8<5>, + + PC2<6>, + + PE9<6>, + + PF10<6>, + + PG7<6>, + ], + + for [ + PB1<6>, + + PD3<6>, + ], + + for [ + PB12<6>, + + PD6<6>, + ], + + for [ + PB14<6>, + + PE7<6>, + ], + + for [ + PC7<6>, + + PE4<6>, + ], + } + + use crate::pac::DFSDM1 as DFSDM; + impl DfsdmBasic for DFSDM { + type Ckin0 = Ckin0; + type Ckin1 = Ckin1; + type Ckout = Ckout; + type Datin0 = Datin0; + type Datin1 = Datin1; + } + impl DfsdmGeneral for DFSDM { + type Ckin2 = Ckin2; + type Ckin3 = Ckin3; + type Datin2 = Datin2; + type Datin3 = Datin3; + } +} + +pub mod fdcan1 { + use super::*; + + pin! { + for [ + PA11<9>, + + PB8<9>, + + PD0<9>, + ], + + for [ + PA12<9>, + + PB9<9>, + + PD1<9>, + ], + } +} + +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PG7<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + + PG14<4>, + ], + + for [ + PB7<4>, + + PB9<4>, + + PG13<4>, + ], + + for [ + PA1<4>, + + PA14<4>, + + PB5<4>, + + PG15<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PB13<4>, + + PF1<4>, + ], + + for [ + PB11<4>, + + PB14<4>, + + PF0<4>, + ], + + for [ + PB12<4>, + + PF2<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA7<4>, + + PC0<4>, + + PG7<4>, + ], + + for [ + PB4<4>, + + PC1<4>, + + PG8<4>, + ], + + for [ + PB2<4>, + + PG6<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c4 { + use super::*; + + pin! { + for [ + PB6<5>, + + PB10<3>, + + PD12<4>, + + PF14<4>, + ], + + for [ + PB7<5>, + + PB11<3>, + + PD13<4>, + + PF15<4>, + ], + + for [ + PA14<5>, + + PD11<4>, + + PF13<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + PB9<1>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<1>, + + PC3<1>, + + PG12<1>, + ], + + for [ + PB5<1>, + + PC0<1>, + + PG10<1>, + ], + + for [ + PB7<1>, + + PC2<1>, + + PG11<1>, + ], + + default:PushPull for [ + PA14<1>, + + PB2<1>, + + PC1<1>, + + PG15<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA5<14>, + + PC3<14>, + + PD11<14>, + ], + + for [ + PB1<14>, + + PC0<14>, + + PD12<14>, + ], + + default:PushPull for [ + PA4<14>, + + PA8<14>, + + PD13<14>, + ], + } +} + +pub mod lptim3 { + use super::*; + + pin! { + for [ + PB14<2>, + + PC10<2>, + + PF4<2>, + ], + + for [ + PB13<2>, + + PC11<2>, + + PF3<2>, + ], + + default:PushPull for [ + PB10<2>, + + PC3<2>, + + PF5<2>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<8>, + + PB13<8>, + + PG5<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + + PG6<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + + PG6<8>, + ], + + for [ + PA3<8>, + + PB10<8>, + + PC0<8>, + + PG8<8>, + ], + } + + pin! { + default:PushPull for [ + PA2<8>, + + PB11<8>, + + PC1<8>, + + PG7<8>, + ], + } +} + +pub mod octospi1 { + use super::*; + + pin! { + for [ // High speed + PA3<10>, + + PB10<10>, + + PE10<10>, + + PF10<3>, + ], + + for [ + PA1<10>, + + PB2<10>, + + PE3<3>, + + PG6<3>, + ], + + for [ + PB1<10>, + + PE12<10>, + + PF8<10>, + ], + + for [ + PB0<10>, + + PE13<10>, + + PF9<10>, + ], + + for [ + PA7<10>, + + PE14<10>, + + PF7<10>, + ], + + for [ + PA6<10>, + + PE15<10>, + + PF6<10>, + ], + + for [ + PC1<10>, + + PD4<10>, + ], + + for [ + PC2<10>, + + PD5<10>, + + PG11<3>, + ], + + for [ + PC3<10>, + + PD6<10>, + ], + + for [ + PC0<3>, + + PC4<10>, + + PD7<10>, + ], + + for [ + PB5<3>, + + PB12<10>, + + PE9<10>, + + PF11<3>, + ], + + for [ + PA2<10>, + + PA4<3>, + + PB11<10>, + + PC11<5>, + + PE11<10>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PB15<0>, + ], + } +} + +pub mod sai1 { + use super::*; + + pin! { + for [ + PA3<3>, + + PB8<3>, + + PE2<3>, + + PG7<3>, + ], + + for [ + PA8<3>, + + PE5<3>, + ], + + for [ + PA10<3>, + + PC3<3>, + + PD6<3>, + + PE6<3>, + ], + + for [ + PB9<3>, + + PE4<3>, + ], + + for [ + PC5<3>, + + PF10<13>, + ], + + for [ + PA0<13>, + + PB0<13>, + ], + + for [ + PA9<13>, + + PB9<13>, + + PE4<13>, + ], + + for [ + PA4<13>, + + PA14<13>, + + PB6<13>, + + PE9<13>, + + PF9<13>, + ], + + for no:NoPin, [ + PA3<13>, + + PB8<13>, + + PE2<13>, + + PG7<13>, + ], + + for no:NoPin, [ + PB4<13>, + + PE10<13>, + + PF7<13>, + ], + + for [ + PA8<13>, + + PB10<13>, + + PE5<13>, + ], + + for [ + PB3<13>, + + PE8<13>, + + PF8<13>, + ], + + for [ + PA10<13>, + + PC1<13>, + + PC3<13>, + + PD6<13>, + + PE6<13>, + ], + + for [ + PA13<13>, + + PB5<13>, + + PE3<13>, + + PE7<13>, + + PF6<13>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sai2 { + use super::*; + + pin! { + for [ + PA2<13>, + + PC9<13>, + ], + + for [ + PB12<13>, + + PC0<13>, + + PD12<13>, + + PG10<13>, + ], + + for [ + PA15<13>, + + PG3<13>, + ], + + for no:NoPin, [ + PB14<13>, + + PC6<13>, + + PD9<13>, + + PG11<13>, + ], + + for no:NoPin, [ + PC7<13>, + + PC11<13>, + + PG4<13>, + ], + + for [ + PB13<13>, + + PD10<13>, + + PG9<13>, + ], + + for [ + PC10<13>, + + PG2<13>, + ], + + for [ + PB15<13>, + + PD11<13>, + + PG12<13>, + ], + + for [ + PC12<13>, + + PG5<13>, + ], + } + use crate::pac::SAI2 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sdmmc1 { + use super::*; + + pin! { + for [ + PB9<8>, + ], + + for [ + PC12<12>, + ], + + for [ + PB8<8>, + ], + + for [ + PD2<12>, + ], + + for [ + PC8<12>, + ], + + for [ + PC6<8>, + ], + + for [ + PC9<12>, + ], + + for [ + PC7<8>, + ], + + for [ + PC10<12>, + ], + + for [ + PC11<12>, + ], + + for [ + PB8<12>, + ], + + for [ + PB9<12>, + + PC0<12>, + ], + + for [ + PC6<12>, + ], + + for [ + PC7<12>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PA11<5>, + + PB4<5>, + + PE14<5>, + + PG3<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PA12<5>, + + PB5<5>, + + PE15<5>, + + PG4<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PB0<5>, + + PE12<5>, + + PG5<5>, + ], + + for no:NoPin, [ + PA1<5>, + + PA5<5>, + + PB3<5>, + + PE13<5>, + + PG2<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + PD3<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC1<3>, + + PC3<5>, + + PD4<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + PD0<5>, + ], + + for no:NoPin, [ + PA9<3>, + + PB10<5>, + + PB13<5>, + + PD1<5>, + + PD3<3>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + + PG10<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + + PD6<5>, + + PG11<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + + PG12<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + + PG9<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + PE9<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + PE8<1>, + ], + + default:PushPull for [ + PA9<1>, + + PE11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + PE10<1>, + ], + + default:PushPull for [ + PA10<1>, + + PE13<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + PE12<1>, + ], + + default:PushPull for [ + PA11<1>, + + PE14<1>, + ], + } + + pin! { + for [ + PA6<12>, + + PB12<3>, + + PE15<3>, + ], + + for [ + PA11<12>, + + PE14<3>, + ], + + for [ + PA12<1>, + + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE3<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + + PE5<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + + PE6<2>, + ], + } + + pin! { + for [ + PD2<2>, + + PE2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PF6<2>, + ], + + default:PushPull for [ + PA1<2>, + + PF7<2>, + ], + + default:PushPull for [ + PA2<2>, + + PF8<2>, + ], + + default:PushPull for [ + PA3<2>, + + PF9<2>, + ], + } + + pin! { + for [ + PF6<1>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + ], + + default:PushPull for [ + PC7<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + ], + + default:PushPull for [ + PC8<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + ], + + default:PushPull for [ + PC9<3>, + ], + } + + pin! { + for [ + PA6<13>, + + PB7<13>, + ], + + for [ + PB6<12>, + + PC9<14>, + ], + + for [ + PA0<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<14>, + + PB14<14>, + + PF9<14>, + + PG10<14>, + ], + + default:PushPull for [ + PA1<14>, + + PB13<14>, + + PG9<14>, + ], + + default:PushPull for [ + PA3<14>, + + PB15<14>, + + PF10<14>, + + PG11<14>, + ], + } + + pin! { + for [ + PA9<14>, + + PB12<14>, + ], + + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<14>, + + PB8<14>, + + PE0<14>, + ], + + default:PushPull for [ + PB6<14>, + ], + } + + pin! { + for [ + PB5<14>, + ], + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<14>, + + PB9<14>, + + PE1<14>, + ], + + default:PushPull for [ + PB7<14>, + ], + } + + pin! { + for [ + PA10<14>, + + PB4<14>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tsc { + use super::*; + + pin! { + for [ + PB10<9>, + + PD2<9>, + ], + } + + pin! { + default:PushPull for [ + PB12<9>, + ], + + default:PushPull for [ + PB13<9>, + ], + + default:PushPull for [ + PB14<9>, + ], + + default:PushPull for [ + PB4<9>, + ], + + default:PushPull for [ + PB5<9>, + ], + + default:PushPull for [ + PB6<9>, + ], + + default:PushPull for [ + PB7<9>, + ], + + default:PushPull for [ + PC10<9>, + ], + + default:PushPull for [ + PC11<9>, + ], + + default:PushPull for [ + PC12<9>, + ], + + default:PushPull for [ + PC6<9>, + ], + + default:PushPull for [ + PC7<9>, + ], + + default:PushPull for [ + PC8<9>, + ], + + default:PushPull for [ + PC9<9>, + ], + + default:PushPull for [ + PE10<9>, + ], + + default:PushPull for [ + PE11<9>, + ], + + default:PushPull for [ + PE12<9>, + ], + + default:PushPull for [ + PE13<9>, + ], + + default:PushPull for [ + PD10<9>, + ], + + default:PushPull for [ + PD11<9>, + ], + + default:PushPull for [ + PD12<9>, + ], + + default:PushPull for [ + PD13<9>, + ], + + default:PushPull for [ + PE2<9>, + ], + + default:PushPull for [ + PE3<9>, + ], + + default:PushPull for [ + PE4<9>, + ], + + default:PushPull for [ + PE5<9>, + ], + + default:PushPull for [ + PF14<9>, + ], + + default:PushPull for [ + PF15<9>, + ], + + default:PushPull for [ + PG0<9>, + ], + + default:PushPull for [ + PG1<9>, + ], + } +} + +pub mod ucpd1 { + use super::*; + + pin! { + default:PushPull for [ + PA2<11>, + + PB2<11>, + + PB13<11>, + + PC11<11>, + + PG6<11>, + + PG7<11>, + ], + + default:PushPull for [ + PA2<11>, + + PB2<11>, + + PB13<11>, + + PC11<11>, + + PG6<11>, + + PG7<11>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + + PB5<7>, + + PG13<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + + PG11<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + PG12<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + + PG11<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + PG12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + PG10<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + PG9<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PA15<3>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB0<7>, + + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PA6<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + PD12<7>, + ], + + for [ + PA6<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PB11<7>, + + PC5<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PB10<7>, + + PC4<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart4 { + use super::*; + + pin! { + for [ + PB7<8>, + ], + + for [ + PA15<8>, + ], + + for [ + PA15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + PC11<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + PC10<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod uart5 { + use super::*; + + pin! { + for [ + PB5<8>, + ], + + for [ + PB4<8>, + ], + + for [ + PB4<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PD2<8>, + ], + + default:PushPull for no:NoPin, [ + PC12<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } +} + +pub mod usb { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA13<10>, + + PC9<10>, + ], + } +} diff --git a/src/gpio/alt/u5.rs b/src/gpio/alt/u5.rs new file mode 100644 index 00000000..09bf4b1d --- /dev/null +++ b/src/gpio/alt/u5.rs @@ -0,0 +1,3545 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +/*pub mod adf1 { + use super::*; + + pin! { + for [ + PB3<3>, + + PE9<3>, + + #[cfg(feature = "gpio-u59x")] + PF3<3>, + ], + + for [ + PC10<3>, + ], + + for [ + PB4<3>, + + PC11<3>, + + PE10<3>, + + #[cfg(feature = "gpio-u59x")] + PF4<3>, + ], + } +}*/ + +pub mod comp1 { + use super::*; + + pin! { + for [ + PB0<12>, + + PB10<12>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PB5<12>, + + PB11<12>, + ], + } +} + +/*pub mod crs { + use super::*; + + pin! { + for [ + PA10<0>, + + PB3<10>, + ], + } +}*/ + +pub mod dcmi { + use super::*; + + pin! { + for [ + PA9<5>, + + PC6<10>, + + PH9<10>, + ], + + for [ + PA10<5>, + + PC7<10>, + + PH10<10>, + ], + + for [ + PB5<10>, + + PD6<4>, + + PI3<10>, + ], + + for [ + PD2<10>, + + PF10<10>, + + PH15<10>, + ], + + for [ + PB4<10>, + + PF6<4>, + + PF11<10>, + ], + + for [ + PG15<10>, + + PI0<10>, + ], + + for [ + PC8<10>, + + PC11<4>, + + PE0<10>, + + PH11<10>, + ], + + for [ + PC9<4>, + + PE1<10>, + + PH12<10>, + ], + + for [ + PC11<10>, + + PE4<10>, + + PH14<10>, + ], + + for [ + PB6<10>, + + PD3<4>, + + PI4<10>, + ], + + for [ + PB8<10>, + + PE5<10>, + + PI6<10>, + ], + + for [ + PB9<10>, + + PE6<10>, + + PI7<10>, + ], + + for [ + PC10<10>, + + PH6<10>, + + PI1<10>, + ], + + for [ + PC12<10>, + + PH7<10>, + + PI2<10>, + ], + + for [ + PA4<10>, + + PD8<10>, + + PH8<10>, + ], + + for [ + PA6<4>, + + PD9<10>, + + PH5<10>, + ], + + for [ + PB7<10>, + + PI5<10>, + ], + } +} + +pub mod debug { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + PA8<12>, + + PE2<0>, + ], + + for [ + PC1<0>, + + PC9<0>, + + PE3<0>, + ], + + for [ + PC10<0>, + + PE4<0>, + ], + + for [ + PD2<0>, + + PE5<0>, + ], + + for [ + PC12<0>, + + PE6<0>, + ], + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod dsihost { + use super::*; + + pin! { + for [ + PF10<11>, + + PF11<11>, + + PG5<11>, + ], + } +} + +pub mod fdcan1 { + use super::*; + + pin! { + for [ + PA11<9>, + + PB8<9>, + + PD0<9>, + + PF7<9>, + + PH14<9>, + ], + + for [ + PA12<9>, + + PB9<9>, + + PD1<9>, + + PF8<9>, + + PH13<9>, + ], + } +} + +pub mod fmc { + use super::*; + + pin! { + for [ + PF0<12, Speed::VeryHigh>, + ], + + for [ + PF1<12, Speed::VeryHigh>, + ], + + for [ + PG0<12, Speed::VeryHigh>, + ], + + for [ + PG1<12, Speed::VeryHigh>, + ], + + for [ + PG2<12, Speed::VeryHigh>, + ], + + for [ + PG3<12, Speed::VeryHigh>, + ], + + for [ + PG4<12, Speed::VeryHigh>, + ], + + for [ + PG5<12, Speed::VeryHigh>, + ], + + for [ + PD11<12, Speed::VeryHigh>, + ], + + for [ + PD12<12, Speed::VeryHigh>, + ], + + for [ + PD13<12, Speed::VeryHigh>, + ], + + for [ + PE3<12, Speed::VeryHigh>, + ], + + for [ + PF2<12, Speed::VeryHigh>, + ], + + for [ + PE4<12, Speed::VeryHigh>, + ], + + for [ + PE5<12, Speed::VeryHigh>, + ], + + for [ + PE6<12, Speed::VeryHigh>, + ], + + for [ + PE2<12, Speed::VeryHigh>, + ], + + for [ + PG13<12, Speed::VeryHigh>, + ], + + for [ + PG14<12, Speed::VeryHigh>, + ], + + for [ + PF3<12, Speed::VeryHigh>, + ], + + for [ + PF4<12, Speed::VeryHigh>, + ], + + for [ + PF5<12, Speed::VeryHigh>, + ], + + for [ + PF12<12, Speed::VeryHigh>, + ], + + for [ + PF13<12, Speed::VeryHigh>, + ], + + for [ + PF14<12, Speed::VeryHigh>, + ], + + for [ + PF15<12, Speed::VeryHigh>, + ], + + for [ + PD3<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PD14<12, Speed::VeryHigh>, + ], + + for [ + PD15<12, Speed::VeryHigh>, + ], + + for [ + PE13<12, Speed::VeryHigh>, + ], + + for [ + PE14<12, Speed::VeryHigh>, + ], + + for [ + PE15<12, Speed::VeryHigh>, + ], + + for [ + PD8<12, Speed::VeryHigh>, + ], + + for [ + PD9<12, Speed::VeryHigh>, + ], + + for [ + PD10<12, Speed::VeryHigh>, + ], + + for [ + PD0<12, Speed::VeryHigh>, + ], + + for [ + PD1<12, Speed::VeryHigh>, + ], + + for [ + PE7<12, Speed::VeryHigh>, + ], + + for [ + PE8<12, Speed::VeryHigh>, + ], + + for [ + PE9<12, Speed::VeryHigh>, + ], + + for [ + PE10<12, Speed::VeryHigh>, + ], + + for [ + PE11<12, Speed::VeryHigh>, + ], + + for [ + PE12<12, Speed::VeryHigh>, + ], + + for [ + PG7<12, Speed::VeryHigh>, + ], + + for [ + PE0<12, Speed::VeryHigh>, + ], + + for [ + PB15<11, Speed::VeryHigh>, + + PE1<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + + PG9<12, Speed::VeryHigh>, + ], + + for [ + PD7<12, Speed::VeryHigh>, + ], + + for [ + PG9<12, Speed::VeryHigh>, + ], + + for [ + PG10<12, Speed::VeryHigh>, + ], + + for [ + PG12<12, Speed::VeryHigh>, + ], + + for [ + PB7<12, Speed::VeryHigh>, + ], + + for [ + PD4<12, Speed::VeryHigh>, + ], + + for [ + PD6<12, Speed::VeryHigh>, + ], + + for [ + PD5<12, Speed::VeryHigh>, + ], + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod hspi1 { + use super::*; + + pin! { + for [ + PI3<8>, + ], + + for [ + PI2<8>, + ], + + for [ + PI8<8>, + ], + + for [ + PH10<8>, + ], + + for [ + PH11<8>, + ], + + for [ + PI11<8>, + ], + + for [ + PI12<8>, + ], + + for [ + PI13<8>, + ], + + for [ + PI14<8>, + ], + + for [ + PI15<8>, + ], + + for [ + PJ0<8>, + ], + + for [ + PH12<8>, + ], + + for [ + PH13<8>, + ], + + for [ + PH14<8>, + ], + + for [ + PH15<8>, + ], + + for [ + PI0<8>, + ], + + for [ + PI1<8>, + ], + + for [ + PI9<8>, + ], + + for [ + PI10<8>, + ], + + for [ + PI4<8>, + ], + + for [ + PH9<8>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PB6<4>, + + PB8<4>, + + PG14<4>, + ], + + for [ + PB3<4>, + + PB7<4>, + + PB9<4>, + + PG13<4>, + ], + + for [ + PA1<4>, + + PA14<4>, + + PB5<4>, + + PG15<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PB10<4>, + + PB13<4>, + + PF1<4>, + + PH4<4>, + ], + + for [ + PB11<4>, + + PB14<4>, + + PF0<4>, + + PH5<4>, + ], + + for [ + PB12<4>, + + PF2<4>, + + PH6<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA7<4>, + + PC0<4>, + + PG7<4>, + + PH7<4>, + ], + + for [ + PB4<4>, + + PC1<4>, + + PG8<4>, + + PH8<4>, + ], + + for [ + PB2<4>, + + PG6<4>, + + PH9<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c4 { + use super::*; + + pin! { + for [ + PB6<5>, + + PB10<3>, + + PD12<4>, + + PF14<4>, + ], + + for [ + PB7<5>, + + PB11<3>, + + PD13<4>, + + PF15<4>, + ], + + for [ + PA14<5>, + + PD11<4>, + + PF13<4>, + ], + } + use crate::pac::I2C4 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod i2c5 { + use super::*; + + pin! { + for [ + PD1<4>, + + PH5<2>, + + PJ2<4>, + ], + + for [ + PD0<4>, + + PH4<2>, + + PJ1<4>, + ], + + for [ + PD2<4>, + + PD10<4>, + + PH6<2>, + + PJ0<4>, + ], + } + use crate::pac::I2C5 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod i2c6 { + use super::*; + + pin! { + for [ + PD1<2>, + + PF1<2>, + + PJ10<2>, + ], + + for [ + PD0<2>, + + PF0<2>, + + PJ9<2>, + ], + + for [ + PB12<2>, + + PC4<2>, + + PD3<2>, + + PJ8<2>, + ], + } + use crate::pac::I2C6 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<1>, + + PB9<1>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PA14<1>, + + PB2<1>, + + PB3<2>, + + PC1<1>, + + PG15<1>, + ], + + for [ + PA1<0>, + + PB4<1>, + + PG14<1>, + ], + + for [ + PB6<1>, + + PC3<1>, + + PG12<1>, + ], + + for [ + PB5<1>, + + PC0<1>, + + PG10<1>, + ], + + for [ + PB7<1>, + + PC2<1>, + + PG11<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA4<14>, + + PA8<14>, + + PD13<14>, + ], + + for [ + PA7<13>, + + PC7<14>, + + PD10<2>, + ], + + for [ + PA5<14>, + + PC3<14>, + + PD11<14>, + ], + + for [ + PB1<14>, + + PC0<14>, + + PD12<14>, + ], + + for [ + PA10<2>, + + PB15<2>, + + PD9<2>, + ], + } +} + +pub mod lptim3 { + use super::*; + + pin! { + for [ + PB0<4>, + + PB10<2>, + + PC3<2>, + + PC8<14>, + + PD14<14>, + + PF5<2>, + ], + + for [ + PB1<4>, + + PC9<14>, + + PD15<14>, + + PF2<2>, + ], + + for [ + PB14<2>, + + PC10<2>, + + PD10<14>, + + PF4<2>, + ], + + for [ + PB13<2>, + + PC11<2>, + + PD9<14>, + + PF3<2>, + ], + } +} + +pub mod lptim4 { + use super::*; + + pin! { + for [ + PD2<13>, + + PF12<13>, + ], + + for [ + PD13<13>, + + PF11<13>, + ], + + default:PushPull for [ + PD7<13>, + + PF13<13>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<8>, + + PB13<8>, + + PG5<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + + PG6<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + + PG6<8>, + ], + + for [ + PA3<8>, + + PB10<8>, + + PC0<8>, + + PG8<8>, + ], + } + + pin! { + default:PushPull for [ + PA2<8>, + + PB11<8>, + + PC1<8>, + + PG7<8>, + ], + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod ltdc { + use super::*; + + pin! { + for [ + PE4<8>, + + PF12<8>, + ], + + for [ + PB2<8>, + + PB8<7>, + + PF13<8>, + ], + + for [ + PD14<8>, + ], + + for [ + PD15<8>, + ], + + for [ + PD0<8>, + ], + + for [ + PD1<8>, + ], + + for [ + PE7<8>, + ], + + for [ + PE8<8>, + ], + + for [ + PD3<8>, + ], + + for [ + PD6<8>, + + PF11<8>, + ], + + for [ + PE5<8>, + + PF14<8>, + ], + + for [ + PE6<8>, + + PF15<8>, + ], + + for [ + PE9<8>, + ], + + for [ + PE10<8>, + ], + + for [ + PE11<8>, + ], + + for [ + PE12<8>, + ], + + for [ + PE13<8>, + ], + + for [ + PE14<8>, + ], + + for [ + PE0<8>, + ], + + for [ + PC6<7>, + + PE2<8>, + + PG13<8>, + ], + + for [ + PC7<7>, + + PE3<8>, + + PG6<7>, + + PG14<8>, + ], + + for [ + PE15<8>, + ], + + for [ + PD8<8>, + ], + + for [ + PD9<8>, + ], + + for [ + PD10<8>, + ], + + for [ + PD11<8>, + ], + + for [ + PD12<8>, + ], + + for [ + PD13<8>, + + PE1<8>, + ], + } +} + +pub mod mdf1 { + use super::*; + + pin! { + for [ + PB8<5>, + + PE9<6>, + + #[cfg(feature = "gpio-u59x")] + PF3<6>, + + PG7<6>, + ], + + for [ + PC2<6>, + + PF10<6>, + ], + + for [ + PB2<6>, + + PD4<6>, + + #[cfg(feature = "gpio-u59x")] + PF5<6>, + ], + + for [ + PB13<6>, + + PD7<6>, + ], + + for [ + PB15<6>, + + PE8<6>, + ], + + for [ + PC6<6>, + + PE5<6>, + ], + + for [ + PC1<6>, + + PE11<6>, + ], + + for [ + PB7<6>, + + PE13<6>, + ], + + for [ + PB1<6>, + + PD3<6>, + + #[cfg(feature = "gpio-u59x")] + PF4<6>, + ], + + for [ + PB12<6>, + + PD6<6>, + ], + + for [ + PB14<6>, + + PE7<6>, + ], + + for [ + PC7<6>, + + PE4<6>, + ], + + for [ + PC0<6>, + + PE10<6>, + ], + + for [ + PB6<6>, + + PE12<6>, + ], + } +} + +pub mod octospim { + use super::*; + + pin! { + for [ // High speed + PA3<10>, + + PB10<10>, + + PE10<10>, + + PF10<3>, + ], + + for [ + PA1<10>, + + PB2<10>, + + PE3<3>, + + PG6<3>, + ], + + for [ + PB1<10>, + + PE12<10>, + + PF8<10>, + ], + + for [ + PB0<10>, + + PE13<10>, + + PF9<10>, + ], + + for [ + PA7<10>, + + PE14<10>, + + PF7<10>, + ], + + for [ + PA6<10>, + + PE15<10>, + + PF6<10>, + ], + + for [ + PC1<10>, + + PD4<10>, + + PH2<3>, + ], + + for [ + PC2<10>, + + PD5<10>, + + PG11<3>, + + PI0<3>, + ], + + for [ + PC3<10>, + + PD6<10>, + ], + + for [ + PC0<3>, + + PC4<10>, + + PD7<10>, + ], + + for [ + PB5<3>, + + PB12<10>, + + PE9<10>, + + PF11<3>, + ], + + for [ + PA2<10>, + + PA4<3>, + + PB11<10>, + + PC11<5>, + + PE11<10>, + ], + + for [ + PF4<5>, + + PH6<5>, + + PI6<5>, + ], + + for [ + PF12<5>, + + PG7<5>, + + PG15<5>, + + PH4<5>, + ], + + for [ + PF0<5>, + + PI3<6>, + ], + + for [ + PF1<5>, + + PI2<6>, + ], + + for [ + PF2<5>, + + PI1<6>, + ], + + for [ + PF3<5>, + + PH8<5>, + ], + + for [ + PG0<5>, + + PH9<5>, + ], + + for [ + PG1<5>, + + PH10<5>, + ], + + for [ + PG9<5>, + + PH11<5>, + + PH15<5>, + ], + + for [ + PG10<5>, + + PH12<5>, + ], + + for [ + PF5<5>, + + PH7<5>, + + PI7<5>, + ], + + for [ + PA0<10>, + + PA12<6>, + + PD3<10>, + + PF6<5>, + + PG12<5>, + + PI5<5>, + ], + } +} + +pub mod pssi { + use super::*; + + pin! { + for [ + PA9<5>, + + PC6<10>, + + PH9<10>, + ], + + for [ + PA10<5>, + + PC7<10>, + + PH10<10>, + ], + + for [ + PB5<10>, + + PD6<4>, + + PI3<10>, + ], + + for [ + PD2<10>, + + PF10<10>, + + PH15<10>, + ], + + for [ + PB4<10>, + + PF6<4>, + + PF11<10>, + ], + + for [ + PG15<10>, + + PI0<10>, + ], + + for [ + PA5<4>, + + PF8<4>, + + PH4<10>, + ], + + for [ + PC5<4>, + + PF9<4>, + + PF10<4>, + ], + + for [ + PC8<10>, + + PC11<4>, + + PE0<10>, + + PH11<10>, + ], + + for [ + PC9<4>, + + PE1<10>, + + PH12<10>, + ], + + for [ + PC11<10>, + + PE4<10>, + + PH14<10>, + ], + + for [ + PB6<10>, + + PD3<4>, + + PI4<10>, + ], + + for [ + PB8<10>, + + PE5<10>, + + PI6<10>, + ], + + for [ + PB9<10>, + + PE6<10>, + + PI7<10>, + ], + + for [ + PC10<10>, + + PH6<10>, + + PI1<10>, + ], + + for [ + PC12<10>, + + PH7<10>, + + PI2<10>, + ], + + for [ + PA4<10>, + + PD8<10>, + + PH8<10>, + ], + + for [ + PA6<4>, + + PD9<10>, + + PH5<10>, + ], + + for [ + PB7<10>, + + PI5<10>, + ], + } +} + +pub mod pwr { + use super::*; + + pin! { + for [ + PA6<0>, + + PC7<0>, + ], + + for [ + PA5<0>, + + PC6<0>, + ], + + for [ + PA7<0>, + + PC8<0>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA8<0>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PB15<0>, + ], + } +} + +pub mod sai1 { + use super::*; + + pin! { + for [ + PA3<3>, + + PB8<3>, + + PE2<3>, + + PG7<3>, + ], + + for [ + PA8<3>, + + PE5<3>, + ], + + for [ + PA10<3>, + + PC3<3>, + + PD6<3>, + + PE6<3>, + ], + + for [ + PB9<3>, + + PE4<3>, + ], + + for [ + PC5<3>, + + PF10<13>, + ], + + for [ + PA9<13>, + + PB9<13>, + + PE4<13>, + ], + + for [ + PA4<13>, + + PA14<13>, + + PB6<13>, + + PE9<13>, + + PF9<13>, + ], + + for no:NoPin, [ + PA3<13>, + + PB8<13>, + + PE2<13>, + + PG7<13>, + ], + + for no:NoPin, [ + PB4<13>, + + PE10<13>, + + PF7<13>, + ], + + for [ + PA8<13>, + + PB10<13>, + + PE5<13>, + ], + + for [ + PB3<13>, + + PE8<13>, + + PF8<13>, + ], + + for [ + PA10<13>, + + PC1<13>, + + PC3<13>, + + PD6<13>, + + PE6<13>, + ], + + for [ + PA13<13>, + + PB5<13>, + + PE3<13>, + + PE7<13>, + + PF6<13>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sai2 { + use super::*; + + pin! { + for [ + PB12<13>, + + PC0<13>, + + PD12<13>, + + PG10<13>, + ], + + for [ + PA15<13>, + + PG3<13>, + ], + + for no:NoPin, [ + PB14<13>, + + PC6<13>, + + PD9<13>, + + PG11<13>, + ], + + for no:NoPin, [ + PC7<13>, + + PC11<13>, + + PG4<13>, + ], + + for [ + PB13<13>, + + PD10<13>, + + PG9<13>, + ], + + for [ + PC10<13>, + + PG2<13>, + ], + + for [ + PB15<13>, + + PD11<13>, + + PG12<13>, + ], + + for [ + PC12<13>, + + PG5<13>, + ], + } + use crate::pac::SAI2 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod sdmmc1 { + use super::*; + + pin! { + for [ + PB9<8>, + ], + + for [ + PC12<12>, + ], + + for [ + PB8<8>, + ], + + for [ + PD2<12>, + ], + + for [ + PC8<12>, + ], + + for [ + PC6<8>, + ], + + for [ + PC9<12>, + ], + + for [ + PC7<8>, + ], + + for [ + PC10<12>, + ], + + for [ + PC11<12>, + ], + + for [ + PB8<12>, + ], + + for [ + PB9<12>, + + PC0<12>, + ], + + for [ + PC6<12>, + ], + + for [ + PC7<12>, + ], + } +} + +pub mod sdmmc2 { + use super::*; + + pin! { + for [ + PC1<12>, + + PD6<11>, + ], + + for [ + PA0<12>, + + PD7<11>, + ], + + for [ + PB14<12>, + ], + + for [ + PB15<12>, + ], + + for [ + PB3<12>, + ], + + for [ + PB4<12>, + ], + + for [ + PB8<11>, + ], + + for [ + PB9<11>, + ], + + for [ + PC6<11>, + ], + + for [ + PC7<11>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PA11<5>, + + PB4<5>, + + PE14<5>, + + PG3<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PA12<5>, + + PB5<5>, + + PE15<5>, + + PG4<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PB0<5>, + + PE12<5>, + + PG5<5>, + ], + + for [ + PA2<5>, + + PA8<5>, + + PB2<5>, + + PE11<5>, + + PG6<5>, + ], + + for no:NoPin, [ + PA1<5>, + + PA5<5>, + + PB3<5>, + + PE13<5>, + + PG2<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + PD3<5>, + + PI2<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC1<3>, + + PC3<5>, + + PD4<5>, + + PI3<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + PD0<5>, + + PI0<5>, + ], + + for [ + PB11<5>, + + PC0<5>, + + PD5<5>, + + PI4<5>, + ], + + for no:NoPin, [ + PA9<3>, + + PB10<5>, + + PB13<5>, + + PD1<5>, + + PD3<3>, + + PI1<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi3 { + use super::*; + + pin! { + for no:NoPin, [ + PB4<6>, + + PC11<6>, + + PG10<6>, + ], + + for no:NoPin, [ + PB5<6>, + + PC12<6>, + + PD6<5>, + + PG11<6>, + ], + + for [ + PA4<6>, + + PA15<6>, + + PG12<6>, + ], + + for [ + PA0<6>, + + PB8<6>, + + PG13<6>, + ], + + for no:NoPin, [ + PB3<6>, + + PC10<6>, + + PG9<6>, + ], + } + impl SpiCommon for crate::pac::SPI3 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + PE9<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + + PE8<1>, + ], + + default:PushPull for [ + PA9<1>, + + PE11<1>, + ], + + default:PushPull for [ + PB0<1>, + + PB14<1>, + + PE10<1>, + ], + + default:PushPull for [ + PA10<1>, + + PE13<1>, + ], + + default:PushPull for [ + PB1<1>, + + PB15<1>, + + PE12<1>, + ], + + default:PushPull for [ + PA11<1>, + + PE14<1>, + ], + + default:PushPull for [ + PC5<1>, + + PE15<3>, + ], + } + + pin! { + for [ + PA6<1>, + + PB12<1>, + + PE15<1>, + ], + + for [ + PA11<2>, + + PE14<2>, + ], + + for [ + PA12<1>, + + PE7<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimNCPin<3> for TIM { + type ChN = Ch4N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim3 { + use super::*; + + pin! { + default:PushPull for [ + PA6<2>, + + PB4<2>, + + PC6<2>, + + PE3<2>, + ], + + default:PushPull for [ + PA7<2>, + + PB5<2>, + + PC7<2>, + + PE4<2>, + ], + + default:PushPull for [ + PB0<2>, + + PC8<2>, + + PE5<2>, + ], + + default:PushPull for [ + PB1<2>, + + PC9<2>, + + PE6<2>, + ], + } + + pin! { + for [ + PD2<2>, + + PE2<2>, + ], + } + + use crate::pac::TIM3 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim4 { + use super::*; + + pin! { + default:PushPull for [ + PB6<2>, + + PD12<2>, + ], + + default:PushPull for [ + PB7<2>, + + PD13<2>, + ], + + default:PushPull for [ + PB8<2>, + + PD14<2>, + ], + + default:PushPull for [ + PB9<2>, + + PD15<2>, + ], + } + + pin! { + for [ + PE0<2>, + ], + } + + use crate::pac::TIM4 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim5 { + use super::*; + + pin! { + default:PushPull for [ + PA0<2>, + + PF6<2>, + + PH10<2>, + ], + + default:PushPull for [ + PA1<2>, + + PF7<2>, + + PH11<2>, + ], + + default:PushPull for [ + PA2<2>, + + PF8<2>, + + PH12<2>, + ], + + default:PushPull for [ + PA3<2>, + + PF9<2>, + + PI0<2>, + ], + } + + pin! { + for [ + PF6<1>, + ], + } + + use crate::pac::TIM5 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim8 { + use super::*; + + pin! { + default:PushPull for [ + PC6<3>, + + PI5<3>, + ], + + default:PushPull for [ + PA5<3>, + + PA7<3>, + + PH13<3>, + ], + + default:PushPull for [ + PC7<3>, + + PI6<3>, + ], + + default:PushPull for [ + PB0<3>, + + PB14<3>, + + PH14<3>, + ], + + default:PushPull for [ + PC8<3>, + + PI7<3>, + ], + + default:PushPull for [ + PB1<3>, + + PB15<3>, + + PH15<3>, + ], + + default:PushPull for [ + PC9<3>, + + PI2<3>, + ], + + default:PushPull for [ + PB2<3>, + + PD0<3>, + + PH12<3>, + ], + } + + pin! { + for [ + PA6<3>, + + PB7<3>, + + PI4<3>, + ], + + for [ + PB6<3>, + + PC9<1>, + ], + + for [ + PA0<3>, + + PI3<3>, + ], + } + + use crate::pac::TIM8 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimNCPin<3> for TIM { + type ChN = Ch4N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim15 { + use super::*; + + pin! { + default:PushPull for [ + PA2<14>, + + PB14<14>, + + PF9<14>, + + PG10<14>, + ], + + default:PushPull for [ + PA1<14>, + + PB13<14>, + + PG9<14>, + ], + + default:PushPull for [ + PA3<14>, + + PB15<14>, + + PF10<14>, + + PG11<14>, + ], + } + + pin! { + for [ + PA9<14>, + + PB12<14>, + ], + } + + use crate::pac::TIM15 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<14>, + + PB8<14>, + + PE0<14>, + ], + + default:PushPull for [ + PB6<14>, + ], + } + + pin! { + for [ + PB5<14>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<14>, + + PB9<14>, + + PE1<14>, + ], + + default:PushPull for [ + PB7<14>, + ], + } + + pin! { + for [ + PA10<14>, + + PB4<14>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tsc { + use super::*; + + pin! { + for [ + PB10<9>, + + PD2<9>, + ], + } + + pin! { + default:PushPull for [ + PB12<9>, + ], + + default:PushPull for [ + PB13<9>, + ], + + default:PushPull for [ + PB14<9>, + ], + + default:PushPull for [ + PC3<9>, + ], + + default:PushPull for [ + PB4<9>, + ], + + default:PushPull for [ + PB5<9>, + ], + + default:PushPull for [ + PB6<9>, + ], + + default:PushPull for [ + PB7<9>, + ], + + default:PushPull for [ + PC2<9>, + ], + + default:PushPull for [ + PC10<9>, + ], + + default:PushPull for [ + PC11<9>, + ], + + default:PushPull for [ + PC12<9>, + ], + + default:PushPull for [ + PC6<9>, + ], + + default:PushPull for [ + PC7<9>, + ], + + default:PushPull for [ + PC8<9>, + ], + + default:PushPull for [ + PC9<9>, + ], + + default:PushPull for [ + PE10<9>, + ], + + default:PushPull for [ + PE11<9>, + ], + + default:PushPull for [ + PE12<9>, + ], + + default:PushPull for [ + PE13<9>, + ], + + default:PushPull for [ + PD10<9>, + ], + + default:PushPull for [ + PD11<9>, + ], + + default:PushPull for [ + PD12<9>, + ], + + default:PushPull for [ + PD13<9>, + ], + + default:PushPull for [ + PE2<9>, + ], + + default:PushPull for [ + PE3<9>, + ], + + default:PushPull for [ + PE4<9>, + ], + + default:PushPull for [ + PE5<9>, + ], + + default:PushPull for [ + PF14<9>, + ], + + default:PushPull for [ + PF15<9>, + ], + + default:PushPull for [ + PG0<9>, + ], + + default:PushPull for [ + PG1<9>, + ], + } +} + +pub mod ucpd1 { + use super::*; + + pin! { + for [ + PA2<11>, + + PB2<11>, + + PG6<11>, + ], + + for [ + PC11<11>, + + PF13<11>, + + PG7<11>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + + PB5<7>, + + PG13<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + + PG11<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + PG12<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + + PG12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + + PG10<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + + PG9<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + + PD7<7>, + ], + + for [ + PA0<7>, + + PD3<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + + for [ + PA1<7>, + + PD4<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + + PA15<3>, + + PD6<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + + PD5<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart3 { + use super::*; + + pin! { + for [ + PB0<7>, + + PB12<7>, + + PC12<7>, + + PD10<7>, + ], + + for [ + PA6<7>, + + PB13<7>, + + PD11<7>, + ], + + for [ + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + PD12<7>, + ], + + for [ + PA15<7>, + + PB1<7>, + + PB14<7>, + + PD2<7>, + + PD12<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA5<7>, + + PB11<7>, + + PC5<7>, + + PC11<7>, + + PD9<7>, + ], + + default:PushPull for no:NoPin, [ + PA7<7>, + + PB10<7>, + + PC4<7>, + + PC10<7>, + + PD8<7>, + ], + } + use crate::pac::USART3 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart4 { + use super::*; + + pin! { + for [ + PB7<8>, + ], + + for [ + PA15<8>, + ], + + for [ + PA15<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA1<8>, + + PC11<8>, + ], + + default:PushPull for no:NoPin, [ + PA0<8>, + + PC10<8>, + ], + } + use crate::pac::UART4 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod uart5 { + use super::*; + + pin! { + for [ + PB5<8>, + ], + + for [ + PB4<8>, + ], + + for [ + PB4<8>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PD2<8>, + + #[cfg(feature = "gpio-u59x")] + PF4<8>, + ], + + default:PushPull for no:NoPin, [ + PC12<8>, + + #[cfg(feature = "gpio-u59x")] + PF3<8>, + ], + } + use crate::pac::UART5 as UART; + impl SerialAsync for UART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialFlowControl for UART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod usart6 { + use super::*; + + pin! { + for [ + PC1<7>, + + PD14<7>, + + PE2<7>, + + PF2<7>, + + PJ6<7>, + ], + + for [ + PC0<7>, + + PD13<7>, + + PE3<7>, + + PF3<7>, + + PJ7<7>, + ], + + for [ + PD15<7>, + + PE4<7>, + + PF4<7>, + + PJ5<7>, + ], + + for [ + PD15<7>, + + PE4<7>, + + PF4<7>, + + PJ5<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PC2<7>, + + PC8<7>, + + PE0<7>, + + PF1<7>, + + PJ4<7>, + ], + + default:PushPull for no:NoPin, [ + PC3<7>, + + PC9<7>, + + PE1<7>, + + PF0<7>, + + PJ3<7>, + ], + } + use crate::pac::USART6 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(feature = "gpio-u5x")] +pub mod otg_fs { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA10<10>, + ], + + for [ + PA13<10>, + + PC9<10>, + ], + + for [ + PA8<10>, + + PA14<10>, + ], + } +} + +#[cfg(feature = "gpio-u59x")] +pub mod otg_hs { + use super::*; + + pin! { + for [ + PA10<10>, + ], + + for [ + PA8<10>, + + PA14<10>, + ], + } +} diff --git a/src/gpio/alt/wb.rs b/src/gpio/alt/wb.rs new file mode 100644 index 00000000..7f7e9732 --- /dev/null +++ b/src/gpio/alt/wb.rs @@ -0,0 +1,1639 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +/*pub mod cm4 { + use super::*; + + pin! { + for [ + PA0<15>, + + PA1<15>, + + PA2<15>, + + PA3<15>, + + PA4<15>, + + PA5<15>, + + PA6<15>, + + PA7<15>, + + PA8<15>, + + PA9<15>, + + PA10<15>, + + PA11<15>, + + PA12<15>, + + PA13<15>, + + PA14<15>, + + PA15<15>, + + PB0<15>, + + PB1<15>, + + PB2<15>, + + PB3<15>, + + PB4<15>, + + PB5<15>, + + PB6<15>, + + PB7<15>, + + PB8<15>, + + PB9<15>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB11<15>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB12<15>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB13<15>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB14<15>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB15<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC0<15>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC1<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC2<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC3<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC4<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC5<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC6<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC7<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC8<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC9<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC10<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC11<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC12<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC13<15>, + + PC14<15>, + + PC15<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD0<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD1<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD2<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD3<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD4<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD5<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD6<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD7<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD8<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD9<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD10<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD11<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD12<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD13<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD14<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD15<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE0<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE1<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE2<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE3<15>, + + PE4<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PH0<15>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PH1<15>, + + PH3<15>, + ], + } +}*/ + +pub mod comp1 { + use super::*; + + pin! { + for [ + PA0<12>, + + PB0<12>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<12>, + ], + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod comp2 { + use super::*; + + pin! { + for [ + PA2<12>, + + PA7<12>, + + PB5<12>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB11<12>, + ], + } +} + +/*#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod crs { + use super::*; + + pin! { + for [ + PA10<10>, + ], + } +}*/ + +/*#[cfg(feature = "gpio-wb3x")] +pub mod ext { + use super::*; + + pin! { + for [ + PB0<6>, + ], + } +}*/ + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PA9<4>, + + PB6<4>, + + PB8<4>, + ], + + for [ + PA10<4>, + + PB7<4>, + + PB9<4>, + ], + + for [ + PA1<4>, + + PA14<4>, + + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA7<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB13<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC0<4>, + ], + + for [ + PB4<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB11<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB14<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC1<4>, + ], + + for [ + PB2<4>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB12<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<8>, + + PB9<8>, + ], + } +} + +#[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod lcd { + use super::*; + + pin! { + for [ + PA8<11>, + ], + + for [ + PA9<11>, + ], + + for [ + PA10<11>, + ], + + for [ + PB9<11>, + ], + + for [ + PC10<11>, + ], + + for [ + PC11<11>, + ], + + for [ + PC12<11>, + ], + + for [ + PD2<11>, + ], + + for [ + PA1<11>, + ], + + for [ + PA2<11>, + ], + + for [ + PB10<11>, + ], + + for [ + PB11<11>, + ], + + for [ + PB12<11>, + ], + + for [ + PB13<11>, + ], + + for [ + PB14<11>, + ], + + for [ + PB15<11>, + ], + + for [ + PB8<11>, + ], + + for [ + PA15<11>, + ], + + for [ + PC0<11>, + ], + + for [ + PC1<11>, + ], + + for [ + PA3<11>, + ], + + for [ + PC2<11>, + ], + + for [ + PB7<11>, + ], + + for [ + PC4<11>, + ], + + for [ + PC5<11>, + ], + + for [ + PC6<11>, + ], + + for [ + PC7<11>, + ], + + for [ + PC8<11>, + ], + + for [ + PC9<11>, + ], + + for [ + PC10<11>, + + PD8<11>, + ], + + for [ + PC11<11>, + + PD9<11>, + ], + + for [ + PA6<11>, + ], + + for [ + PC12<11>, + + PD10<11>, + ], + + for [ + PD2<11>, + + PD11<11>, + ], + + for [ + PD12<11>, + ], + + for [ + PD13<11>, + ], + + for [ + PD14<11>, + ], + + for [ + PD15<11>, + ], + + for [ + PE0<11>, + ], + + for [ + PE1<11>, + ], + + for [ + PE2<11>, + ], + + for [ + PD7<11>, + ], + + for [ + PA7<11>, + ], + + for [ + PC10<11>, + ], + + for [ + PC11<11>, + ], + + for [ + PC12<11>, + ], + + for [ + PD2<11>, + ], + + for [ + PA4<11>, + + PA14<11>, + ], + + for [ + PB6<11>, + ], + + for [ + PB3<11>, + ], + + for [ + PB4<11>, + ], + + for [ + PB5<11>, + ], + + for [ + PB2<11>, + + PC3<11>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC3<1>, + ], + + for [ + PB5<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC0<1>, + ], + + for [ + PB7<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC2<1>, + ], + + default:PushPull for [ + PA14<1>, + + PB2<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC1<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA5<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC3<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD11<14>, + ], + + for [ + PB1<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC0<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD12<14>, + ], + + default:PushPull for [ + PA4<14>, + + PA8<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD13<14>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB13<8>, + ], + + for [ + PB1<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB12<8>, + ], + + for [ + PB1<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB12<8>, + ], + + for [ + PA3<8>, + + PA12<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC0<8>, + ], + } + + pin! { + default:PushPull for [ + PA2<8>, + + PB5<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB11<8>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC1<8>, + ], + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod quadspi { + use super::*; + + pin! { + for [ + PB9<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD4<10>, + ], + + for [ + PB8<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD5<10>, + ], + + for [ + PA7<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD6<10>, + ], + + for [ + PA6<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD7<10>, + ], + + for [ + PA2<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB11<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD3<10>, + ], + + for [ + PA3<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<10>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA2<0>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC12<6>, + + PH3<0>, + ], + + for [ + PA8<0>, + + #[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb3x", feature = "gpio-wb55x"))] + PA15<6>, + + PB6<0>, + ], + } +} + +#[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod rf { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-wb5mx")] + PC14<6>, + ], + + for [ + #[cfg(feature = "gpio-wb5mx")] + PC15<6>, + ], + + for [ + PB0<6>, + ], + } +} + +#[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod rtc { + use super::*; + + pin! { + for [ + #[cfg(feature = "gpio-wb35x")] + PB2<0>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB15<0>, + ], + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod sai1 { + use super::*; + + pin! { + for [ + PA3<3>, + + PB8<3>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE2<3>, + ], + + for [ + PA8<3>, + ], + + for [ + PA10<3>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC3<3>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD6<3>, + ], + + for [ + PA9<3>, + + PB9<3>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC5<3>, + ], + + for [ + #[cfg(feature = "gpio-wb3x")] + PA10<3>, + ], + + for [ + #[cfg(feature = "gpio-wb3x")] + PA9<3>, + + #[cfg(feature = "gpio-wb3x")] + PB9<3>, + ], + + for [ + PA0<13>, + + PB2<13>, + ], + + for [ + PA9<13>, + + PB9<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB12<13>, + ], + + for [ + PA4<13>, + + PA14<13>, + + PB6<13>, + ], + + for no:NoPin, [ + PA3<13>, + + PB8<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB14<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE2<13>, + ], + + for no:NoPin, [ + PB4<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD5<13>, + ], + + for [ + PA8<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB13<13>, + ], + + for [ + PB3<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC9<13>, + ], + + for [ + PA10<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB15<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC3<13>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD6<13>, + ], + + for [ + PA5<13>, + + PA13<13>, + + PB5<13>, + ], + } + use crate::pac::SAI1 as SAI; + use crate::sai::SAICH; + impl SaiChannels for SAI { + type A = SAICH; + type B = SAICH; + } + impl SaiChannel for SAICH { + type Fs = FsA; + type Mclk = MclkA; + type Sck = SckA; + type Sd = SdA; + } + impl SaiChannel for SAICH { + type Fs = FsB; + type Mclk = MclkB; + type Sck = SckB; + type Sd = SdB; + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PA11<5>, + + PB4<5>, + ], + + for no:NoPin, [ + #[cfg(feature = "gpio-wb35x")] + PA5<4>, + + PA7<5>, + + PA12<5>, + + #[cfg(feature = "gpio-wb35x")] + PA13<5>, + + PB5<5>, + ], + + for [ + PA4<5>, + + #[cfg(feature = "gpio-wb35x")] + PA14<5>, + + PA15<5>, + + PB2<5>, + + #[cfg(feature = "gpio-wb35x")] + PB6<5>, + ], + + for no:NoPin, [ + PA1<5>, + + PA5<5>, + + PB3<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +#[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PB14<5>, + + PC2<5>, + + PD3<5>, + ], + + for no:NoPin, [ + PB15<5>, + + PC1<3>, + + PC3<5>, + + PD4<5>, + ], + + for [ + PB9<5>, + + PB12<5>, + + PD0<5>, + ], + + for no:NoPin, [ + PA9<5>, + + PB10<5>, + + PB13<5>, + + PD1<5>, + + PD3<3>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PB4<0>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE2<0>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD9<0>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC10<0>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD2<0>, + ], + + for [ + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC12<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + + #[cfg(feature = "gpio-wb35x")] + PB14<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD14<1>, + ], + + default:PushPull for [ + PA7<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB13<1>, + ], + + default:PushPull for [ + PA9<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD15<1>, + ], + + default:PushPull for [ + PB8<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB14<1>, + ], + + default:PushPull for [ + PA10<1>, + + #[cfg(feature = "gpio-wb35x")] + PB7<12>, + ], + + default:PushPull for [ + PB9<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB15<1>, + ], + + default:PushPull for [ + PA11<1>, + ], + } + + pin! { + for [ + #[cfg(feature = "gpio-wb35x")] + PA6<1>, + + #[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PA6<12>, + + PB7<3>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB12<3>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC9<3>, + ], + + for [ + #[cfg(feature = "gpio-wb35x")] + PA11<2>, + + #[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PA11<12>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PD8<2>, + ], + + for [ + PA12<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE0<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + + #[cfg(feature = "gpio-wb35x")] + PB15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + + #[cfg(feature = "gpio-wb35x")] + PB12<1>, + ], + + default:PushPull for [ + PA2<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB10<1>, + + #[cfg(feature = "gpio-wb35x")] + PB13<1>, + ], + + default:PushPull for [ + PA3<1>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PB11<1>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<14>, + + PB8<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE0<14>, + ], + + default:PushPull for [ + PB6<14>, + ], + } + + pin! { + for [ + PB5<14>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<14>, + + PB9<14>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE1<14>, + ], + + default:PushPull for [ + PB7<14>, + ], + } + + pin! { + for [ + PA10<14>, + + PB4<14>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +/*#[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod trig { + use super::*; + + pin! { + for [ + PD10<0>, + ], + } +}*/ + +#[cfg(any(feature = "gpio-wb35x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod tsc { + use super::*; + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + pin! { + for [ + PB10<9>, + + PD2<9>, + ], + } + + pin! { + default:PushPull for [ + PB12<9>, + ], + + default:PushPull for [ + PB13<9>, + ], + + default:PushPull for [ + PB4<9>, + ], + + default:PushPull for [ + PB5<9>, + ], + + default:PushPull for [ + PB6<9>, + ], + + default:PushPull for [ + PB7<9>, + ], + + default:PushPull for [ + PA15<9>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-wb35x")] + PB10<9>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC10<9>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-wb35x")] + PC1<9>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC11<9>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-wb35x")] + PA13<9>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE2<9>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-wb35x")] + PA10<9>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE1<9>, + ], + + default:PushPull for [ + #[cfg(feature = "gpio-wb35x")] + PB8<9>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PE0<9>, + ], + + default:PushPull for [ + PB9<9>, + ], + } + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + pin! { + default:PushPull for [ + PB14<9>, + ], + + default:PushPull for [ + PB15<9>, + ], + + default:PushPull for [ + PC12<9>, + ], + + default:PushPull for [ + PC6<9>, + ], + + default:PushPull for [ + PC7<9>, + ], + + default:PushPull for [ + PC8<9>, + ], + + default:PushPull for [ + PC9<9>, + ], + + default:PushPull for [ + PD4<9>, + ], + + default:PushPull for [ + PD5<9>, + ], + + default:PushPull for [ + PD6<9>, + ], + + default:PushPull for [ + PD7<9>, + ], + + default:PushPull for [ + PD10<9>, + ], + + default:PushPull for [ + PD11<9>, + ], + + default:PushPull for [ + PD12<9>, + ], + + default:PushPull for [ + PD13<9>, + ], + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + + PB5<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +#[cfg(any(feature = "gpio-wb3x", feature = "gpio-wb55x", feature = "gpio-wb5mx"))] +pub mod usb { + use super::*; + + pin! { + for [ + PA11<10>, + ], + + for [ + PA12<10>, + ], + + for [ + PA13<10>, + + #[cfg(any(feature = "gpio-wb55x", feature = "gpio-wb5mx"))] + PC9<10>, + ], + } +} diff --git a/src/gpio/alt/wl.rs b/src/gpio/alt/wl.rs new file mode 100644 index 00000000..7ff1a1f9 --- /dev/null +++ b/src/gpio/alt/wl.rs @@ -0,0 +1,960 @@ +use super::*; +use crate::gpio::{self, NoPin, OpenDrain, PushPull}; + +/*pub mod cm4 { + use super::*; + + pin! { + for [ + PA0<15>, + + PA1<15>, + + PA2<15>, + + PA3<15>, + + PA4<15>, + + PA5<15>, + + PA6<15>, + + PA7<15>, + + PA8<15>, + + PA9<15>, + + PA10<15>, + + PA11<15>, + + PA12<15>, + + PA13<15>, + + PA14<15>, + + PA15<15>, + + PB0<15>, + + PB1<15>, + + PB2<15>, + + PB3<15>, + + PB4<15>, + + PB5<15>, + + PB6<15>, + + PB7<15>, + + PB8<15>, + + PB9<15>, + + PB10<15>, + + PB11<15>, + + PB12<15>, + + PB13<15>, + + PB14<15>, + + PB15<15>, + + PC0<15>, + + PC1<15>, + + PC2<15>, + + PC3<15>, + + PC4<15>, + + PC5<15>, + + PC6<15>, + + PC13<15>, + + PC14<15>, + + PC15<15>, + + PH3<15>, + ], + } +}*/ + +pub mod comp1 { + use super::*; + + pin! { + for [ + PA0<12>, + + PB0<12>, + + PB10<12>, + ], + } +} + +pub mod comp2 { + use super::*; + + pin! { + for [ + PA2<12>, + + PA7<12>, + + PB5<12>, + + PB11<12>, + ], + } +} + +pub mod debug { + use super::*; + + pin! { + for [ + PA14<0>, + ], + + for [ + PA15<0>, + ], + + for [ + PB3<0>, + ], + + for [ + PA13<0>, + ], + + for [ + PA2<13>, + ], + + for [ + PA0<13>, + ], + + for [ + PA1<13>, + ], + + for [ + PA12<6>, + ], + + for [ + PB3<13>, + ], + + for [ + PA10<13>, + ], + + for [ + PB4<13>, + ], + + for [ + PA11<13>, + ], + + for [ + PB2<13>, + ], + + for [ + PA6<13>, + ], + + for [ + PA7<13>, + ], + + for [ + PA4<13>, + ], + + for [ + PA5<13>, + ], + } +} + +pub mod i2c1 { + use super::*; + + pin! { + for [ + PA9<4>, + + PB6<4>, + + PB8<4>, + ], + + for [ + PA10<4>, + + PB7<4>, + + PB9<4>, + ], + + for [ + PA1<4>, + + PA14<4>, + + PB5<4>, + ], + } + use crate::pac::I2C1 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c2 { + use super::*; + + pin! { + for [ + PA12<4>, + + PB15<4>, + ], + + for [ + PA11<4>, + + PA15<4>, + ], + + for [ + PA6<4>, + + PA13<4>, + ], + } + use crate::pac::I2C2 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2c3 { + use super::*; + + pin! { + for [ + PA7<4>, + + PB10<4>, + + PB13<4>, + + PC0<4>, + ], + + for [ + PB4<4>, + + PB11<4>, + + PB14<4>, + + PC1<4>, + ], + + for [ + PA0<4>, + + PB2<4>, + + PB12<4>, + ], + } + use crate::pac::I2C3 as I2C; + impl I2cCommon for I2C { + type Scl = Scl; + type Sda = Sda; + type Smba = Smba; + } +} + +pub mod i2s { + use super::*; + + pin! { + for [ + PA0<5>, + ], + } +} + +pub mod i2s2 { + use super::*; + + pin! { + for [ + PA8<5>, + + PA9<5>, + + PB10<5>, + + PB13<5>, + ], + + for no:NoPin, [ + PA3<5>, + + PB14<3>, + + PC6<5>, + ], + + for [ + PA10<5>, + + PB15<5>, + + PC1<3>, + + PC3<5>, + ], + + for [ + PA9<3>, + + PB9<5>, + + PB12<5>, + ], + } +} + +pub mod ir { + use super::*; + + pin! { + default: PushPull for [ + PA13<8>, + + PB9<8>, + ], + } +} + +pub mod lptim1 { + use super::*; + + pin! { + for [ + PB6<1>, + + PC3<1>, + ], + + for [ + PB5<1>, + + PC0<1>, + ], + + for [ + PB7<1>, + + PC2<1>, + ], + + default:PushPull for [ + PA4<1>, + + PA14<1>, + + PB2<1>, + + PC1<1>, + ], + } +} + +pub mod lptim2 { + use super::*; + + pin! { + for [ + PA5<14>, + + PC3<14>, + ], + + for [ + PB1<14>, + + PC0<14>, + ], + + default:PushPull for [ + PA4<14>, + + PA8<14>, + ], + } +} + +pub mod lptim3 { + use super::*; + + pin! { + for [ + PA11<3>, + ], + + for [ + PA12<3>, + ], + + default:PushPull for [ + PA1<3>, + ], + } +} + +pub mod lpuart1 { + use super::*; + + pin! { + for [ + PA6<8>, + + PB13<8>, + ], + + for [ + PB1<8>, + + PB12<8>, + ], + + for [ + PA1<8>, + + PB1<8>, + + PB12<8>, + ], + + for [ + PA3<8>, + + PB10<8>, + + PC0<8>, + ], + } + + pin! { + default:PushPull for [ + PA2<8>, + + PB11<8>, + + PC1<8>, + ], + } +} + +pub mod rcc { + use super::*; + + pin! { + for [ + PA2<0>, + ], + + for [ + PA8<0>, + ], + } +} + +pub mod rf { + use super::*; + + pin! { + for [ + PB3<6>, + ], + + for [ + PB5<6>, + ], + + for [ + PB8<6>, + ], + } +} + +pub mod rtc { + use super::*; + + pin! { + for [ + PA10<0>, + ], + } +} + +pub mod spi1 { + use super::*; + + pin! { + for no:NoPin, [ + PA6<5>, + + PA11<5>, + + PB4<5>, + ], + + for no:NoPin, [ + PA7<5>, + + PA12<5>, + + PB5<5>, + ], + + for [ + PA4<5>, + + PA15<5>, + + PB2<5>, + ], + + for no:NoPin, [ + PA1<5>, + + PA5<5>, + + PB3<5>, + ], + } + impl SpiCommon for crate::pac::SPI1 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod spi2 { + use super::*; + + pin! { + for no:NoPin, [ + PA5<3>, + + PB14<5>, + + PC2<5>, + ], + + for no:NoPin, [ + PA10<5>, + + PB15<5>, + + PC1<3>, + + PC3<5>, + ], + + for [ + PA9<3>, + + PB9<5>, + + PB12<5>, + ], + + for no:NoPin, [ + PA8<5>, + + PA9<5>, + + PB10<5>, + + PB13<5>, + ], + } + impl SpiCommon for crate::pac::SPI2 { + type Miso = Miso; + type Mosi = Mosi; + type Nss = Nss; + type Sck = Sck; + } +} + +pub mod sys { + use super::*; + + pin! { + for [ + PB4<0>, + ], + } +} + +pub mod tim1 { + use super::*; + + pin! { + default:PushPull for [ + PA8<1>, + ], + + default:PushPull for [ + PA7<1>, + + PB13<1>, + ], + + default:PushPull for [ + PA9<1>, + ], + + default:PushPull for [ + PB8<1>, + + PB14<1>, + ], + + default:PushPull for [ + PA10<1>, + ], + + default:PushPull for [ + PB9<1>, + + PB15<1>, + ], + + default:PushPull for [ + PA11<1>, + ], + } + + pin! { + for [ + PA6<12>, + + PB7<3>, + + PB12<3>, + ], + + for [ + PA11<12>, + ], + + for [ + PA12<1>, + ], + } + + use crate::pac::TIM1 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimNCPin<1> for TIM { + type ChN = Ch2N; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimNCPin<2> for TIM { + type ChN = Ch3N; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim2 { + use super::*; + + pin! { + default:PushPull for [ + PA0<1>, + + PA5<1>, + + PA15<1>, + ], + + default:PushPull for [ + PA1<1>, + + PB3<1>, + ], + + default:PushPull for [ + PA2<1>, + + PB10<1>, + ], + + default:PushPull for [ + PA3<1>, + + PB11<1>, + ], + } + + pin! { + for [ + PA0<14>, + + PA5<2>, + + PA15<2>, + ], + } + + use crate::pac::TIM2 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimCPin<1> for TIM { + type Ch = Ch2; + } + impl TimCPin<2> for TIM { + type Ch = Ch3; + } + impl TimCPin<3> for TIM { + type Ch = Ch4; + } + impl TimEtr for TIM { + type Etr = Etr; + } +} + +pub mod tim16 { + use super::*; + + pin! { + default:PushPull for [ + PA6<14>, + + PB8<14>, + ], + + default:PushPull for [ + PB6<14>, + ], + } + + pin! { + for [ + PB5<14>, + ], + + } + + use crate::pac::TIM16 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod tim17 { + use super::*; + + pin! { + default:PushPull for [ + PA7<14>, + + PB9<14>, + ], + + default:PushPull for [ + PB7<14>, + ], + } + + pin! { + for [ + PA10<14>, + + PB4<14>, + ], + + } + + use crate::pac::TIM17 as TIM; + impl TimCPin<0> for TIM { + type Ch = Ch1; + } + impl TimNCPin<0> for TIM { + type ChN = Ch1N; + } + impl TimBkin for TIM { + type Bkin = Bkin; + } +} + +pub mod usart1 { + use super::*; + + pin! { + for [ + PA8<7>, + + PB5<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + ], + + for [ + PA11<7>, + + PB4<7>, + ], + + for [ + PA12<7>, + + PB3<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA10<7>, + + PB7<7>, + ], + + default:PushPull for no:NoPin, [ + PA9<7>, + + PB6<7>, + ], + } + use crate::pac::USART1 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} + +pub mod usart2 { + use super::*; + + pin! { + for [ + PA4<7>, + ], + + for [ + PA0<7>, + ], + + for [ + PA1<7>, + ], + + for [ + PA0<7>, + ], + + for [ + PA1<7>, + ], + } + + pin! { + default:PushPull for no:NoPin, [ + PA3<7>, + ], + + default:PushPull for no:NoPin, [ + PA2<7>, + ], + } + use crate::pac::USART2 as USART; + impl SerialAsync for USART { + type Rx = Rx; + type Tx = Tx; + } + impl SerialSync for USART { + type Ck = Ck; + } + impl SerialFlowControl for USART { + type Cts = Cts; + type Rts = Rts; + } +} diff --git a/src/gpio/c0.rs b/src/gpio/c0.rs new file mode 100644 index 00000000..70a09cd9 --- /dev/null +++ b/src/gpio/c0.rs @@ -0,0 +1,119 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-c0xx_453")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 4, 5]), + PA1: (pa1, 1, [0, 1, 2, 4, 5, 6, 7]), + PA2: (pa2, 2, [0, 1, 2, 3, 5]), + PA3: (pa3, 3, [1, 2, 5, 7]), + PA4: (pa4, 4, [0, 1, 2, 4, 5, 7]), + PA5: (pa5, 5, [0, 1, 2, 5, 7]), + PA6: (pa6, 6, [0, 1, 2, 5]), + PA7: (pa7, 7, [0, 1, 2, 4, 5]), + PA8: (pa8, 8, [0, 1, 2, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [0, 1, 2, 3, 4, 5, 6, 7]), + PA10: (pa10, 10, [0, 1, 2, 3, 5, 6, 7]), + PA11: (pa11, 11, [0, 1, 2, 5]), + PA12: (pa12, 12, [0, 1, 2, 5]), + PA13: (pa13, 13, [0, 1, 3, 4, 7], super::Debugger), + PA14: (pa14, 14, [0, 1, 7, 8, 9, 10, 11, 12], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4, 7], super::Debugger), +]); + +#[cfg(feature = "gpio-c0xx_453")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2]), + PB1: (pb1, 1, [0, 1, 2, 5, 7]), + PB2: (pb2, 2, [0, 3, 7]), + PB3: (pb3, 3, [0, 1, 3, 4, 7], super::Debugger), + PB4: (pb4, 4, [0, 1, 4, 5, 7], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3, 6]), + PB6: (pb6, 6, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB7: (pb7, 7, [0, 1, 2, 3, 6, 7, 9, 10, 11, 14]), + PB8: (pb8, 8, [1, 2, 3, 6, 7]), + PB9: (pb9, 9, [0, 1, 2, 3, 6, 7]), + PB10: (pb10, 10, []), + PB11: (pb11, 11, []), + PB12: (pb12, 12, [1, 2, 7]), + PB13: (pb13, 13, [2, 7]), + PB14: (pb14, 14, [2, 7]), + PB15: (pb15, 15, [2, 7]), +]); + +#[cfg(feature = "gpio-c0xx_453")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC6: (pc6, 6, [1]), + PC7: (pc7, 7, [1]), + PC13: (pc13, 13, [1, 2]), + PC14: (pc14, 14, [0, 1, 2, 8, 9, 10, 11, 14, 15]), + PC15: (pc15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-c0xx_453")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 2]), + PD1: (pd1, 1, [0, 2]), + PD2: (pd2, 2, [1, 2]), + PD3: (pd3, 3, [0, 2]), +]); + +#[cfg(feature = "gpio-c0xx_453")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [2]), + PF1: (pf1, 1, [0]), + PF2: (pf2, 2, [0, 1]), + PF3: (pf3, 3, []), +]); +/* +#[cfg(feature = "gpio-c0xx_453")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); + */ + +#[cfg(feature = "gpio-c0xx")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 4, 5]), + PA1: (pa1, 1, [0, 1, 2, 4, 5, 6, 7]), + PA2: (pa2, 2, [0, 1, 2, 3, 5]), + PA3: (pa3, 3, [1, 2, 5, 7]), + PA4: (pa4, 4, [0, 1, 2, 4, 5, 7]), + PA5: (pa5, 5, [0, 1, 2, 5, 7]), + PA6: (pa6, 6, [0, 1, 2, 5]), + PA7: (pa7, 7, [0, 1, 2, 4, 5]), + PA8: (pa8, 8, [0, 1, 2, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [0, 1, 2, 3, 4, 5, 6, 7]), + PA10: (pa10, 10, [0, 1, 2, 3, 5, 6, 7]), + PA11: (pa11, 11, [0, 1, 2, 5]), + PA12: (pa12, 12, [0, 1, 2, 5]), + PA13: (pa13, 13, [0, 1, 3, 4, 7], super::Debugger), + PA14: (pa14, 14, [0, 1, 7, 8, 9, 10, 11, 12], super::Debugger), +]); + +#[cfg(feature = "gpio-c0xx")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB6: (pb6, 6, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB7: (pb7, 7, [0, 1, 2, 3, 6, 7, 9, 10, 11, 14]), +]); + +#[cfg(feature = "gpio-c0xx")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC13: (pc13, 13, []), + PC14: (pc14, 14, [0, 1, 2, 8, 9, 10, 11, 14, 15]), + PC15: (pc15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-c0xx")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF2: (pf2, 2, [0, 1]), +]); +/* +#[cfg(feature = "gpio-c0xx")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ diff --git a/src/gpio/exti.rs b/src/gpio/exti.rs index f3efe9ee..7cbbeb99 100644 --- a/src/gpio/exti.rs +++ b/src/gpio/exti.rs @@ -1,15 +1,14 @@ -use super::{marker, Edge, Pin, PinExt}; -use crate::{ - pac::{Interrupt, EXTI}, - syscfg::SysCfg, -}; +use super::{marker, Edge, PinExt}; +use crate::{pac::EXTI, syscfg::SysCfg}; -impl Pin { +#[cfg(feature = "f4")] +impl super::Pin { /// NVIC interrupt number of interrupt from this pin /// /// Used to unmask / enable the interrupt with [`cortex_m::peripheral::NVIC::unmask()`]. /// This is also useful for all other [`cortex_m::peripheral::NVIC`] functions. - pub const fn interrupt(&self) -> Interrupt { + pub const fn interrupt(&self) -> crate::pac::Interrupt { + use crate::pac::Interrupt; match N { 0 => Interrupt::EXTI0, 1 => Interrupt::EXTI1, @@ -84,45 +83,65 @@ where let i = self.pin_id(); match edge { Edge::Rising => { - exti.rtsr() - .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.ftsr() - .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); + #[cfg(any(feature = "f4", feature = "f7"))] + let (rtsr, ftsr) = (exti.rtsr(), exti.ftsr()); + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let (rtsr, ftsr) = (exti.rtsr1, exti.ftsr1()); + rtsr.modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); + ftsr.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); } Edge::Falling => { - exti.ftsr() - .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.rtsr() - .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); + #[cfg(any(feature = "f4", feature = "f7"))] + let (rtsr, ftsr) = (exti.rtsr(), &exti.ftsr()); + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let (rtsr, ftsr) = (exti.rtsr1, exti.ftsr1()); + ftsr.modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); + rtsr.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << i)) }); } Edge::RisingFalling => { - exti.rtsr() - .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); - exti.ftsr() - .modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); + #[cfg(any(feature = "f4", feature = "f7"))] + let (rtsr, ftsr) = (exti.rtsr(), exti.ftsr()); + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let (rtsr, ftsr) = (exti.rtsr1(), exti.ftsr1()); + rtsr.modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); + ftsr.modify(|r, w| unsafe { w.bits(r.bits() | (1 << i)) }); } } } #[inline(always)] fn enable_interrupt(&mut self, exti: &mut EXTI) { - exti.imr() - .modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.pin_id())) }); + #[cfg(any(feature = "f4", feature = "f7"))] + let imr = exti.imr(); + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let imr = exti.imr1(); + imr.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.pin_id())) }); } #[inline(always)] fn disable_interrupt(&mut self, exti: &mut EXTI) { - exti.imr() - .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id())) }); + #[cfg(any(feature = "f4", feature = "f7"))] + let imr = exti.imr(); + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let imr = exti.imr1(); + imr.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id())) }); } #[inline(always)] fn clear_interrupt_pending_bit(&mut self) { - unsafe { (*EXTI::ptr()).pr().write(|w| w.bits(1 << self.pin_id())) }; + #[cfg(any(feature = "f4", feature = "f7"))] + let pr = unsafe { (*EXTI::ptr()).pr() }; + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let pr = unsafe { (*EXTI::ptr()).pr1() }; + pr.write(|w| unsafe { w.bits(1 << self.pin_id()) }); } #[inline(always)] fn check_interrupt(&self) -> bool { - unsafe { ((*EXTI::ptr()).pr().read().bits() & (1 << self.pin_id())) != 0 } + #[cfg(any(feature = "f4", feature = "f7"))] + let pr = unsafe { (*EXTI::ptr()).pr() }; + #[cfg(any(feature = "f3", feature = "g4", feature = "l4"))] + let pr = unsafe { (*EXTI::ptr()).pr1() }; + (pr.read().bits() & (1 << self.pin_id())) != 0 } } diff --git a/src/gpio/f0.rs b/src/gpio/f0.rs new file mode 100644 index 00000000..883d3084 --- /dev/null +++ b/src/gpio/f0.rs @@ -0,0 +1,411 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Input as DefaultMode; + +#[cfg(feature = "gpio-f031")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 3]), + PA1: (pa1, 1, [0, 1, 2, 3]), + PA2: (pa2, 2, [0, 1, 2, 3]), + PA3: (pa3, 3, [0, 1, 2, 3]), + PA4: (pa4, 4, [0, 1, 3, 4]), + PA5: (pa5, 5, [0, 1, 2, 3]), + PA6: (pa6, 6, [0, 1, 2, 3, 5, 6]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6]), + PA8: (pa8, 8, [0, 1, 2, 3]), + PA9: (pa9, 9, [0, 1, 2, 3, 4]), + PA10: (pa10, 10, [0, 1, 2, 3, 4]), + PA11: (pa11, 11, [0, 1, 2, 3]), + PA12: (pa12, 12, [0, 1, 2, 3]), + PA13: (pa13, 13, [1], super::Debugger), + PA14: (pa14, 14, [0, 1], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3], super::Debugger), +]); + +#[cfg(feature = "gpio-f031")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3]), + PB1: (pb1, 1, [0, 1, 2, 3]), + PB2: (pb2, 2, [3]), + PB3: (pb3, 3, [0, 1, 2, 3], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3]), + PB8: (pb8, 8, [1, 2, 3]), + PB9: (pb9, 9, [0, 1, 2, 3]), + PB10: (pb10, 10, [1, 2, 3]), + PB11: (pb11, 11, [0, 1, 2, 3]), + PB12: (pb12, 12, [0, 1, 2, 3]), + PB13: (pb13, 13, [0, 2, 3]), + PB14: (pb14, 14, [0, 1, 2, 3]), + PB15: (pb15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-f031")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f031")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, []), + PF1: (pf1, 1, []), + PF6: (pf6, 6, []), + PF7: (pf7, 7, []), +]); + +#[cfg(feature = "gpio-f042")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3]), + PA1: (pa1, 1, [0, 1, 2, 3]), + PA2: (pa2, 2, [1, 2, 3]), + PA3: (pa3, 3, [1, 2, 3]), + PA4: (pa4, 4, [0, 1, 2, 3, 4]), + PA5: (pa5, 5, [0, 1, 2, 3]), + PA6: (pa6, 6, [0, 1, 2, 3, 5, 6]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6]), + PA8: (pa8, 8, [0, 1, 2, 3, 4]), + PA9: (pa9, 9, [1, 2, 3, 4, 5]), + PA10: (pa10, 10, [0, 1, 2, 3, 4]), + PA11: (pa11, 11, [0, 1, 2, 3, 4, 5]), + PA12: (pa12, 12, [0, 1, 2, 3, 4, 5]), + PA13: (pa13, 13, [0, 1, 2], super::Debugger), + PA14: (pa14, 14, [0, 1], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5], super::Debugger), +]); + +#[cfg(feature = "gpio-f042")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3]), + PB1: (pb1, 1, [0, 1, 2, 3]), + PB2: (pb2, 2, [3]), + PB3: (pb3, 3, [0, 1, 2, 3], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 5], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3]), + PB8: (pb8, 8, [0, 1, 2, 3, 4]), + PB9: (pb9, 9, [0, 1, 2, 3, 4, 5]), + PB10: (pb10, 10, [0, 1, 2, 3, 5]), + PB11: (pb11, 11, [0, 1, 2]), + PB12: (pb12, 12, [0, 1, 2]), + PB13: (pb13, 13, [0, 2, 5]), + PB14: (pb14, 14, [0, 2, 5]), + PB15: (pb15, 15, [0, 2]), +]); + +#[cfg(feature = "gpio-f042")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f042")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [0, 1]), + PF1: (pf1, 1, [1]), + PF11: (pf11, 11, []), +]); + +#[cfg(feature = "gpio-f051")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 3, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 7]), + PA2: (pa2, 2, [0, 1, 2, 3, 7]), + PA3: (pa3, 3, [0, 1, 2, 3, 7]), + PA4: (pa4, 4, [0, 1, 3, 4, 7]), + PA5: (pa5, 5, [0, 1, 2, 3, 7]), + PA6: (pa6, 6, [0, 1, 2, 3, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6, 7]), + PA8: (pa8, 8, [0, 1, 2, 3]), + PA9: (pa9, 9, [0, 1, 2, 3]), + PA10: (pa10, 10, [0, 1, 2, 3]), + PA11: (pa11, 11, [0, 1, 2, 3, 7]), + PA12: (pa12, 12, [0, 1, 2, 3, 7]), + PA13: (pa13, 13, [1], super::Debugger), + PA14: (pa14, 14, [0, 1], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3], super::Debugger), +]); + +#[cfg(feature = "gpio-f051")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3]), + PB1: (pb1, 1, [0, 1, 2, 3]), + PB2: (pb2, 2, [3]), + PB3: (pb3, 3, [0, 1, 2, 3], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3]), + PB8: (pb8, 8, [0, 1, 2, 3]), + PB9: (pb9, 9, [0, 1, 2, 3]), + PB10: (pb10, 10, [0, 1, 2, 3]), + PB11: (pb11, 11, [0, 1, 2, 3]), + PB12: (pb12, 12, [0, 1, 2, 3]), + PB13: (pb13, 13, [0, 2, 3]), + PB14: (pb14, 14, [0, 1, 2, 3]), + PB15: (pb15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-f051")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, []), + PC1: (pc1, 1, []), + PC2: (pc2, 2, []), + PC3: (pc3, 3, []), + PC4: (pc4, 4, []), + PC5: (pc5, 5, []), + PC6: (pc6, 6, [0]), + PC7: (pc7, 7, [0]), + PC8: (pc8, 8, [0]), + PC9: (pc9, 9, [0]), + PC10: (pc10, 10, []), + PC11: (pc11, 11, []), + PC12: (pc12, 12, []), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f051")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD2: (pd2, 2, [0]), +]); + +#[cfg(feature = "gpio-f051")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, []), + PF1: (pf1, 1, []), + PF4: (pf4, 4, []), + PF5: (pf5, 5, []), + PF6: (pf6, 6, []), + PF7: (pf7, 7, []), +]); + +#[cfg(feature = "gpio-f052")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 4, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5]), + PA2: (pa2, 2, [0, 1, 2, 3, 7]), + PA3: (pa3, 3, [0, 1, 2, 3]), + PA4: (pa4, 4, [0, 1, 3, 4]), + PA5: (pa5, 5, [0, 1, 2, 3]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6, 7]), + PA8: (pa8, 8, [0, 1, 2, 3, 4]), + PA9: (pa9, 9, [0, 1, 2, 3]), + PA10: (pa10, 10, [0, 1, 2, 3]), + PA11: (pa11, 11, [0, 1, 2, 3, 4, 7]), + PA12: (pa12, 12, [0, 1, 2, 3, 4, 7]), + PA13: (pa13, 13, [0, 1, 2], super::Debugger), + PA14: (pa14, 14, [0, 1], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4], super::Debugger), +]); + +#[cfg(feature = "gpio-f052")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3, 4]), + PB1: (pb1, 1, [0, 1, 2, 3, 4]), + PB2: (pb2, 2, [3]), + PB3: (pb3, 3, [0, 1, 2, 3], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 5], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3, 4]), + PB8: (pb8, 8, [0, 1, 2, 3, 4]), + PB9: (pb9, 9, [0, 1, 2, 3, 4, 5]), + PB10: (pb10, 10, [0, 1, 2, 3, 4, 5]), + PB11: (pb11, 11, [0, 1, 2, 3, 4]), + PB12: (pb12, 12, [0, 1, 2, 3, 4, 5]), + PB13: (pb13, 13, [0, 2, 3, 4, 5]), + PB14: (pb14, 14, [0, 1, 2, 3, 4, 5]), + PB15: (pb15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-f052")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 7]), + PC1: (pc1, 1, [0, 7]), + PC2: (pc2, 2, [0, 1, 7]), + PC3: (pc3, 3, [0, 1, 7]), + PC4: (pc4, 4, [0, 1]), + PC5: (pc5, 5, [0, 1, 7]), + PC6: (pc6, 6, [0, 7]), + PC7: (pc7, 7, [0, 7]), + PC8: (pc8, 8, [0, 7]), + PC9: (pc9, 9, [0, 7]), + PC10: (pc10, 10, [0, 1, 7]), + PC11: (pc11, 11, [0, 1, 7]), + PC12: (pc12, 12, [0, 1, 7]), + PC13: (pc13, 13, [7]), + PC14: (pc14, 14, [7]), + PC15: (pc15, 15, [7]), +]); + +#[cfg(feature = "gpio-f052")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1]), + PD1: (pd1, 1, [0, 1]), + PD2: (pd2, 2, [0, 1]), + PD3: (pd3, 3, [0, 1, 4]), + PD4: (pd4, 4, [0, 1, 4]), + PD5: (pd5, 5, [0]), + PD6: (pd6, 6, [0]), + PD7: (pd7, 7, [0]), + PD8: (pd8, 8, [0, 4]), + PD9: (pd9, 9, [0]), + PD10: (pd10, 10, [0]), + PD11: (pd11, 11, [0]), + PD12: (pd12, 12, [0, 1]), + PD13: (pd13, 13, [1]), + PD14: (pd14, 14, [1]), + PD15: (pd15, 15, [0, 1]), +]); + +#[cfg(feature = "gpio-f052")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [0, 1]), + PE1: (pe1, 1, [0, 1]), + PE2: (pe2, 2, [0, 1]), + PE3: (pe3, 3, [0, 1]), + PE4: (pe4, 4, [0, 1]), + PE5: (pe5, 5, [0, 1]), + PE6: (pe6, 6, [0]), + PE7: (pe7, 7, [0]), + PE8: (pe8, 8, [0]), + PE9: (pe9, 9, [0]), + PE10: (pe10, 10, [0]), + PE11: (pe11, 11, [0]), + PE12: (pe12, 12, [0, 1]), + PE13: (pe13, 13, [0, 1]), + PE14: (pe14, 14, [0, 1]), + PE15: (pe15, 15, [0, 1]), +]); + +#[cfg(feature = "gpio-f052")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [0]), + PF1: (pf1, 1, []), + PF2: (pf2, 2, [0]), + PF3: (pf3, 3, [0]), + PF6: (pf6, 6, []), + PF9: (pf9, 9, [0]), + PF10: (pf10, 10, [0]), +]); + +#[cfg(feature = "gpio-f091")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 4, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5]), + PA2: (pa2, 2, [0, 1, 2, 3, 7]), + PA3: (pa3, 3, [0, 1, 2, 3]), + PA4: (pa4, 4, [0, 1, 3, 4, 5]), + PA5: (pa5, 5, [0, 1, 2, 3, 5]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6, 7]), + PA8: (pa8, 8, [0, 1, 2, 3, 4]), + PA9: (pa9, 9, [0, 1, 2, 3, 4, 5]), + PA10: (pa10, 10, [0, 1, 2, 3, 4]), + PA11: (pa11, 11, [0, 1, 2, 3, 4, 5, 7]), + PA12: (pa12, 12, [0, 1, 2, 3, 4, 5, 7]), + PA13: (pa13, 13, [0, 1, 2], super::Debugger), + PA14: (pa14, 14, [0, 1], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4], super::Debugger), +]); + +#[cfg(feature = "gpio-f091")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3, 4]), + PB1: (pb1, 1, [0, 1, 2, 3, 4]), + PB2: (pb2, 2, [3]), + PB3: (pb3, 3, [0, 1, 2, 3, 4], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4, 5], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3, 4]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3, 4]), + PB8: (pb8, 8, [0, 1, 2, 3, 4]), + PB9: (pb9, 9, [0, 1, 2, 3, 4, 5]), + PB10: (pb10, 10, [0, 1, 2, 3, 4, 5]), + PB11: (pb11, 11, [0, 1, 2, 3, 4]), + PB12: (pb12, 12, [0, 1, 2, 3, 4, 5]), + PB13: (pb13, 13, [0, 2, 3, 4, 5]), + PB14: (pb14, 14, [0, 1, 2, 3, 4, 5]), + PB15: (pb15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-f091")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 1, 2]), + PC1: (pc1, 1, [0, 1, 2]), + PC2: (pc2, 2, [0, 1, 2]), + PC3: (pc3, 3, [0, 1, 2]), + PC4: (pc4, 4, [0, 1]), + PC5: (pc5, 5, [0, 1]), + PC6: (pc6, 6, [0, 1]), + PC7: (pc7, 7, [0, 1]), + PC8: (pc8, 8, [0, 1]), + PC9: (pc9, 9, [0, 1]), + PC10: (pc10, 10, [0, 1]), + PC11: (pc11, 11, [0, 1]), + PC12: (pc12, 12, [0, 1, 2]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f091")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1]), + PD1: (pd1, 1, [0, 1]), + PD2: (pd2, 2, [0, 1, 2]), + PD3: (pd3, 3, [0, 1]), + PD4: (pd4, 4, [0, 1]), + PD5: (pd5, 5, [0]), + PD6: (pd6, 6, [0]), + PD7: (pd7, 7, [0]), + PD8: (pd8, 8, [0]), + PD9: (pd9, 9, [0]), + PD10: (pd10, 10, [0]), + PD11: (pd11, 11, [0]), + PD12: (pd12, 12, [0, 1, 2]), + PD13: (pd13, 13, [0, 1]), + PD14: (pd14, 14, [0, 1]), + PD15: (pd15, 15, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-f091")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [0, 1]), + PE1: (pe1, 1, [0, 1]), + PE2: (pe2, 2, [0, 1]), + PE3: (pe3, 3, [0, 1]), + PE4: (pe4, 4, [0, 1]), + PE5: (pe5, 5, [0, 1]), + PE6: (pe6, 6, [0]), + PE7: (pe7, 7, [0, 1]), + PE8: (pe8, 8, [0, 1]), + PE9: (pe9, 9, [0, 1]), + PE10: (pe10, 10, [0, 1]), + PE11: (pe11, 11, [0, 1]), + PE12: (pe12, 12, [0, 1]), + PE13: (pe13, 13, [0, 1]), + PE14: (pe14, 14, [0, 1]), + PE15: (pe15, 15, [0, 1]), +]); + +#[cfg(feature = "gpio-f091")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [0, 1]), + PF1: (pf1, 1, [1]), + PF2: (pf2, 2, [0, 1, 2]), + PF3: (pf3, 3, [0, 1, 2]), + PF6: (pf6, 6, []), + PF9: (pf9, 9, [0, 1]), + PF10: (pf10, 10, [0, 1]), +]); diff --git a/src/gpio/f2.rs b/src/gpio/f2.rs new file mode 100644 index 00000000..60ca10c0 --- /dev/null +++ b/src/gpio/f2.rs @@ -0,0 +1,181 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Input as DefaultMode; + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 3, 7, 8, 11]), + PA1: (pa1, 1, [1, 2, 7, 8, 11]), + PA2: (pa2, 2, [1, 2, 3, 7, 11]), + PA3: (pa3, 3, [1, 2, 3, 7, 10, 11]), + PA4: (pa4, 4, [5, 6, 7, 12, 13]), + PA5: (pa5, 5, [1, 3, 5, 10]), + PA6: (pa6, 6, [1, 2, 3, 5, 9, 13]), + PA7: (pa7, 7, [1, 2, 3, 5, 9, 11]), + PA8: (pa8, 8, [0, 1, 4, 7, 10]), + PA9: (pa9, 9, [1, 4, 7, 13]), + PA10: (pa10, 10, [1, 7, 10, 13]), + PA11: (pa11, 11, [1, 7, 9, 10]), + PA12: (pa12, 12, [1, 7, 9, 10]), + PA13: (pa13, 13, [0], super::Debugger), + PA14: (pa14, 14, [0], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 6], super::Debugger), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 10, 11]), + PB1: (pb1, 1, [1, 2, 3, 10, 11]), + PB2: (pb2, 2, []), + PB3: (pb3, 3, [0, 1, 5, 6], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 9, 10, 11, 13]), + PB6: (pb6, 6, [2, 4, 7, 9, 13]), + PB7: (pb7, 7, [2, 4, 7, 12, 13]), + PB8: (pb8, 8, [2, 3, 4, 9, 11, 12, 13]), + PB9: (pb9, 9, [2, 3, 4, 5, 9, 12, 13]), + PB10: (pb10, 10, [1, 4, 5, 7, 10, 11]), + PB11: (pb11, 11, [1, 4, 7, 10, 11]), + PB12: (pb12, 12, [1, 4, 5, 7, 9, 10, 11, 12]), + PB13: (pb13, 13, [1, 5, 7, 9, 10, 11, 12]), + PB14: (pb14, 14, [1, 3, 5, 7, 9, 12]), + PB15: (pb15, 15, [0, 1, 3, 5, 9, 12]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [10]), + PC1: (pc1, 1, [11]), + PC2: (pc2, 2, [5, 10, 11]), + PC3: (pc3, 3, [5, 10, 11]), + PC4: (pc4, 4, [11]), + PC5: (pc5, 5, [11]), + PC6: (pc6, 6, [2, 3, 5, 8, 12, 13]), + PC7: (pc7, 7, [2, 3, 6, 8, 12, 13]), + PC8: (pc8, 8, [2, 3, 8, 12, 13]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 12, 13]), + PC10: (pc10, 10, [6, 7, 8, 12, 13]), + PC11: (pc11, 11, [6, 7, 8, 12, 13]), + PC12: (pc12, 12, [6, 7, 8, 12, 13]), + PC13: (pc13, 13, [0]), + PC14: (pc14, 14, [0]), + PC15: (pc15, 15, [0]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [9, 12]), + PD1: (pd1, 1, [9, 12]), + PD2: (pd2, 2, [2, 8, 12, 13]), + PD3: (pd3, 3, [7, 12]), + PD4: (pd4, 4, [7, 12]), + PD5: (pd5, 5, [7, 12]), + PD6: (pd6, 6, [7, 12]), + PD7: (pd7, 7, [7, 12]), + PD8: (pd8, 8, [7, 12]), + PD9: (pd9, 9, [7, 12]), + PD10: (pd10, 10, [7, 12]), + PD11: (pd11, 11, [7, 12]), + PD12: (pd12, 12, [2, 7, 12]), + PD13: (pd13, 13, [2, 12]), + PD14: (pd14, 14, [2, 12]), + PD15: (pd15, 15, [2, 12]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 12, 13]), + PE1: (pe1, 1, [12, 13]), + PE2: (pe2, 2, [0, 11, 12]), + PE3: (pe3, 3, [0, 12]), + PE4: (pe4, 4, [0, 12, 13]), + PE5: (pe5, 5, [0, 3, 12, 13]), + PE6: (pe6, 6, [0, 3, 12, 13]), + PE7: (pe7, 7, [1, 12]), + PE8: (pe8, 8, [1, 12]), + PE9: (pe9, 9, [1, 12]), + PE10: (pe10, 10, [1, 12]), + PE11: (pe11, 11, [1, 12]), + PE12: (pe12, 12, [1, 12]), + PE13: (pe13, 13, [1, 12]), + PE14: (pe14, 14, [1, 12]), + PE15: (pe15, 15, [1, 12]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12]), + PF1: (pf1, 1, [4, 12]), + PF2: (pf2, 2, [4, 12]), + PF3: (pf3, 3, [12]), + PF4: (pf4, 4, [12]), + PF5: (pf5, 5, [12]), + PF6: (pf6, 6, [3, 12]), + PF7: (pf7, 7, [3, 12]), + PF8: (pf8, 8, [9, 12]), + PF9: (pf9, 9, [9, 12]), + PF10: (pf10, 10, [12]), + PF11: (pf11, 11, [13]), + PF12: (pf12, 12, [12]), + PF13: (pf13, 13, [12]), + PF14: (pf14, 14, [12]), + PF15: (pf15, 15, [12]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [12]), + PG1: (pg1, 1, [12]), + PG2: (pg2, 2, [12]), + PG3: (pg3, 3, [12]), + PG4: (pg4, 4, [12]), + PG5: (pg5, 5, [12]), + PG6: (pg6, 6, [12]), + PG7: (pg7, 7, [8, 12]), + PG8: (pg8, 8, [8, 11]), + PG9: (pg9, 9, [8, 12]), + PG10: (pg10, 10, [12]), + PG11: (pg11, 11, [11, 12]), + PG12: (pg12, 12, [8, 12]), + PG13: (pg13, 13, [8, 11, 12]), + PG14: (pg14, 14, [8, 11, 12]), + PG15: (pg15, 15, [8, 13]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, [0]), + PH2: (ph2, 2, [11]), + PH3: (ph3, 3, [11]), + PH4: (ph4, 4, [4, 10]), + PH5: (ph5, 5, [4]), + PH6: (ph6, 6, [4, 9, 11]), + PH7: (ph7, 7, [4, 11]), + PH8: (ph8, 8, [4, 13]), + PH9: (ph9, 9, [4, 9, 13]), + PH10: (ph10, 10, [2, 13]), + PH11: (ph11, 11, [2, 13]), + PH12: (ph12, 12, [2, 13]), + PH13: (ph13, 13, [3, 9]), + PH14: (ph14, 14, [3, 13]), + PH15: (ph15, 15, [3, 13]), +]); + +#[cfg(feature = "gpio-f217")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 13]), + PI1: (pi1, 1, [5, 13]), + PI2: (pi2, 2, [3, 5, 13]), + PI3: (pi3, 3, [3, 5, 13]), + PI4: (pi4, 4, [3, 13]), + PI5: (pi5, 5, [3, 13]), + PI6: (pi6, 6, [3, 13]), + PI7: (pi7, 7, [3, 13]), + PI8: (pi8, 8, []), + PI9: (pi9, 9, [9]), + PI10: (pi10, 10, [11]), + PI11: (pi11, 11, [10]), +]); diff --git a/src/gpio/f3.rs b/src/gpio/f3.rs new file mode 100644 index 00000000..9ce02a38 --- /dev/null +++ b/src/gpio/f3.rs @@ -0,0 +1,514 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Input as DefaultMode; + +#[cfg(feature = "gpio-f302")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 3, 7, 15]), + PA1: (pa1, 1, [0, 1, 3, 7, 9, 15]), + PA2: (pa2, 2, [1, 3, 7, 8, 9, 15]), + PA3: (pa3, 3, [1, 3, 7, 9, 15]), + PA4: (pa4, 4, [3, 6, 7, 15]), + PA5: (pa5, 5, [1, 3, 15]), + PA6: (pa6, 6, [1, 3, 6, 15]), + PA7: (pa7, 7, [1, 3, 6, 15]), + PA8: (pa8, 8, [0, 3, 4, 5, 6, 7, 15]), + PA9: (pa9, 9, [2, 3, 4, 5, 6, 7, 9, 10, 15]), + PA10: (pa10, 10, [1, 3, 4, 5, 6, 7, 8, 10, 15]), + PA11: (pa11, 11, [5, 6, 7, 9, 11, 12, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 8, 9, 11, 15]), + PA13: (pa13, 13, [0, 1, 3, 5, 7, 15], super::Debugger), + PA14: (pa14, 14, [0, 3, 4, 6, 7, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 3, 4, 6, 7, 9, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-f302")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [3, 6, 15]), + PB1: (pb1, 1, [3, 6, 8, 15]), + PB2: (pb2, 2, [3, 15]), + PB3: (pb3, 3, [0, 1, 3, 6, 7, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 3, 6, 7, 10, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 6, 7, 8, 10, 15]), + PB6: (pb6, 6, [1, 3, 4, 7, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 15]), + PB8: (pb8, 8, [1, 3, 4, 7, 9, 12, 15]), + PB9: (pb9, 9, [1, 4, 6, 7, 8, 9, 15]), + PB10: (pb10, 10, [1, 3, 7, 15]), + PB11: (pb11, 11, [1, 3, 7, 15]), + PB12: (pb12, 12, [3, 4, 5, 6, 7, 15]), + PB13: (pb13, 13, [3, 5, 6, 7, 15]), + PB14: (pb14, 14, [1, 3, 5, 6, 7, 15]), + PB15: (pb15, 15, [0, 1, 2, 4, 5, 15]), +]); + +#[cfg(feature = "gpio-f302")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2]), + PC1: (pc1, 1, [1, 2]), + PC2: (pc2, 2, [1, 2]), + PC3: (pc3, 3, [1, 2, 6]), + PC4: (pc4, 4, [1, 2, 7]), + PC5: (pc5, 5, [1, 2, 3, 7]), + PC6: (pc6, 6, [1, 6, 7]), + PC7: (pc7, 7, [1, 6]), + PC8: (pc8, 8, [1]), + PC9: (pc9, 9, [1, 3, 5]), + PC10: (pc10, 10, [1, 6, 7]), + PC11: (pc11, 11, [1, 6, 7]), + PC12: (pc12, 12, [1, 6, 7]), + PC13: (pc13, 13, [4]), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f302")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD2: (pd2, 2, [1]), +]); + +#[cfg(feature = "gpio-f302")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 6]), + PF1: (pf1, 1, [4, 5]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 3, 7, 8, 9, 10, 15]), + PA1: (pa1, 1, [0, 1, 3, 7, 9, 15]), + PA2: (pa2, 2, [1, 3, 7, 8, 9, 15]), + PA3: (pa3, 3, [1, 3, 7, 9, 15]), + PA4: (pa4, 4, [2, 3, 5, 6, 7, 15]), + PA5: (pa5, 5, [1, 3, 5, 15]), + PA6: (pa6, 6, [1, 2, 3, 4, 5, 6, 8, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 6, 15]), + PA8: (pa8, 8, [0, 3, 4, 5, 6, 7, 8, 10, 15]), + PA9: (pa9, 9, [2, 3, 4, 5, 6, 7, 8, 9, 10, 15]), + PA10: (pa10, 10, [1, 3, 4, 5, 6, 7, 8, 10, 11, 15]), + PA11: (pa11, 11, [5, 6, 7, 8, 9, 10, 11, 12, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 8, 9, 10, 11, 15]), + PA13: (pa13, 13, [0, 1, 3, 5, 7, 10, 15], super::Debugger), + PA14: (pa14, 14, [0, 3, 4, 5, 6, 7, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4, 5, 6, 7, 9, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 3, 4, 6, 15]), + PB1: (pb1, 1, [2, 3, 4, 6, 8, 15]), + PB2: (pb2, 2, [3, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4, 5, 6, 7, 10, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 10, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 5, 6, 7, 10, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 5, 7, 10, 12, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 7, 8, 9, 10, 12, 15]), + PB9: (pb9, 9, [1, 2, 4, 6, 7, 8, 9, 10, 15]), + PB10: (pb10, 10, [1, 3, 7, 15]), + PB11: (pb11, 11, [1, 3, 7, 15]), + PB12: (pb12, 12, [3, 4, 5, 6, 7, 15]), + PB13: (pb13, 13, [3, 5, 6, 7, 15]), + PB14: (pb14, 14, [1, 3, 5, 6, 7, 15]), + PB15: (pb15, 15, [0, 1, 2, 4, 5, 15]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2]), + PC1: (pc1, 1, [1, 2]), + PC2: (pc2, 2, [1, 2, 3]), + PC3: (pc3, 3, [1, 2, 6]), + PC4: (pc4, 4, [1, 2, 7]), + PC5: (pc5, 5, [1, 2, 3, 7]), + PC6: (pc6, 6, [1, 2, 4, 6, 7]), + PC7: (pc7, 7, [1, 2, 4, 6, 7]), + PC8: (pc8, 8, [1, 2, 4, 7]), + PC9: (pc9, 9, [1, 2, 3, 4, 5, 6]), + PC10: (pc10, 10, [1, 4, 5, 6, 7]), + PC11: (pc11, 11, [1, 4, 5, 6, 7]), + PC12: (pc12, 12, [1, 4, 5, 6, 7]), + PC13: (pc13, 13, [1, 4]), + PC14: (pc14, 14, [1]), + PC15: (pc15, 15, [1]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [1, 7, 12]), + PD1: (pd1, 1, [1, 4, 6, 7, 12]), + PD2: (pd2, 2, [1, 2, 4, 5]), + PD3: (pd3, 3, [1, 2, 7, 12]), + PD4: (pd4, 4, [1, 2, 7, 12]), + PD5: (pd5, 5, [1, 7, 12]), + PD6: (pd6, 6, [1, 2, 7, 12]), + PD7: (pd7, 7, [1, 2, 7, 12]), + PD8: (pd8, 8, [1, 7, 12]), + PD9: (pd9, 9, [1, 7, 12]), + PD10: (pd10, 10, [1, 7, 12]), + PD11: (pd11, 11, [1, 7, 12]), + PD12: (pd12, 12, [1, 2, 3, 7, 12]), + PD13: (pd13, 13, [1, 2, 3, 12]), + PD14: (pd14, 14, [1, 2, 3, 12]), + PD15: (pd15, 15, [1, 2, 3, 6, 12]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2, 4, 6, 7, 12]), + PE1: (pe1, 1, [1, 4, 6, 7, 12]), + PE2: (pe2, 2, [0, 1, 2, 3, 5, 6, 12]), + PE3: (pe3, 3, [0, 1, 2, 3, 5, 6, 12]), + PE4: (pe4, 4, [0, 1, 2, 3, 5, 6, 12]), + PE5: (pe5, 5, [0, 1, 2, 3, 5, 6, 12]), + PE6: (pe6, 6, [0, 1, 5, 6, 12]), + PE7: (pe7, 7, [1, 2, 12]), + PE8: (pe8, 8, [1, 2, 12]), + PE9: (pe9, 9, [1, 2, 12]), + PE10: (pe10, 10, [1, 2, 12]), + PE11: (pe11, 11, [1, 2, 5, 12]), + PE12: (pe12, 12, [1, 2, 5, 12]), + PE13: (pe13, 13, [1, 2, 5, 12]), + PE14: (pe14, 14, [1, 2, 5, 6, 12]), + PE15: (pe15, 15, [1, 2, 7, 12]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [1, 4, 5, 6]), + PF1: (pf1, 1, [1, 4, 5]), + PF2: (pf2, 2, [1, 2, 12]), + PF3: (pf3, 3, [1, 2, 12]), + PF4: (pf4, 4, [1, 2, 3, 12]), + PF5: (pf5, 5, [1, 2, 12]), + PF6: (pf6, 6, [1, 2, 4, 7, 12]), + PF7: (pf7, 7, [1, 2, 12]), + PF8: (pf8, 8, [1, 2, 12]), + PF9: (pf9, 9, [1, 2, 3, 5, 12]), + PF10: (pf10, 10, [1, 2, 3, 5, 12]), + PF11: (pf11, 11, [1, 2]), + PF12: (pf12, 12, [1, 2, 12]), + PF13: (pf13, 13, [1, 2, 12]), + PF14: (pf14, 14, [1, 2, 12]), + PF15: (pf15, 15, [1, 2, 12]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [1, 2, 12]), + PG1: (pg1, 1, [1, 2, 12]), + PG2: (pg2, 2, [1, 2, 12]), + PG3: (pg3, 3, [1, 2, 12]), + PG4: (pg4, 4, [1, 2, 12]), + PG5: (pg5, 5, [1, 2, 12]), + PG6: (pg6, 6, [1, 12]), + PG7: (pg7, 7, [1, 12]), + PG8: (pg8, 8, [1]), + PG9: (pg9, 9, [1, 12]), + PG10: (pg10, 10, [1, 12]), + PG11: (pg11, 11, [1, 12]), + PG12: (pg12, 12, [1, 12]), + PG13: (pg13, 13, [1, 12]), + PG14: (pg14, 14, [1, 12]), + PG15: (pg15, 15, [1]), +]); + +#[cfg(feature = "gpio-f303e")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [1, 2, 12]), + PH1: (ph1, 1, [1, 2, 12]), + PH2: (ph2, 2, [1]), +]); + +#[cfg(feature = "gpio-f303")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 3, 7, 8, 9, 10, 15]), + PA1: (pa1, 1, [0, 1, 3, 7, 9, 15]), + PA2: (pa2, 2, [1, 3, 7, 8, 9, 15]), + PA3: (pa3, 3, [1, 3, 7, 9, 15]), + PA4: (pa4, 4, [2, 3, 5, 6, 7, 15]), + PA5: (pa5, 5, [1, 3, 5, 15]), + PA6: (pa6, 6, [1, 2, 3, 4, 5, 6, 8, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 6, 8, 15]), + PA8: (pa8, 8, [0, 4, 5, 6, 7, 8, 10, 15]), + PA9: (pa9, 9, [3, 4, 5, 6, 7, 8, 9, 10, 15]), + PA10: (pa10, 10, [1, 3, 4, 6, 7, 8, 10, 11, 15]), + PA11: (pa11, 11, [6, 7, 8, 9, 10, 11, 12, 14, 15]), + PA12: (pa12, 12, [1, 6, 7, 8, 9, 10, 11, 14, 15]), + PA13: (pa13, 13, [0, 1, 3, 5, 7, 10, 15], super::Debugger), + PA14: (pa14, 14, [0, 3, 4, 5, 6, 7, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 4, 5, 6, 7, 9, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-f303")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 3, 4, 6, 15]), + PB1: (pb1, 1, [2, 3, 4, 6, 8, 15]), + PB2: (pb2, 2, [3, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4, 5, 6, 7, 10, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 10, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 5, 6, 7, 10, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 5, 7, 10, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 8, 9, 10, 12, 15]), + PB9: (pb9, 9, [1, 2, 4, 6, 8, 9, 10, 15]), + PB10: (pb10, 10, [1, 3, 7, 15]), + PB11: (pb11, 11, [1, 3, 7, 15]), + PB12: (pb12, 12, [3, 4, 5, 6, 7, 15]), + PB13: (pb13, 13, [3, 5, 6, 7, 15]), + PB14: (pb14, 14, [1, 3, 5, 6, 7, 15]), + PB15: (pb15, 15, [0, 1, 2, 4, 5, 15]), +]); + +#[cfg(feature = "gpio-f303")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1]), + PC1: (pc1, 1, [1]), + PC2: (pc2, 2, [1, 3]), + PC3: (pc3, 3, [1, 6]), + PC4: (pc4, 4, [1, 7]), + PC5: (pc5, 5, [1, 3, 7]), + PC6: (pc6, 6, [1, 2, 4, 6, 7]), + PC7: (pc7, 7, [1, 2, 4, 6, 7]), + PC8: (pc8, 8, [1, 2, 4, 7]), + PC9: (pc9, 9, [1, 2, 4, 5, 6]), + PC10: (pc10, 10, [1, 4, 5, 6, 7]), + PC11: (pc11, 11, [1, 4, 5, 6, 7]), + PC12: (pc12, 12, [1, 4, 5, 6, 7]), + PC13: (pc13, 13, [4]), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f303")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [1, 7]), + PD1: (pd1, 1, [1, 4, 6, 7]), + PD2: (pd2, 2, [1, 2, 4, 5]), + PD3: (pd3, 3, [1, 2, 7]), + PD4: (pd4, 4, [1, 2, 7]), + PD5: (pd5, 5, [1, 7]), + PD6: (pd6, 6, [1, 2, 7]), + PD7: (pd7, 7, [1, 2, 7]), + PD8: (pd8, 8, [1, 7]), + PD9: (pd9, 9, [1, 7]), + PD10: (pd10, 10, [1, 7]), + PD11: (pd11, 11, [1, 7]), + PD12: (pd12, 12, [1, 2, 3, 7]), + PD13: (pd13, 13, [1, 2, 3]), + PD14: (pd14, 14, [1, 2, 3]), + PD15: (pd15, 15, [1, 2, 3, 6]), +]); + +#[cfg(feature = "gpio-f303")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2, 4, 7]), + PE1: (pe1, 1, [1, 4, 7]), + PE2: (pe2, 2, [0, 1, 2, 3]), + PE3: (pe3, 3, [0, 1, 2, 3]), + PE4: (pe4, 4, [0, 1, 2, 3]), + PE5: (pe5, 5, [0, 1, 2, 3]), + PE6: (pe6, 6, [0, 1]), + PE7: (pe7, 7, [1, 2]), + PE8: (pe8, 8, [1, 2]), + PE9: (pe9, 9, [1, 2]), + PE10: (pe10, 10, [1, 2]), + PE11: (pe11, 11, [1, 2]), + PE12: (pe12, 12, [1, 2]), + PE13: (pe13, 13, [1, 2]), + PE14: (pe14, 14, [1, 2, 6]), + PE15: (pe15, 15, [1, 2, 7]), +]); + +#[cfg(feature = "gpio-f303")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 6]), + PF1: (pf1, 1, [4]), + PF2: (pf2, 2, [1]), + PF4: (pf4, 4, [1, 2]), + PF6: (pf6, 6, [1, 2, 4, 7]), + PF9: (pf9, 9, [1, 3, 5]), + PF10: (pf10, 10, [1, 3, 5]), +]); + +#[cfg(feature = "gpio-f333")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 3, 7, 15]), + PA1: (pa1, 1, [1, 3, 7, 9, 15]), + PA2: (pa2, 2, [1, 3, 7, 8, 9, 15]), + PA3: (pa3, 3, [1, 3, 7, 9, 15]), + PA4: (pa4, 4, [2, 3, 5, 7, 15]), + PA5: (pa5, 5, [1, 3, 5, 15]), + PA6: (pa6, 6, [1, 2, 3, 5, 6, 13, 15]), + PA7: (pa7, 7, [1, 2, 3, 5, 6, 15]), + PA8: (pa8, 8, [0, 6, 7, 13, 15]), + PA9: (pa9, 9, [3, 6, 7, 9, 10, 13, 15]), + PA10: (pa10, 10, [1, 3, 6, 7, 8, 10, 13, 15]), + PA11: (pa11, 11, [6, 7, 9, 11, 12, 13, 15]), + PA12: (pa12, 12, [1, 6, 7, 8, 9, 11, 13, 15]), + PA13: (pa13, 13, [0, 1, 3, 5, 7, 15], super::Debugger), + PA14: (pa14, 14, [0, 3, 4, 6, 7, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 3, 4, 5, 7, 9, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-f333")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 3, 6, 15]), + PB1: (pb1, 1, [2, 3, 6, 8, 13, 15]), + PB2: (pb2, 2, [3, 13, 15]), + PB3: (pb3, 3, [0, 1, 3, 5, 7, 10, 12, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 5, 7, 10, 13, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 4, 5, 7, 10, 13, 15]), + PB6: (pb6, 6, [1, 3, 4, 7, 12, 13, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 10, 13, 15]), + PB8: (pb8, 8, [1, 3, 4, 7, 9, 12, 13, 15]), + PB9: (pb9, 9, [1, 4, 6, 7, 8, 9, 13, 15]), + PB10: (pb10, 10, [1, 3, 7, 13, 15]), + PB11: (pb11, 11, [1, 3, 7, 13, 15]), + PB12: (pb12, 12, [3, 6, 7, 13, 15]), + PB13: (pb13, 13, [3, 6, 7, 13, 15]), + PB14: (pb14, 14, [1, 3, 6, 7, 13, 15]), + PB15: (pb15, 15, [1, 2, 4, 13, 15]), +]); + +#[cfg(feature = "gpio-f333")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2]), + PC1: (pc1, 1, [1, 2]), + PC2: (pc2, 2, [1, 2]), + PC3: (pc3, 3, [1, 2, 6]), + PC4: (pc4, 4, [1, 2, 7]), + PC5: (pc5, 5, [1, 2, 3, 7]), + PC6: (pc6, 6, [1, 2, 3, 7]), + PC7: (pc7, 7, [1, 2, 3]), + PC8: (pc8, 8, [1, 2, 3]), + PC9: (pc9, 9, [1, 2, 3]), + PC10: (pc10, 10, [1, 7]), + PC11: (pc11, 11, [1, 3, 7]), + PC12: (pc12, 12, [1, 3, 7]), + PC13: (pc13, 13, [4]), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f333")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD2: (pd2, 2, [1, 2]), +]); + +#[cfg(feature = "gpio-f333")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [6]), + PF1: (pf1, 1, []), +]); + +#[cfg(feature = "gpio-f373")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 11, 15]), + PA1: (pa1, 1, [0, 1, 2, 3, 6, 7, 9, 11, 15]), + PA2: (pa2, 2, [1, 2, 3, 6, 7, 8, 9, 11, 15]), + PA3: (pa3, 3, [1, 2, 3, 6, 7, 9, 11, 15]), + PA4: (pa4, 4, [2, 3, 5, 6, 7, 10, 15]), + PA5: (pa5, 5, [1, 3, 5, 7, 9, 10, 15]), + PA6: (pa6, 6, [1, 2, 3, 5, 8, 9, 15]), + PA7: (pa7, 7, [1, 2, 3, 5, 8, 9, 15]), + PA8: (pa8, 8, [0, 2, 4, 5, 7, 10, 15]), + PA9: (pa9, 9, [2, 3, 4, 5, 7, 9, 10, 15]), + PA10: (pa10, 10, [1, 3, 4, 5, 7, 9, 10, 15]), + PA11: (pa11, 11, [2, 5, 6, 7, 8, 9, 10, 14, 15]), + PA12: (pa12, 12, [1, 2, 6, 7, 8, 9, 10, 14, 15]), + PA13: (pa13, 13, [0, 1, 2, 3, 5, 6, 7, 10, 15], super::Debugger), + PA14: (pa14, 14, [0, 3, 4, 10, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 3, 4, 5, 6, 10, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-f373")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 3, 5, 10, 15]), + PB1: (pb1, 1, [2, 3, 15]), + PB2: (pb2, 2, [15]), + PB3: (pb3, 3, [0, 1, 2, 3, 5, 6, 7, 9, 10, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 5, 6, 7, 9, 10, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 4, 5, 6, 7, 10, 11, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 7, 9, 10, 11, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 7, 9, 10, 11, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15]), + PB9: (pb9, 9, [1, 2, 4, 5, 6, 7, 8, 9, 11, 15]), + PB10: (pb10, 10, [1, 3, 5, 6, 7, 15]), + PB14: (pb14, 14, [1, 3, 5, 7, 9, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 5, 9, 15]), +]); + +#[cfg(feature = "gpio-f373")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2]), + PC1: (pc1, 1, [1, 2]), + PC2: (pc2, 2, [1, 2, 5]), + PC3: (pc3, 3, [1, 2, 5]), + PC4: (pc4, 4, [1, 2, 3, 7]), + PC5: (pc5, 5, [1, 3, 7]), + PC6: (pc6, 6, [1, 2, 5]), + PC7: (pc7, 7, [1, 2, 5]), + PC8: (pc8, 8, [1, 2, 5]), + PC9: (pc9, 9, [1, 2, 5]), + PC10: (pc10, 10, [1, 2, 6, 7]), + PC11: (pc11, 11, [1, 2, 6, 7]), + PC12: (pc12, 12, [1, 2, 6, 7]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f373")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [1, 2, 7]), + PD1: (pd1, 1, [1, 2, 7]), + PD2: (pd2, 2, [1, 2]), + PD3: (pd3, 3, [1, 5, 7]), + PD4: (pd4, 4, [1, 5, 7]), + PD5: (pd5, 5, [1, 7]), + PD6: (pd6, 6, [1, 5, 7]), + PD7: (pd7, 7, [1, 5, 7]), + PD8: (pd8, 8, [1, 3, 5, 7]), + PD9: (pd9, 9, [1, 3, 7]), + PD10: (pd10, 10, [1, 7]), + PD11: (pd11, 11, [1, 7]), + PD12: (pd12, 12, [1, 2, 3, 7]), + PD13: (pd13, 13, [1, 2, 3]), + PD14: (pd14, 14, [1, 2, 3]), + PD15: (pd15, 15, [1, 2, 3]), +]); + +#[cfg(feature = "gpio-f373")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2, 7]), + PE1: (pe1, 1, [1, 7]), + PE2: (pe2, 2, [0, 1, 3]), + PE3: (pe3, 3, [0, 1, 3]), + PE4: (pe4, 4, [0, 1, 3]), + PE5: (pe5, 5, [0, 1, 3]), + PE6: (pe6, 6, [0, 1]), + PE7: (pe7, 7, [1]), + PE8: (pe8, 8, [1]), + PE9: (pe9, 9, [1]), + PE10: (pe10, 10, [1]), + PE11: (pe11, 11, [1]), + PE12: (pe12, 12, [1]), + PE13: (pe13, 13, [1]), + PE14: (pe14, 14, [1]), + PE15: (pe15, 15, [1, 7]), +]); + +#[cfg(feature = "gpio-f373")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4]), + PF1: (pf1, 1, [4]), + PF2: (pf2, 2, [1, 4]), + PF4: (pf4, 4, [1]), + PF6: (pf6, 6, [1, 2, 4, 5, 7]), + PF7: (pf7, 7, [1, 4, 7]), + PF9: (pf9, 9, [1, 2]), + PF10: (pf10, 10, [1]), +]); diff --git a/src/gpio/f7.rs b/src/gpio/f7.rs new file mode 100644 index 00000000..06ee95b2 --- /dev/null +++ b/src/gpio/f7.rs @@ -0,0 +1,605 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Input as DefaultMode; + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 10]), + PA1: (pa1, 1, [1, 2, 7, 8, 9, 10]), + PA2: (pa2, 2, [1, 2, 3, 7, 8]), + PA3: (pa3, 3, [1, 2, 3, 7, 10]), + PA4: (pa4, 4, [5, 6, 7, 12]), + PA5: (pa5, 5, [1, 3, 5, 10]), + PA6: (pa6, 6, [1, 2, 3, 5, 9]), + PA7: (pa7, 7, [1, 2, 3, 5, 9, 12]), + PA8: (pa8, 8, [0, 1, 3, 4, 7, 10]), + PA9: (pa9, 9, [1, 4, 5, 7]), + PA10: (pa10, 10, [1, 7, 10]), + PA11: (pa11, 11, [1, 7, 9, 10]), + PA12: (pa12, 12, [1, 7, 8, 9, 10]), + PA13: (pa13, 13, [0], super::Debugger), + PA14: (pa14, 14, [0], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 6, 8], super::Debugger), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 8, 10]), + PB1: (pb1, 1, [1, 2, 3, 10]), + PB2: (pb2, 2, [6, 7, 9]), + PB3: (pb3, 3, [0, 1, 5, 6, 10], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 7, 10], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 10, 12]), + PB6: (pb6, 6, [2, 4, 7, 10, 12]), + PB7: (pb7, 7, [2, 4, 7, 12]), + PB8: (pb8, 8, [2, 3, 4, 9, 10, 12]), + PB9: (pb9, 9, [2, 3, 4, 5, 9, 10, 12]), + PB10: (pb10, 10, [1, 4, 5, 7, 10]), + PB11: (pb11, 11, [1, 4, 7, 10]), + PB12: (pb12, 12, [1, 4, 5, 7, 10, 12]), + PB13: (pb13, 13, [1, 5, 7, 10]), + PB14: (pb14, 14, [1, 3, 5, 7, 9, 10, 12]), + PB15: (pb15, 15, [0, 1, 3, 5, 9, 10, 12]), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [8, 10, 12]), + PC1: (pc1, 1, [0, 5, 6]), + PC2: (pc2, 2, [5, 10, 12]), + PC3: (pc3, 3, [5, 10, 12]), + PC4: (pc4, 4, [5, 12]), + PC5: (pc5, 5, [12]), + PC6: (pc6, 6, [2, 3, 5, 8, 10, 12]), + PC7: (pc7, 7, [2, 3, 6, 8, 10, 12]), + PC8: (pc8, 8, [0, 2, 3, 7, 8, 12]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 7, 9, 12]), + PC10: (pc10, 10, [6, 7, 8, 9, 12]), + PC11: (pc11, 11, [6, 7, 8, 9, 12]), + PC12: (pc12, 12, [0, 6, 7, 8, 12]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [9, 12]), + PD1: (pd1, 1, [9, 12]), + PD2: (pd2, 2, [0, 2, 8, 12]), + PD3: (pd3, 3, [5, 7, 12]), + PD4: (pd4, 4, [7, 12]), + PD5: (pd5, 5, [7, 12]), + PD6: (pd6, 6, [5, 6, 7, 11, 12]), + PD7: (pd7, 7, [7, 11, 12]), + PD8: (pd8, 8, [7, 12]), + PD9: (pd9, 9, [7, 12]), + PD10: (pd10, 10, [7, 12]), + PD11: (pd11, 11, [7, 9, 10, 12]), + PD12: (pd12, 12, [2, 3, 7, 9, 10, 12]), + PD13: (pd13, 13, [2, 3, 9, 10, 12]), + PD14: (pd14, 14, [2, 8, 12]), + PD15: (pd15, 15, [2, 8, 12]), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 8, 10, 12]), + PE1: (pe1, 1, [3, 8, 12]), + PE2: (pe2, 2, [0, 5, 6, 9, 12]), + PE3: (pe3, 3, [0, 6, 12]), + PE4: (pe4, 4, [0, 5, 6, 12]), + PE5: (pe5, 5, [0, 3, 5, 6, 12]), + PE6: (pe6, 6, [0, 1, 3, 5, 6, 10, 12]), + PE7: (pe7, 7, [1, 8, 10, 12]), + PE8: (pe8, 8, [1, 8, 10, 12]), + PE9: (pe9, 9, [1, 8, 10, 12]), + PE10: (pe10, 10, [1, 8, 10, 12]), + PE11: (pe11, 11, [1, 5, 10, 12]), + PE12: (pe12, 12, [1, 5, 10, 12]), + PE13: (pe13, 13, [1, 5, 10, 12]), + PE14: (pe14, 14, [1, 5, 10, 12]), + PE15: (pe15, 15, [1, 12]), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12]), + PF1: (pf1, 1, [4, 12]), + PF2: (pf2, 2, [4, 12]), + PF3: (pf3, 3, [12]), + PF4: (pf4, 4, [12]), + PF5: (pf5, 5, [12]), + PF6: (pf6, 6, [3, 5, 6, 8, 9]), + PF7: (pf7, 7, [3, 5, 6, 8, 9]), + PF8: (pf8, 8, [5, 6, 8, 9, 10]), + PF9: (pf9, 9, [5, 6, 8, 9, 10]), + PF10: (pf10, 10, []), + PF11: (pf11, 11, [5, 10, 12]), + PF12: (pf12, 12, [12]), + PF13: (pf13, 13, [12]), + PF14: (pf14, 14, [12]), + PF15: (pf15, 15, [12]), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [12]), + PG1: (pg1, 1, [12]), + PG2: (pg2, 2, [12]), + PG3: (pg3, 3, [12]), + PG4: (pg4, 4, [12]), + PG5: (pg5, 5, [12]), + PG6: (pg6, 6, []), + PG7: (pg7, 7, [8, 12]), + PG8: (pg8, 8, [8, 12]), + PG9: (pg9, 9, [8, 9, 10, 11, 12]), + PG10: (pg10, 10, [10, 11, 12]), + PG11: (pg11, 11, [10, 12]), + PG12: (pg12, 12, [3, 8, 11, 12]), + PG13: (pg13, 13, [0, 3, 8, 12]), + PG14: (pg14, 14, [0, 3, 8, 9, 12]), + PG15: (pg15, 15, [8, 12]), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, []), + PH1: (ph1, 1, []), + PH2: (ph2, 2, [3, 9, 10, 12]), + PH3: (ph3, 3, [9, 10, 12]), + PH4: (ph4, 4, [4, 10]), + PH5: (ph5, 5, [4, 5, 12]), + PH6: (ph6, 6, [4, 5, 9, 12]), + PH7: (ph7, 7, [4, 5, 12]), + PH8: (ph8, 8, [4, 12]), + PH9: (ph9, 9, [4, 9, 12]), + PH10: (ph10, 10, [2, 12]), + PH11: (ph11, 11, [2, 12]), + PH12: (ph12, 12, [2, 12]), + PH13: (ph13, 13, [3, 8, 9, 12]), + PH14: (ph14, 14, [3, 8, 9, 12]), + PH15: (ph15, 15, [3, 12]), +]); + +#[cfg(feature = "gpio-f72x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 12]), + PI1: (pi1, 1, [3, 5, 12]), + PI2: (pi2, 2, [3, 5, 12]), + PI3: (pi3, 3, [3, 5, 12]), + PI4: (pi4, 4, [3, 10, 12]), + PI5: (pi5, 5, [3, 10, 12]), + PI6: (pi6, 6, [3, 10, 12]), + PI7: (pi7, 7, [3, 10, 12]), + PI8: (pi8, 8, []), + PI9: (pi9, 9, [8, 9, 12]), + PI10: (pi10, 10, [12]), + PI11: (pi11, 11, [10]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 10, 11]), + PA1: (pa1, 1, [1, 2, 7, 8, 9, 10, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 7, 8, 11, 14]), + PA3: (pa3, 3, [1, 2, 3, 7, 10, 11, 14]), + PA4: (pa4, 4, [5, 6, 7, 12, 13, 14]), + PA5: (pa5, 5, [1, 3, 5, 10, 14]), + PA6: (pa6, 6, [1, 2, 3, 5, 9, 13, 14]), + PA7: (pa7, 7, [1, 2, 3, 5, 9, 11, 12]), + PA8: (pa8, 8, [0, 1, 3, 4, 7, 10, 14]), + PA9: (pa9, 9, [1, 4, 5, 7, 13]), + PA10: (pa10, 10, [1, 7, 10, 13]), + PA11: (pa11, 11, [1, 7, 9, 10, 14]), + PA12: (pa12, 12, [1, 7, 8, 9, 10, 14]), + PA13: (pa13, 13, [0], super::Debugger), + PA14: (pa14, 14, [0], super::Debugger), + PA15: (pa15, 15, [0, 1, 4, 5, 6, 8], super::Debugger), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 8, 9, 10, 11]), + PB1: (pb1, 1, [1, 2, 3, 9, 10, 11]), + PB2: (pb2, 2, [6, 7, 9]), + PB3: (pb3, 3, [0, 1, 5, 6], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 7], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 9, 10, 11, 12, 13]), + PB6: (pb6, 6, [2, 3, 4, 7, 9, 10, 12, 13]), + PB7: (pb7, 7, [2, 4, 7, 12, 13]), + PB8: (pb8, 8, [2, 3, 4, 9, 11, 12, 13, 14]), + PB9: (pb9, 9, [2, 3, 4, 5, 9, 12, 13, 14]), + PB10: (pb10, 10, [1, 4, 5, 7, 10, 11, 14]), + PB11: (pb11, 11, [1, 4, 7, 10, 11, 14]), + PB12: (pb12, 12, [1, 4, 5, 7, 9, 10, 11, 12]), + PB13: (pb13, 13, [1, 5, 7, 9, 10, 11]), + PB14: (pb14, 14, [1, 3, 5, 7, 9, 12]), + PB15: (pb15, 15, [0, 1, 3, 5, 9, 12]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [8, 10, 12, 14]), + PC1: (pc1, 1, [0, 5, 6, 11]), + PC2: (pc2, 2, [5, 10, 11, 12]), + PC3: (pc3, 3, [5, 10, 11, 12]), + PC4: (pc4, 4, [5, 8, 11, 12]), + PC5: (pc5, 5, [8, 11, 12]), + PC6: (pc6, 6, [2, 3, 5, 8, 12, 13, 14]), + PC7: (pc7, 7, [2, 3, 6, 8, 12, 13, 14]), + PC8: (pc8, 8, [0, 2, 3, 7, 8, 12, 13]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 7, 9, 12, 13]), + PC10: (pc10, 10, [6, 7, 8, 9, 12, 13, 14]), + PC11: (pc11, 11, [6, 7, 8, 9, 12, 13]), + PC12: (pc12, 12, [0, 6, 7, 8, 12, 13]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [9, 12]), + PD1: (pd1, 1, [9, 12]), + PD2: (pd2, 2, [0, 2, 8, 12, 13]), + PD3: (pd3, 3, [5, 7, 12, 13, 14]), + PD4: (pd4, 4, [7, 12]), + PD5: (pd5, 5, [7, 12]), + PD6: (pd6, 6, [5, 6, 7, 12, 13, 14]), + PD7: (pd7, 7, [7, 8, 12]), + PD8: (pd8, 8, [7, 8, 12]), + PD9: (pd9, 9, [7, 12]), + PD10: (pd10, 10, [7, 12, 14]), + PD11: (pd11, 11, [4, 7, 9, 10, 12]), + PD12: (pd12, 12, [2, 3, 4, 7, 9, 10, 12]), + PD13: (pd13, 13, [2, 3, 4, 9, 10, 12]), + PD14: (pd14, 14, [2, 8, 12]), + PD15: (pd15, 15, [2, 8, 12]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 8, 10, 12, 13]), + PE1: (pe1, 1, [3, 8, 12, 13]), + PE2: (pe2, 2, [0, 5, 6, 9, 11, 12]), + PE3: (pe3, 3, [0, 6, 12]), + PE4: (pe4, 4, [0, 5, 6, 12, 13, 14]), + PE5: (pe5, 5, [0, 3, 5, 6, 12, 13, 14]), + PE6: (pe6, 6, [0, 1, 3, 5, 6, 10, 12, 13, 14]), + PE7: (pe7, 7, [1, 8, 10, 12]), + PE8: (pe8, 8, [1, 8, 10, 12]), + PE9: (pe9, 9, [1, 8, 10, 12]), + PE10: (pe10, 10, [1, 8, 10, 12]), + PE11: (pe11, 11, [1, 5, 10, 12, 14]), + PE12: (pe12, 12, [1, 5, 10, 12, 14]), + PE13: (pe13, 13, [1, 5, 10, 12, 14]), + PE14: (pe14, 14, [1, 5, 10, 12, 14]), + PE15: (pe15, 15, [1, 12, 14]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12]), + PF1: (pf1, 1, [4, 12]), + PF2: (pf2, 2, [4, 12]), + PF3: (pf3, 3, [12]), + PF4: (pf4, 4, [12]), + PF5: (pf5, 5, [12]), + PF6: (pf6, 6, [3, 5, 6, 8, 9]), + PF7: (pf7, 7, [3, 5, 6, 8, 9]), + PF8: (pf8, 8, [5, 6, 8, 9, 10]), + PF9: (pf9, 9, [5, 6, 8, 9, 10]), + PF10: (pf10, 10, [13, 14]), + PF11: (pf11, 11, [5, 10, 12, 13]), + PF12: (pf12, 12, [12]), + PF13: (pf13, 13, [4, 12]), + PF14: (pf14, 14, [4, 12]), + PF15: (pf15, 15, [4, 12]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [12]), + PG1: (pg1, 1, [12]), + PG2: (pg2, 2, [12]), + PG3: (pg3, 3, [12]), + PG4: (pg4, 4, [12]), + PG5: (pg5, 5, [12]), + PG6: (pg6, 6, [13, 14]), + PG7: (pg7, 7, [8, 12, 13, 14]), + PG8: (pg8, 8, [5, 7, 8, 11, 12]), + PG9: (pg9, 9, [7, 8, 9, 10, 12, 13]), + PG10: (pg10, 10, [9, 10, 12, 13, 14]), + PG11: (pg11, 11, [7, 11, 13, 14]), + PG12: (pg12, 12, [3, 5, 7, 8, 9, 12, 14]), + PG13: (pg13, 13, [0, 3, 5, 8, 11, 12, 14]), + PG14: (pg14, 14, [0, 3, 5, 8, 9, 11, 12, 14]), + PG15: (pg15, 15, [8, 12, 13]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, []), + PH1: (ph1, 1, []), + PH2: (ph2, 2, [3, 9, 10, 11, 12, 14]), + PH3: (ph3, 3, [9, 10, 11, 12, 14]), + PH4: (ph4, 4, [4, 10]), + PH5: (ph5, 5, [4, 5, 12]), + PH6: (ph6, 6, [4, 5, 9, 11, 12, 13]), + PH7: (ph7, 7, [4, 5, 11, 12, 13]), + PH8: (ph8, 8, [4, 12, 13, 14]), + PH9: (ph9, 9, [4, 9, 12, 13, 14]), + PH10: (ph10, 10, [2, 4, 12, 13, 14]), + PH11: (ph11, 11, [2, 4, 12, 13, 14]), + PH12: (ph12, 12, [2, 4, 12, 13, 14]), + PH13: (ph13, 13, [3, 9, 12, 14]), + PH14: (ph14, 14, [3, 12, 13, 14]), + PH15: (ph15, 15, [3, 12, 13, 14]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 12, 13, 14]), + PI1: (pi1, 1, [3, 5, 12, 13, 14]), + PI2: (pi2, 2, [3, 5, 12, 13, 14]), + PI3: (pi3, 3, [3, 5, 12, 13]), + PI4: (pi4, 4, [3, 10, 12, 13, 14]), + PI5: (pi5, 5, [3, 10, 12, 13, 14]), + PI6: (pi6, 6, [3, 10, 12, 13, 14]), + PI7: (pi7, 7, [3, 10, 12, 13, 14]), + PI8: (pi8, 8, []), + PI9: (pi9, 9, [9, 12, 14]), + PI10: (pi10, 10, [11, 12, 14]), + PI11: (pi11, 11, [10]), + PI12: (pi12, 12, [14]), + PI13: (pi13, 13, [14]), + PI14: (pi14, 14, [14]), + PI15: (pi15, 15, [14]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOJ, gpioj, PJ, 'J', PJn, [ + PJ0: (pj0, 0, [14]), + PJ1: (pj1, 1, [14]), + PJ2: (pj2, 2, [14]), + PJ3: (pj3, 3, [14]), + PJ4: (pj4, 4, [14]), + PJ5: (pj5, 5, [14]), + PJ6: (pj6, 6, [14]), + PJ7: (pj7, 7, [14]), + PJ8: (pj8, 8, [14]), + PJ9: (pj9, 9, [14]), + PJ10: (pj10, 10, [14]), + PJ11: (pj11, 11, [14]), + PJ12: (pj12, 12, [14]), + PJ13: (pj13, 13, [14]), + PJ14: (pj14, 14, [14]), + PJ15: (pj15, 15, [14]), +]); + +#[cfg(feature = "gpio-f746")] +gpio!(GPIOK, gpiok, PK, 'K', PKn, [ + PK0: (pk0, 0, [14]), + PK1: (pk1, 1, [14]), + PK2: (pk2, 2, [14]), + PK3: (pk3, 3, [14]), + PK4: (pk4, 4, [14]), + PK5: (pk5, 5, [14]), + PK6: (pk6, 6, [14]), + PK7: (pk7, 7, [14]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 10, 11]), + PA1: (pa1, 1, [1, 2, 7, 8, 9, 10, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 7, 8, 11, 12, 14]), + PA3: (pa3, 3, [1, 2, 3, 7, 9, 10, 11, 14]), + PA4: (pa4, 4, [5, 6, 7, 8, 12, 13, 14]), + PA5: (pa5, 5, [1, 3, 5, 8, 10, 14]), + PA6: (pa6, 6, [1, 2, 3, 5, 8, 9, 12, 13, 14]), + PA7: (pa7, 7, [1, 2, 3, 5, 8, 9, 11, 12]), + PA8: (pa8, 8, [0, 1, 3, 4, 7, 10, 11, 12, 13, 14]), + PA9: (pa9, 9, [1, 4, 5, 7, 13, 14]), + PA10: (pa10, 10, [1, 7, 9, 10, 12, 13, 14]), + PA11: (pa11, 11, [1, 5, 6, 7, 9, 10, 14]), + PA12: (pa12, 12, [1, 5, 6, 7, 8, 9, 10, 14]), + PA13: (pa13, 13, [0], super::Debugger), + PA14: (pa14, 14, [0], super::Debugger), + PA15: (pa15, 15, [0, 1, 4, 5, 6, 7, 8, 11, 12], super::Debugger), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 6, 8, 9, 10, 11, 14]), + PB1: (pb1, 1, [1, 2, 3, 6, 9, 10, 11, 14]), + PB2: (pb2, 2, [6, 7, 9, 10]), + PB3: (pb3, 3, [0, 1, 5, 6, 8, 10, 11, 12], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 7, 8, 10, 11, 12], super::Debugger), + PB5: (pb5, 5, [1, 2, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14]), + PB6: (pb6, 6, [1, 2, 3, 4, 6, 7, 9, 10, 11, 12, 13]), + PB7: (pb7, 7, [2, 4, 6, 7, 11, 12, 13]), + PB8: (pb8, 8, [1, 2, 3, 4, 6, 7, 9, 10, 11, 12, 13, 14]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14]), + PB10: (pb10, 10, [1, 4, 5, 6, 7, 9, 10, 11, 14]), + PB11: (pb11, 11, [1, 4, 6, 7, 10, 11, 13, 14]), + PB12: (pb12, 12, [1, 4, 5, 6, 7, 8, 9, 10, 11, 12]), + PB13: (pb13, 13, [1, 5, 6, 7, 8, 9, 10, 11]), + PB14: (pb14, 14, [1, 3, 4, 5, 6, 7, 8, 9, 10, 12]), + PB15: (pb15, 15, [0, 1, 3, 4, 5, 6, 8, 9, 10, 12]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [3, 6, 8, 10, 12, 14]), + PC1: (pc1, 1, [0, 3, 5, 6, 10, 11, 12]), + PC2: (pc2, 2, [3, 5, 6, 10, 11, 12]), + PC3: (pc3, 3, [3, 5, 10, 11, 12]), + PC4: (pc4, 4, [3, 5, 8, 11, 12]), + PC5: (pc5, 5, [3, 8, 11, 12]), + PC6: (pc6, 6, [2, 3, 5, 7, 8, 9, 10, 12, 13, 14]), + PC7: (pc7, 7, [2, 3, 6, 7, 8, 9, 10, 12, 13, 14]), + PC8: (pc8, 8, [0, 2, 3, 7, 8, 9, 12, 13]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 7, 9, 10, 12, 13, 14]), + PC10: (pc10, 10, [3, 6, 7, 8, 9, 12, 13, 14]), + PC11: (pc11, 11, [3, 6, 7, 8, 9, 12, 13]), + PC12: (pc12, 12, [0, 6, 7, 8, 12, 13]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 6, 8, 9, 12]), + PD1: (pd1, 1, [3, 6, 8, 9, 12]), + PD2: (pd2, 2, [0, 2, 8, 12, 13]), + PD3: (pd3, 3, [3, 5, 6, 7, 12, 13, 14]), + PD4: (pd4, 4, [6, 7, 12]), + PD5: (pd5, 5, [7, 12]), + PD6: (pd6, 6, [3, 5, 6, 7, 10, 11, 12, 13, 14]), + PD7: (pd7, 7, [3, 5, 6, 7, 8, 11, 12]), + PD8: (pd8, 8, [3, 7, 8, 12]), + PD9: (pd9, 9, [3, 7, 12]), + PD10: (pd10, 10, [3, 7, 12, 14]), + PD11: (pd11, 11, [4, 7, 9, 10, 12]), + PD12: (pd12, 12, [2, 3, 4, 7, 9, 10, 12]), + PD13: (pd13, 13, [2, 3, 4, 9, 10, 12]), + PD14: (pd14, 14, [2, 8, 12]), + PD15: (pd15, 15, [2, 8, 12]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 8, 10, 12, 13]), + PE1: (pe1, 1, [3, 8, 12, 13]), + PE2: (pe2, 2, [0, 5, 6, 9, 11, 12]), + PE3: (pe3, 3, [0, 6, 12]), + PE4: (pe4, 4, [0, 5, 6, 10, 12, 13, 14]), + PE5: (pe5, 5, [0, 3, 5, 6, 10, 12, 13, 14]), + PE6: (pe6, 6, [0, 1, 3, 5, 6, 10, 12, 13, 14]), + PE7: (pe7, 7, [1, 6, 8, 10, 12]), + PE8: (pe8, 8, [1, 6, 8, 10, 12]), + PE9: (pe9, 9, [1, 6, 8, 10, 12]), + PE10: (pe10, 10, [1, 6, 8, 10, 12]), + PE11: (pe11, 11, [1, 5, 6, 10, 12, 14]), + PE12: (pe12, 12, [1, 5, 6, 10, 12, 14]), + PE13: (pe13, 13, [1, 5, 6, 10, 12, 14]), + PE14: (pe14, 14, [1, 5, 10, 12, 14]), + PE15: (pe15, 15, [1, 12, 14]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12]), + PF1: (pf1, 1, [4, 12]), + PF2: (pf2, 2, [4, 12]), + PF3: (pf3, 3, [12]), + PF4: (pf4, 4, [12]), + PF5: (pf5, 5, [12]), + PF6: (pf6, 6, [3, 5, 6, 8, 9]), + PF7: (pf7, 7, [3, 5, 6, 8, 9]), + PF8: (pf8, 8, [5, 6, 8, 9, 10]), + PF9: (pf9, 9, [5, 6, 8, 9, 10]), + PF10: (pf10, 10, [9, 13, 14]), + PF11: (pf11, 11, [5, 10, 12, 13]), + PF12: (pf12, 12, [12]), + PF13: (pf13, 13, [4, 6, 12]), + PF14: (pf14, 14, [4, 6, 12]), + PF15: (pf15, 15, [4, 12]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [12]), + PG1: (pg1, 1, [12]), + PG2: (pg2, 2, [12]), + PG3: (pg3, 3, [12]), + PG4: (pg4, 4, [12]), + PG5: (pg5, 5, [12]), + PG6: (pg6, 6, [12, 13, 14]), + PG7: (pg7, 7, [6, 8, 12, 13, 14]), + PG8: (pg8, 8, [5, 7, 8, 11, 12, 14]), + PG9: (pg9, 9, [5, 7, 8, 9, 10, 11, 12, 13]), + PG10: (pg10, 10, [5, 9, 10, 11, 12, 13, 14]), + PG11: (pg11, 11, [5, 7, 10, 11, 13, 14]), + PG12: (pg12, 12, [3, 5, 7, 8, 9, 11, 12, 14]), + PG13: (pg13, 13, [0, 3, 5, 8, 11, 12, 14]), + PG14: (pg14, 14, [0, 3, 5, 8, 9, 11, 12, 14]), + PG15: (pg15, 15, [8, 12, 13]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, []), + PH1: (ph1, 1, []), + PH2: (ph2, 2, [3, 9, 10, 11, 12, 14]), + PH3: (ph3, 3, [9, 10, 11, 12, 14]), + PH4: (ph4, 4, [4, 9, 10, 14]), + PH5: (ph5, 5, [4, 5, 12]), + PH6: (ph6, 6, [4, 5, 9, 11, 12, 13]), + PH7: (ph7, 7, [4, 5, 11, 12, 13]), + PH8: (ph8, 8, [4, 12, 13, 14]), + PH9: (ph9, 9, [4, 9, 12, 13, 14]), + PH10: (ph10, 10, [2, 4, 12, 13, 14]), + PH11: (ph11, 11, [2, 4, 12, 13, 14]), + PH12: (ph12, 12, [2, 4, 12, 13, 14]), + PH13: (ph13, 13, [3, 8, 9, 12, 14]), + PH14: (ph14, 14, [3, 8, 9, 12, 13, 14]), + PH15: (ph15, 15, [3, 12, 13, 14]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 12, 13, 14]), + PI1: (pi1, 1, [3, 5, 12, 13, 14]), + PI2: (pi2, 2, [3, 5, 12, 13, 14]), + PI3: (pi3, 3, [3, 5, 12, 13]), + PI4: (pi4, 4, [3, 10, 12, 13, 14]), + PI5: (pi5, 5, [3, 10, 12, 13, 14]), + PI6: (pi6, 6, [3, 10, 12, 13, 14]), + PI7: (pi7, 7, [3, 10, 12, 13, 14]), + PI8: (pi8, 8, []), + PI9: (pi9, 9, [8, 9, 12, 14]), + PI10: (pi10, 10, [11, 12, 14]), + PI11: (pi11, 11, [9, 10]), + PI12: (pi12, 12, [14]), + PI13: (pi13, 13, [14]), + PI14: (pi14, 14, [14]), + PI15: (pi15, 15, [9, 14]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOJ, gpioj, PJ, 'J', PJn, [ + PJ0: (pj0, 0, [9, 14]), + PJ1: (pj1, 1, [14]), + PJ2: (pj2, 2, [13, 14]), + PJ3: (pj3, 3, [14]), + PJ4: (pj4, 4, [14]), + PJ5: (pj5, 5, [14]), + PJ6: (pj6, 6, [14]), + PJ7: (pj7, 7, [14]), + PJ8: (pj8, 8, [14]), + PJ9: (pj9, 9, [14]), + PJ10: (pj10, 10, [14]), + PJ11: (pj11, 11, [14]), + PJ12: (pj12, 12, [9, 14]), + PJ13: (pj13, 13, [9, 14]), + PJ14: (pj14, 14, [14]), + PJ15: (pj15, 15, [14]), +]); + +#[cfg(feature = "gpio-f76x")] +gpio!(GPIOK, gpiok, PK, 'K', PKn, [ + PK0: (pk0, 0, [14]), + PK1: (pk1, 1, [14]), + PK2: (pk2, 2, [14]), + PK3: (pk3, 3, [14]), + PK4: (pk4, 4, [14]), + PK5: (pk5, 5, [14]), + PK6: (pk6, 6, [14]), + PK7: (pk7, 7, [14]), +]); diff --git a/src/gpio/g0.rs b/src/gpio/g0.rs new file mode 100644 index 00000000..98afd4eb --- /dev/null +++ b/src/gpio/g0.rs @@ -0,0 +1,355 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-g03x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 5]), + PA1: (pa1, 1, [0, 1, 2, 6, 7]), + PA2: (pa2, 2, [0, 1, 2, 6]), + PA3: (pa3, 3, [0, 1, 2, 6, 7]), + PA4: (pa4, 4, [0, 1, 4, 5, 7]), + PA5: (pa5, 5, [0, 2, 5, 7]), + PA6: (pa6, 6, [0, 1, 2, 5, 6]), + PA7: (pa7, 7, [0, 1, 2, 4, 5]), + PA8: (pa8, 8, [0, 1, 2, 5, 7]), + PA9: (pa9, 9, [0, 1, 2, 4, 5, 6, 7]), + PA10: (pa10, 10, [0, 1, 2, 5, 6, 7]), + PA11: (pa11, 11, [0, 1, 2, 5, 6]), + PA12: (pa12, 12, [0, 1, 2, 5, 6]), + PA13: (pa13, 13, [0, 1, 7], super::Debugger), + PA14: (pa14, 14, [0, 1, 7], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 7], super::Debugger), +]); + +#[cfg(feature = "gpio-g03x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 5]), + PB1: (pb1, 1, [0, 1, 2, 5, 6, 7]), + PB2: (pb2, 2, [1, 5, 7]), + PB3: (pb3, 3, [0, 1, 2, 4, 7], super::Debugger), + PB4: (pb4, 4, [0, 1, 4, 5, 7], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 5, 6]), + PB6: (pb6, 6, [0, 1, 2, 4, 5, 6, 7]), + PB7: (pb7, 7, [0, 1, 2, 5, 6, 7]), + PB8: (pb8, 8, [1, 2, 6, 7]), + PB9: (pb9, 9, [0, 2, 5, 6, 7]), + PB10: (pb10, 10, [1, 2, 5, 6]), + PB11: (pb11, 11, [0, 1, 2, 6]), + PB12: (pb12, 12, [0, 1, 2, 7]), + PB13: (pb13, 13, [0, 1, 2, 6, 7]), + PB14: (pb14, 14, [0, 2, 6, 7]), + PB15: (pb15, 15, [0, 2, 7]), +]); + +#[cfg(feature = "gpio-g03x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC6: (pc6, 6, [1, 2]), + PC7: (pc7, 7, [1, 2]), + PC13: (pc13, 13, [2]), + PC14: (pc14, 14, [2]), + PC15: (pc15, 15, [0, 1]), +]); + +#[cfg(feature = "gpio-g03x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1, 2]), + PD1: (pd1, 1, [0, 1, 2]), + PD2: (pd2, 2, [1, 2]), + PD3: (pd3, 3, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-g03x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [2]), + PF1: (pf1, 1, [0]), + PF2: (pf2, 2, [0]), +]); +/* +#[cfg(feature = "gpio-g03x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-g05x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 5, 7]), + PA1: (pa1, 1, [0, 1, 2, 5, 6, 7]), + PA2: (pa2, 2, [0, 1, 2, 5, 6, 7]), + PA3: (pa3, 3, [0, 1, 2, 5, 6, 7]), + PA4: (pa4, 4, [0, 1, 4, 5, 7]), + PA5: (pa5, 5, [0, 2, 5, 7]), + PA6: (pa6, 6, [0, 1, 2, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 2, 4, 5, 7]), + PA8: (pa8, 8, [0, 1, 2, 5, 7]), + PA9: (pa9, 9, []), + PA10: (pa10, 10, []), + PA11: (pa11, 11, [0, 1, 2, 5, 6, 7]), + PA12: (pa12, 12, [0, 1, 2, 5, 6, 7]), + PA13: (pa13, 13, [0, 1, 7], super::Debugger), + PA14: (pa14, 14, [0, 1, 7], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 7], super::Debugger), +]); + +#[cfg(feature = "gpio-g05x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 5, 7]), + PB1: (pb1, 1, [0, 1, 2, 5, 6, 7]), + PB2: (pb2, 2, [1, 5, 7]), + PB3: (pb3, 3, [0, 1, 2, 4, 7], super::Debugger), + PB4: (pb4, 4, [0, 1, 4, 5, 7], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 5, 6, 7]), + PB6: (pb6, 6, [0, 1, 2, 4, 5, 6, 7]), + PB7: (pb7, 7, [0, 1, 2, 5, 6, 7]), + PB8: (pb8, 8, [1, 2, 5, 6, 7]), + PB9: (pb9, 9, [0, 2, 5, 6, 7]), + PB10: (pb10, 10, [1, 2, 5, 6, 7]), + PB11: (pb11, 11, [0, 1, 2, 6, 7]), + PB12: (pb12, 12, [0, 1, 2, 5, 7]), + PB13: (pb13, 13, [0, 1, 2, 5, 6, 7]), + PB14: (pb14, 14, [0, 2, 5, 6, 7]), + PB15: (pb15, 15, [0, 2, 4, 5, 7]), +]); + +#[cfg(feature = "gpio-g05x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC6: (pc6, 6, [1, 2]), + PC7: (pc7, 7, [1, 2]), + PC13: (pc13, 13, [2]), + PC14: (pc14, 14, [2]), + PC15: (pc15, 15, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-g05x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1, 2]), + PD1: (pd1, 1, [0, 1, 2]), + PD2: (pd2, 2, [1, 2]), + PD3: (pd3, 3, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-g05x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [2]), + PF1: (pf1, 1, [0, 2]), + PF2: (pf2, 2, [0]), +]); +/* +#[cfg(feature = "gpio-g05x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-g07x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 4, 5, 6, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5, 6, 7]), + PA2: (pa2, 2, [0, 1, 2, 4, 5, 6, 7]), + PA3: (pa3, 3, [0, 1, 2, 3, 4, 5, 6, 7]), + PA4: (pa4, 4, [0, 1, 4, 5, 6, 7]), + PA5: (pa5, 5, [0, 1, 2, 3, 4, 5, 6, 7]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6, 7]), + PA8: (pa8, 8, [0, 1, 2, 3, 5, 7]), + PA9: (pa9, 9, [0, 1, 2, 3, 4, 5, 6, 7]), + PA10: (pa10, 10, [0, 1, 2, 3, 5, 6, 7]), + PA11: (pa11, 11, [0, 1, 2, 5, 6, 7]), + PA12: (pa12, 12, [0, 1, 2, 5, 6, 7]), + PA13: (pa13, 13, [0, 1, 7], super::Debugger), + PA14: (pa14, 14, [0, 1, 7], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 4, 5, 7], super::Debugger), +]); + +#[cfg(feature = "gpio-g07x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 4, 5, 6, 7]), + PB1: (pb1, 1, [0, 1, 2, 4, 5, 6, 7]), + PB2: (pb2, 2, [1, 3, 4, 5, 7]), + PB3: (pb3, 3, [0, 1, 2, 4, 7], super::Debugger), + PB4: (pb4, 4, [0, 1, 3, 4, 5, 7], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 5, 6, 7]), + PB6: (pb6, 6, [0, 1, 2, 3, 4, 5, 6, 7]), + PB7: (pb7, 7, [0, 1, 2, 4, 5, 6, 7]), + PB8: (pb8, 8, [0, 1, 2, 3, 4, 5, 6, 7]), + PB9: (pb9, 9, [0, 1, 2, 3, 4, 5, 6, 7]), + PB10: (pb10, 10, [0, 1, 2, 3, 4, 5, 6, 7]), + PB11: (pb11, 11, [0, 1, 2, 3, 4, 6, 7]), + PB12: (pb12, 12, [0, 1, 2, 5, 6, 7]), + PB13: (pb13, 13, [0, 1, 2, 3, 4, 5, 6, 7]), + PB14: (pb14, 14, [0, 1, 2, 3, 4, 5, 6, 7]), + PB15: (pb15, 15, [0, 2, 4, 5, 7]), +]); + +#[cfg(feature = "gpio-g07x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 1, 2, 3]), + PC1: (pc1, 1, [0, 1, 2, 3]), + PC2: (pc2, 2, [0, 1, 2, 3]), + PC3: (pc3, 3, [0, 1, 2, 3]), + PC4: (pc4, 4, [0, 1, 2]), + PC5: (pc5, 5, [0, 1, 2, 3]), + PC6: (pc6, 6, [0, 1, 2, 3]), + PC7: (pc7, 7, [0, 1, 2, 3]), + PC8: (pc8, 8, [0, 1, 2, 3]), + PC9: (pc9, 9, [0, 1, 2, 3]), + PC10: (pc10, 10, [0, 1, 2, 3]), + PC11: (pc11, 11, [0, 1, 2, 3]), + PC12: (pc12, 12, [0, 1, 2]), + PC13: (pc13, 13, [2]), + PC14: (pc14, 14, [2]), + PC15: (pc15, 15, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-g07x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1, 2, 3]), + PD1: (pd1, 1, [0, 1, 2, 3]), + PD2: (pd2, 2, [0, 1, 2, 3]), + PD3: (pd3, 3, [0, 1, 2, 3]), + PD4: (pd4, 4, [0, 1, 2]), + PD5: (pd5, 5, [0, 1, 2]), + PD6: (pd6, 6, [0, 1, 2]), + PD8: (pd8, 8, [0, 1, 2, 3]), + PD9: (pd9, 9, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-g07x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [2]), + PF1: (pf1, 1, [0, 2]), + PF2: (pf2, 2, [0]), +]); +/* +#[cfg(feature = "gpio-g07x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 4, 5, 6, 7]), + PA1: (pa1, 1, [0, 1, 2, 4, 5, 6, 7]), + PA2: (pa2, 2, [0, 1, 2, 4, 5, 6, 7]), + PA3: (pa3, 3, [0, 1, 2, 4, 5, 6, 7]), + PA4: (pa4, 4, [0, 1, 2, 3, 4, 5, 6, 7, 9]), + PA5: (pa5, 5, [0, 1, 2, 3, 4, 5, 6, 7]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]), + PA8: (pa8, 8, [0, 1, 2, 4, 5, 7, 8]), + PA9: (pa9, 9, [0, 1, 2, 4, 5, 6, 7, 8]), + PA10: (pa10, 10, [0, 1, 2, 3, 5, 6, 7, 8]), + PA11: (pa11, 11, [0, 1, 2, 3, 5, 6, 7]), + PA12: (pa12, 12, [0, 1, 2, 3, 5, 6, 7]), + PA13: (pa13, 13, [0, 1, 2, 7, 10], super::Debugger), + PA14: (pa14, 14, [0, 1, 7, 10], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9], super::Debugger), +]); + +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3, 4, 5, 6, 7, 8, 10]), + PB1: (pb1, 1, [0, 1, 2, 3, 4, 5, 6, 7, 8, 10]), + PB2: (pb2, 2, [1, 3, 4, 5, 7]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 6, 7, 8, 9], super::Debugger), + PB4: (pb4, 4, [0, 1, 3, 4, 5, 6, 7, 8, 9], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3, 5, 6, 7, 8, 9]), + PB6: (pb6, 6, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10]), + PB7: (pb7, 7, [0, 1, 2, 4, 5, 6, 7, 9, 10]), + PB8: (pb8, 8, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]), + PB9: (pb9, 9, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9]), + PB10: (pb10, 10, [0, 1, 2, 4, 5, 6, 7]), + PB11: (pb11, 11, [0, 1, 2, 4, 6, 7]), + PB12: (pb12, 12, [0, 1, 2, 3, 5, 6, 7, 8]), + PB13: (pb13, 13, [0, 1, 2, 3, 4, 5, 6, 7]), + PB14: (pb14, 14, [0, 1, 2, 4, 5, 6, 7, 8]), + PB15: (pb15, 15, [0, 2, 4, 5, 7, 8]), +]); + +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 1, 2, 3, 4, 6, 7]), + PC1: (pc1, 1, [0, 1, 2, 3, 4, 6]), + PC2: (pc2, 2, [0, 1, 2, 3, 7]), + PC3: (pc3, 3, [0, 1, 2, 3]), + PC4: (pc4, 4, [0, 1, 2, 3]), + PC5: (pc5, 5, [0, 1, 2, 3]), + PC6: (pc6, 6, [0, 1, 2, 3]), + PC7: (pc7, 7, [0, 1, 2, 3]), + PC8: (pc8, 8, [0, 1, 2, 3]), + PC9: (pc9, 9, [0, 1, 2, 3, 6]), + PC10: (pc10, 10, [0, 1, 2, 4]), + PC11: (pc11, 11, [0, 1, 2, 4]), + PC12: (pc12, 12, [0, 1, 2, 3, 4]), + PC13: (pc13, 13, [2]), + PC14: (pc14, 14, [2]), + PC15: (pc15, 15, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1, 2, 3]), + PD1: (pd1, 1, [0, 1, 2, 3]), + PD2: (pd2, 2, [0, 1, 2, 3]), + PD3: (pd3, 3, [0, 1, 2, 3]), + PD4: (pd4, 4, [0, 1, 2, 3]), + PD5: (pd5, 5, [0, 1, 2, 3]), + PD6: (pd6, 6, [0, 1, 2]), + PD7: (pd7, 7, [3]), + PD8: (pd8, 8, [0, 1, 2]), + PD9: (pd9, 9, [0, 1, 2]), + PD10: (pd10, 10, [0]), + PD11: (pd11, 11, [0, 1]), + PD12: (pd12, 12, [0, 1, 2, 3]), + PD13: (pd13, 13, [1, 2, 3]), + PD14: (pd14, 14, [1, 2, 3]), + PD15: (pd15, 15, [0, 1, 2, 3]), +]); + +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [0, 1, 2]), + PE1: (pe1, 1, [0, 1]), + PE2: (pe2, 2, [1]), + PE3: (pe3, 3, [1]), + PE4: (pe4, 4, [1]), + PE5: (pe5, 5, [1]), + PE6: (pe6, 6, [1]), + PE7: (pe7, 7, [1, 3]), + PE8: (pe8, 8, [0, 1]), + PE9: (pe9, 9, [0, 1]), + PE10: (pe10, 10, [1, 3]), + PE11: (pe11, 11, [1, 3]), + PE12: (pe12, 12, [0, 1]), + PE13: (pe13, 13, [0, 1]), + PE14: (pe14, 14, [0, 1, 2]), + PE15: (pe15, 15, [0, 1]), +]); + +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [0, 1, 2]), + PF1: (pf1, 1, [0, 1, 2]), + PF2: (pf2, 2, [0, 1, 3]), + PF3: (pf3, 3, [1, 3]), + PF4: (pf4, 4, [1]), + PF5: (pf5, 5, [1]), + PF6: (pf6, 6, [1]), + PF7: (pf7, 7, [1, 3]), + PF8: (pf8, 8, []), + PF9: (pf9, 9, [3]), + PF10: (pf10, 10, [3]), + PF11: (pf11, 11, [3]), + PF12: (pf12, 12, [0, 3]), + PF13: (pf13, 13, [0]), +]); +/* +#[cfg(feature = "gpio-g0bx")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ diff --git a/src/gpio/g4.rs b/src/gpio/g4.rs new file mode 100644 index 00000000..669906c8 --- /dev/null +++ b/src/gpio/g4.rs @@ -0,0 +1,386 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 7, 8, 9, 10, 14, 15]), + PA1: (pa1, 1, [0, 1, 7, 9, 15]), + PA2: (pa2, 2, [1, 7, 8, 9, 12, 14, 15]), + PA3: (pa3, 3, [1, 3, 7, 9, 12, 13, 15]), + PA4: (pa4, 4, [2, 5, 6, 7, 13, 15]), + PA5: (pa5, 5, [1, 2, 5, 14, 15]), + PA6: (pa6, 6, [1, 2, 4, 5, 6, 8, 12, 15]), + PA7: (pa7, 7, [1, 2, 4, 5, 6, 8, 14, 15]), + PA8: (pa8, 8, [0, 2, 4, 5, 6, 7, 10, 12, 14, 15]), + PA9: (pa9, 9, [2, 4, 5, 6, 7, 9, 10, 14, 15]), + PA10: (pa10, 10, [1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15]), + PA11: (pa11, 11, [5, 6, 7, 8, 9, 10, 11, 12, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 8, 9, 10, 11, 15]), + PA13: (pa13, 13, [0, 1, 4, 5, 7, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 6, 7, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 4, 5, 6, 7, 8, 9, 14, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 4, 6, 14, 15]), + PB1: (pb1, 1, [2, 4, 6, 8, 12, 15]), + PB2: (pb2, 2, [0, 1, 4, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 14, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 4, 5, 6, 7, 10, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 15]), + PB6: (pb6, 6, [1, 2, 5, 6, 7, 8, 10, 11, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 5, 7, 8, 10, 11, 14, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 7, 8, 9, 10, 12, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 6, 7, 8, 9, 10, 12, 14, 15]), + PB10: (pb10, 10, [1, 7, 8, 12, 14, 15]), + PB11: (pb11, 11, [1, 7, 8, 15]), + PB12: (pb12, 12, [4, 5, 6, 7, 8, 15]), + PB13: (pb13, 13, [5, 6, 7, 8, 15]), + PB14: (pb14, 14, [1, 5, 6, 7, 8, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 4, 5, 15]), +]); + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2, 8, 15]), + PC1: (pc1, 1, [1, 2, 8, 13, 15]), + PC2: (pc2, 2, [1, 2, 3, 15]), + PC3: (pc3, 3, [1, 2, 3, 6, 13, 15]), + PC4: (pc4, 4, [2, 4, 7, 15]), + PC5: (pc5, 5, [2, 3, 6, 7, 15]), + PC6: (pc6, 6, [2, 4, 6, 15]), + PC7: (pc7, 7, [2, 4, 6, 15]), + PC8: (pc8, 8, [2, 4, 8, 15]), + PC9: (pc9, 9, [2, 4, 5, 6, 8, 15]), + PC10: (pc10, 10, [4, 5, 6, 7, 15]), + PC11: (pc11, 11, [4, 5, 6, 7, 8, 15]), + PC12: (pc12, 12, [4, 6, 7, 14, 15]), + PC13: (pc13, 13, [2, 4, 6, 15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [6, 9, 15]), + PD1: (pd1, 1, [4, 6, 9, 15]), + PD2: (pd2, 2, [2, 4, 15]), + PD3: (pd3, 3, [2, 7, 15]), + PD4: (pd4, 4, [2, 7, 15]), + PD5: (pd5, 5, [7, 15]), + PD6: (pd6, 6, [2, 3, 7, 13, 15]), + PD7: (pd7, 7, [2, 7, 15]), + PD8: (pd8, 8, [7, 15]), + PD9: (pd9, 9, [7, 15]), + PD10: (pd10, 10, [7, 15]), + PD11: (pd11, 11, [7, 15]), + PD12: (pd12, 12, [2, 7, 15]), + PD13: (pd13, 13, [2, 15]), + PD14: (pd14, 14, [2, 15]), + PD15: (pd15, 15, [2, 6, 15]), +]); + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 4, 7, 15]), + PE1: (pe1, 1, [4, 7, 15]), + PE2: (pe2, 2, [0, 2, 3, 13, 15]), + PE3: (pe3, 3, [0, 2, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 13, 15]), + PE6: (pe6, 6, [0, 3, 13, 15]), + PE7: (pe7, 7, [2, 13, 15]), + PE8: (pe8, 8, [2, 13, 15]), + PE9: (pe9, 9, [2, 13, 15]), + PE10: (pe10, 10, [2, 13, 15]), + PE11: (pe11, 11, [2, 15]), + PE12: (pe12, 12, [2, 15]), + PE13: (pe13, 13, [2, 15]), + PE14: (pe14, 14, [2, 6, 15]), + PE15: (pe15, 15, [2, 6, 7, 15]), +]); + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 6, 15]), + PF1: (pf1, 1, [5, 15]), + PF2: (pf2, 2, [4, 15]), + PF9: (pf9, 9, [3, 5, 13, 15]), + PF10: (pf10, 10, [3, 5, 13, 15]), +]); + +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG10: (pg10, 10, [0, 15]), +]); +/* +#[cfg(feature = "gpio-g43x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 7, 8, 9, 10, 14, 15]), + PA1: (pa1, 1, [0, 1, 2, 7, 9, 15]), + PA2: (pa2, 2, [1, 2, 7, 8, 9, 10, 12, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 7, 9, 10, 12, 13, 15]), + PA4: (pa4, 4, [2, 5, 6, 7, 13, 15]), + PA5: (pa5, 5, [1, 2, 5, 14, 15]), + PA6: (pa6, 6, [1, 2, 4, 5, 6, 8, 10, 12, 15]), + PA7: (pa7, 7, [1, 2, 4, 5, 6, 8, 10, 14, 15]), + PA8: (pa8, 8, [0, 2, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PA10: (pa10, 10, [1, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15]), + PA11: (pa11, 11, [5, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 8, 9, 10, 11, 13, 15]), + PA13: (pa13, 13, [0, 1, 3, 4, 5, 7, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 3, 4, 5, 6, 7, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 4, 6, 10, 13, 14, 15]), + PB1: (pb1, 1, [2, 4, 6, 8, 10, 12, 13, 15]), + PB2: (pb2, 2, [0, 1, 2, 3, 4, 10, 13, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 4, 5, 6, 7, 8, 10, 11, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 5, 7, 8, 10, 11, 12, 13, 14, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 7, 8, 9, 10, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 7, 8, 10, 12, 13, 14, 15]), + PB11: (pb11, 11, [1, 7, 8, 10, 13, 15]), + PB12: (pb12, 12, [2, 4, 5, 6, 7, 8, 9, 13, 15]), + PB13: (pb13, 13, [5, 6, 7, 8, 9, 13, 15]), + PB14: (pb14, 14, [1, 5, 6, 7, 8, 13, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 4, 5, 13, 15]), +]); + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2, 8, 15]), + PC1: (pc1, 1, [1, 2, 8, 10, 13, 15]), + PC2: (pc2, 2, [1, 2, 3, 6, 10, 15]), + PC3: (pc3, 3, [0, 1, 2, 3, 6, 10, 13, 15]), + PC4: (pc4, 4, [2, 4, 7, 10, 15]), + PC5: (pc5, 5, [2, 3, 6, 7, 13, 15]), + PC6: (pc6, 6, [2, 3, 4, 6, 7, 8, 13, 15]), + PC7: (pc7, 7, [2, 3, 4, 6, 7, 8, 13, 15]), + PC8: (pc8, 8, [2, 3, 4, 6, 7, 8, 15]), + PC9: (pc9, 9, [2, 3, 4, 5, 6, 8, 15]), + PC10: (pc10, 10, [4, 5, 6, 7, 13, 15]), + PC11: (pc11, 11, [3, 4, 5, 6, 7, 8, 15]), + PC12: (pc12, 12, [1, 3, 4, 5, 6, 7, 14, 15]), + PC13: (pc13, 13, [2, 4, 6, 15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [6, 9, 12, 15]), + PD1: (pd1, 1, [4, 6, 9, 12, 15]), + PD2: (pd2, 2, [2, 4, 5, 15]), + PD3: (pd3, 3, [2, 7, 10, 12, 15]), + PD4: (pd4, 4, [2, 7, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [2, 3, 7, 10, 12, 13, 15]), + PD7: (pd7, 7, [2, 7, 10, 12, 15]), + PD8: (pd8, 8, [7, 12, 15]), + PD9: (pd9, 9, [7, 12, 15]), + PD10: (pd10, 10, [7, 12, 15]), + PD11: (pd11, 11, [1, 4, 7, 12, 15]), + PD12: (pd12, 12, [2, 7, 12, 15]), + PD13: (pd13, 13, [2, 12, 15]), + PD14: (pd14, 14, [2, 12, 15]), + PD15: (pd15, 15, [2, 6, 12, 15]), +]); + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 4, 6, 7, 12, 15]), + PE1: (pe1, 1, [4, 6, 7, 12, 15]), + PE2: (pe2, 2, [0, 2, 3, 5, 6, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 5, 6, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 5, 6, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 5, 6, 12, 13, 15]), + PE6: (pe6, 6, [0, 3, 5, 6, 12, 13, 15]), + PE7: (pe7, 7, [2, 12, 13, 15]), + PE8: (pe8, 8, [1, 2, 12, 13, 15]), + PE9: (pe9, 9, [1, 2, 12, 13, 15]), + PE10: (pe10, 10, [2, 10, 12, 13, 15]), + PE11: (pe11, 11, [2, 5, 10, 12, 15]), + PE12: (pe12, 12, [2, 5, 10, 12, 15]), + PE13: (pe13, 13, [2, 5, 10, 12, 15]), + PE14: (pe14, 14, [2, 5, 6, 10, 12, 15]), + PE15: (pe15, 15, [2, 6, 7, 10, 12, 15]), +]); + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 6, 15]), + PF1: (pf1, 1, [5, 15]), + PF2: (pf2, 2, [2, 4, 12, 15]), + PF3: (pf3, 3, [2, 4, 12, 15]), + PF4: (pf4, 4, [2, 3, 4, 12, 15]), + PF5: (pf5, 5, [2, 12, 15]), + PF6: (pf6, 6, [1, 2, 3, 4, 6, 7, 10, 15]), + PF7: (pf7, 7, [2, 6, 10, 12, 13, 15]), + PF8: (pf8, 8, [2, 6, 10, 12, 13, 15]), + PF9: (pf9, 9, [2, 3, 5, 6, 10, 12, 13, 15]), + PF10: (pf10, 10, [2, 3, 5, 10, 12, 13, 15]), + PF11: (pf11, 11, [2, 12, 15]), + PF12: (pf12, 12, [2, 12, 15]), + PF13: (pf13, 13, [2, 4, 12, 15]), + PF14: (pf14, 14, [2, 4, 12, 15]), + PF15: (pf15, 15, [2, 4, 12, 15]), +]); + +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [2, 12, 15]), + PG1: (pg1, 1, [2, 12, 15]), + PG2: (pg2, 2, [2, 5, 12, 15]), + PG3: (pg3, 3, [2, 4, 5, 6, 12, 15]), + PG4: (pg4, 4, [2, 4, 5, 12, 15]), + PG5: (pg5, 5, [2, 5, 8, 12, 15]), + PG6: (pg6, 6, [2, 4, 8, 12, 15]), + PG7: (pg7, 7, [3, 4, 8, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 12, 15]), + PG9: (pg9, 9, [6, 7, 12, 14, 15]), + PG10: (pg10, 10, [0, 15]), +]); +/* +#[cfg(feature = "gpio-g47x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 7, 8, 9, 10, 14, 15]), + PA1: (pa1, 1, [0, 1, 7, 9, 15]), + PA2: (pa2, 2, [1, 7, 8, 9, 10, 12, 14, 15]), + PA3: (pa3, 3, [1, 3, 7, 9, 10, 12, 13, 15]), + PA4: (pa4, 4, [2, 5, 6, 7, 13, 15]), + PA5: (pa5, 5, [1, 2, 5, 14, 15]), + PA6: (pa6, 6, [1, 2, 4, 5, 6, 8, 10, 12, 15]), + PA7: (pa7, 7, [1, 2, 4, 5, 6, 8, 10, 14, 15]), + PA8: (pa8, 8, [0, 2, 4, 5, 6, 7, 10, 12, 14, 15]), + PA9: (pa9, 9, [2, 4, 5, 6, 7, 9, 10, 14, 15]), + PA10: (pa10, 10, [1, 3, 4, 5, 6, 7, 10, 11, 12, 14, 15]), + PA11: (pa11, 11, [5, 6, 7, 8, 9, 10, 11, 12, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 8, 9, 10, 11, 15]), + PA13: (pa13, 13, [0, 1, 4, 5, 7, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 6, 7, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 4, 6, 10, 14, 15]), + PB1: (pb1, 1, [2, 4, 6, 8, 10, 12, 15]), + PB2: (pb2, 2, [0, 1, 3, 4, 10, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 14, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 4, 5, 6, 7, 8, 10, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15]), + PB6: (pb6, 6, [1, 2, 5, 6, 7, 8, 9, 10, 11, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 5, 7, 8, 10, 11, 14, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 7, 8, 9, 10, 12, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 6, 7, 8, 9, 10, 12, 14, 15]), + PB10: (pb10, 10, [1, 7, 8, 10, 12, 14, 15]), + PB11: (pb11, 11, [1, 7, 8, 10, 15]), + PB12: (pb12, 12, [4, 5, 6, 7, 8, 9, 15]), + PB13: (pb13, 13, [5, 6, 7, 8, 9, 15]), + PB14: (pb14, 14, [1, 5, 6, 7, 8, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 4, 5, 15]), +]); + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2, 8, 15]), + PC1: (pc1, 1, [1, 2, 8, 10, 13, 15]), + PC2: (pc2, 2, [1, 2, 3, 6, 10, 15]), + PC3: (pc3, 3, [1, 2, 3, 6, 10, 13, 15]), + PC4: (pc4, 4, [2, 4, 7, 10, 15]), + PC5: (pc5, 5, [2, 3, 6, 7, 15]), + PC6: (pc6, 6, [2, 4, 6, 15]), + PC7: (pc7, 7, [2, 4, 6, 15]), + PC8: (pc8, 8, [2, 4, 6, 8, 15]), + PC9: (pc9, 9, [2, 4, 5, 6, 8, 15]), + PC10: (pc10, 10, [4, 5, 6, 7, 15]), + PC11: (pc11, 11, [4, 5, 6, 7, 8, 15]), + PC12: (pc12, 12, [4, 5, 6, 7, 14, 15]), + PC13: (pc13, 13, [2, 4, 6, 15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [6, 9, 15]), + PD1: (pd1, 1, [4, 6, 9, 15]), + PD2: (pd2, 2, [2, 4, 5, 15]), + PD3: (pd3, 3, [2, 7, 10, 15]), + PD4: (pd4, 4, [2, 7, 10, 15]), + PD5: (pd5, 5, [7, 10, 15]), + PD6: (pd6, 6, [2, 3, 7, 10, 13, 15]), + PD7: (pd7, 7, [2, 7, 10, 15]), + PD8: (pd8, 8, [7, 15]), + PD9: (pd9, 9, [7, 15]), + PD10: (pd10, 10, [7, 15]), + PD11: (pd11, 11, [7, 15]), + PD12: (pd12, 12, [2, 7, 15]), + PD13: (pd13, 13, [2, 15]), + PD14: (pd14, 14, [2, 15]), + PD15: (pd15, 15, [2, 6, 15]), +]); + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 4, 6, 7, 15]), + PE1: (pe1, 1, [4, 6, 7, 15]), + PE2: (pe2, 2, [0, 2, 3, 6, 13, 15]), + PE3: (pe3, 3, [0, 2, 6, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 6, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 6, 13, 15]), + PE6: (pe6, 6, [0, 3, 6, 13, 15]), + PE7: (pe7, 7, [2, 13, 15]), + PE8: (pe8, 8, [2, 13, 15]), + PE9: (pe9, 9, [2, 13, 15]), + PE10: (pe10, 10, [2, 10, 13, 15]), + PE11: (pe11, 11, [2, 10, 15]), + PE12: (pe12, 12, [2, 10, 15]), + PE13: (pe13, 13, [2, 10, 15]), + PE14: (pe14, 14, [2, 6, 10, 15]), + PE15: (pe15, 15, [2, 6, 7, 10, 15]), +]); + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 6, 15]), + PF1: (pf1, 1, [5, 15]), + PF2: (pf2, 2, [2, 4, 15]), + PF9: (pf9, 9, [2, 3, 5, 10, 13, 15]), + PF10: (pf10, 10, [2, 3, 5, 10, 13, 15]), +]); + +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG10: (pg10, 10, [0, 15]), +]); +/* +#[cfg(feature = "gpio-g49x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ diff --git a/src/gpio/h7.rs b/src/gpio/h7.rs new file mode 100644 index 00000000..d5636895 --- /dev/null +++ b/src/gpio/h7.rs @@ -0,0 +1,609 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 15]), + PA1: (pa1, 1, [1, 2, 3, 4, 7, 8, 9, 10, 11, 12, 14, 15]), + PA2: (pa2, 2, [1, 2, 3, 4, 6, 7, 8, 11, 12, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15]), + PA4: (pa4, 4, [2, 5, 6, 7, 8, 12, 13, 14, 15]), + PA5: (pa5, 5, [1, 3, 5, 8, 10, 12, 13, 14, 15]), + PA6: (pa6, 6, [1, 2, 3, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 5, 8, 9, 10, 11, 12, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 4, 6, 7, 10, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 4, 5, 6, 7, 11, 13, 14, 15]), + PA10: (pa10, 10, [1, 3, 7, 10, 11, 12, 13, 14, 15]), + PA11: (pa11, 11, [1, 3, 5, 6, 7, 9, 14, 15]), + PA12: (pa12, 12, [1, 3, 5, 6, 7, 8, 9, 12, 14, 15]), + PA13: (pa13, 13, [0, 15], super::Debugger), + PA14: (pa14, 14, [0, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 4, 5, 6, 7, 8, 9, 11, 14, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 4, 6, 8, 9, 10, 11, 14, 15]), + PB1: (pb1, 1, [1, 2, 3, 4, 6, 9, 10, 11, 14, 15]), + PB2: (pb2, 2, [0, 1, 2, 4, 6, 7, 8, 9, 10, 11, 13, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 8, 9, 10, 11, 14, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 5, 6, 7, 8, 9, 11, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 6, 7, 8, 11, 12, 13, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 3, 4, 5, 6, 7, 9, 10, 11, 14, 15]), + PB11: (pb11, 11, [1, 3, 4, 6, 7, 10, 11, 14, 15]), + PB12: (pb12, 12, [1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15]), + PB13: (pb13, 13, [1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15]), + PB14: (pb14, 14, [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 4, 5, 6, 8, 9, 12, 14, 15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 3, 6, 8, 9, 10, 11, 12, 14, 15]), + PC1: (pc1, 1, [0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 14, 15]), + PC2: (pc2, 2, []), + PC3: (pc3, 3, []), + PC4: (pc4, 4, [1, 3, 5, 9, 10, 11, 12, 14, 15]), + PC5: (pc5, 5, [1, 2, 3, 4, 9, 10, 11, 12, 13, 14, 15]), + PC6: (pc6, 6, [2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 14, 15]), + PC7: (pc7, 7, [0, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PC8: (pc8, 8, [0, 2, 3, 7, 8, 9, 10, 11, 12, 13, 15]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PC10: (pc10, 10, [3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PC11: (pc11, 11, [3, 4, 6, 7, 8, 9, 12, 13, 14, 15]), + PC12: (pc12, 12, [0, 1, 2, 4, 5, 6, 7, 8, 12, 13, 14, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 8, 9, 11, 12, 14, 15]), + PD1: (pd1, 1, [3, 8, 9, 12, 15]), + PD2: (pd2, 2, [0, 1, 2, 4, 8, 9, 12, 13, 14, 15]), + PD3: (pd3, 3, [3, 5, 7, 12, 13, 14, 15]), + PD4: (pd4, 4, [7, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15]), + PD7: (pd7, 7, [3, 5, 6, 7, 9, 10, 11, 12, 15]), + PD8: (pd8, 8, [3, 7, 9, 12, 15]), + PD9: (pd9, 9, [3, 7, 12, 15]), + PD10: (pd10, 10, [3, 7, 12, 14, 15]), + PD11: (pd11, 11, [3, 4, 7, 9, 10, 12, 15]), + PD12: (pd12, 12, [1, 2, 3, 4, 5, 7, 9, 10, 12, 13, 15]), + PD13: (pd13, 13, [1, 2, 4, 5, 9, 10, 11, 12, 13, 15]), + PD14: (pd14, 14, [2, 8, 11, 12, 15]), + PD15: (pd15, 15, [2, 8, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2, 4, 8, 10, 12, 13, 14, 15]), + PE1: (pe1, 1, [1, 8, 12, 13, 14, 15]), + PE2: (pe2, 2, [0, 2, 4, 5, 6, 8, 9, 10, 11, 12, 15]), + PE3: (pe3, 3, [0, 4, 6, 8, 11, 12, 15]), + PE4: (pe4, 4, [0, 2, 3, 4, 5, 6, 8, 10, 12, 13, 14, 15]), + PE5: (pe5, 5, [0, 2, 3, 4, 5, 6, 8, 10, 12, 13, 14, 15]), + PE6: (pe6, 6, [0, 1, 2, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PE7: (pe7, 7, [1, 3, 7, 10, 12, 15]), + PE8: (pe8, 8, [1, 3, 7, 10, 12, 13, 15]), + PE9: (pe9, 9, [1, 3, 7, 10, 12, 15]), + PE10: (pe10, 10, [1, 3, 7, 10, 12, 15]), + PE11: (pe11, 11, [1, 3, 5, 10, 11, 12, 14, 15]), + PE12: (pe12, 12, [1, 3, 5, 10, 12, 13, 14, 15]), + PE13: (pe13, 13, [1, 3, 5, 10, 12, 13, 14, 15]), + PE14: (pe14, 14, [1, 5, 10, 12, 14, 15]), + PE15: (pe15, 15, [1, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 6, 9, 12, 13, 15]), + PF1: (pf1, 1, [4, 6, 9, 12, 13, 15]), + PF2: (pf2, 2, [4, 6, 9, 12, 13, 15]), + PF3: (pf3, 3, [9, 12, 13, 15]), + PF4: (pf4, 4, [9, 12, 15]), + PF5: (pf5, 5, [9, 12, 15]), + PF6: (pf6, 6, [1, 2, 5, 6, 7, 8, 10, 13, 15]), + PF7: (pf7, 7, [1, 2, 5, 6, 7, 8, 10, 13, 15]), + PF8: (pf8, 8, [1, 5, 6, 7, 8, 9, 10, 13, 15]), + PF9: (pf9, 9, [1, 5, 6, 7, 8, 9, 10, 13, 15]), + PF10: (pf10, 10, [1, 2, 4, 9, 10, 13, 14, 15]), + PF11: (pf11, 11, [5, 9, 10, 12, 13, 14, 15]), + PF12: (pf12, 12, [9, 12, 14, 15]), + PF13: (pf13, 13, [3, 4, 12, 14, 15]), + PF14: (pf14, 14, [3, 4, 12, 14, 15]), + PF15: (pf15, 15, [4, 12, 15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [9, 11, 12, 15]), + PG1: (pg1, 1, [9, 11, 12, 15]), + PG2: (pg2, 2, [3, 11, 12, 14, 15]), + PG3: (pg3, 3, [3, 11, 12, 13, 15]), + PG4: (pg4, 4, [1, 11, 12, 15]), + PG5: (pg5, 5, [1, 12, 15]), + PG6: (pg6, 6, [1, 10, 12, 13, 14, 15]), + PG7: (pg7, 7, [6, 7, 9, 12, 13, 14, 15]), + PG8: (pg8, 8, [3, 5, 7, 8, 11, 12, 14, 15]), + PG9: (pg9, 9, [2, 5, 7, 8, 9, 10, 11, 12, 13, 15]), + PG10: (pg10, 10, [2, 3, 5, 9, 10, 11, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 4, 5, 8, 9, 10, 11, 13, 14, 15]), + PG12: (pg12, 12, [1, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PG13: (pg13, 13, [0, 1, 4, 5, 7, 10, 11, 12, 13, 14, 15]), + PG14: (pg14, 14, [0, 1, 4, 5, 7, 9, 10, 11, 12, 13, 14, 15]), + PG15: (pg15, 15, [7, 9, 11, 12, 13, 15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [1, 9, 10, 11, 12, 14, 15]), + PH3: (ph3, 3, [9, 10, 11, 12, 14, 15]), + PH4: (ph4, 4, [4, 9, 10, 13, 14, 15]), + PH5: (ph5, 5, [4, 5, 12, 15]), + PH6: (ph6, 6, [2, 4, 5, 11, 12, 13, 15]), + PH7: (ph7, 7, [4, 5, 11, 12, 13, 15]), + PH8: (ph8, 8, [2, 4, 12, 13, 14, 15]), + PH9: (ph9, 9, [2, 4, 12, 13, 14, 15]), + PH10: (ph10, 10, [2, 4, 12, 13, 14, 15]), + PH11: (ph11, 11, [2, 4, 12, 13, 14, 15]), + PH12: (ph12, 12, [2, 4, 12, 13, 14, 15]), + PH13: (ph13, 13, [3, 8, 9, 12, 14, 15]), + PH14: (ph14, 14, [3, 8, 9, 12, 13, 14, 15]), + PH15: (ph15, 15, [3, 12, 13, 14, 15]), +]); +/* +#[cfg(feature = "gpio-h72")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ +#[cfg(feature = "gpio-h72")] +gpio!(GPIOJ, gpioj, PJ, 'J', PJn, [ + PJ8: (pj8, 8, [1, 3, 8, 14, 15]), + PJ9: (pj9, 9, [1, 3, 8, 14, 15]), + PJ10: (pj10, 10, [1, 3, 5, 14, 15]), + PJ11: (pj11, 11, [1, 3, 5, 14, 15]), +]); + +#[cfg(feature = "gpio-h72")] +gpio!(GPIOK, gpiok, PK, 'K', PKn, [ + PK0: (pk0, 0, [1, 3, 5, 14, 15]), + PK1: (pk1, 1, [1, 3, 5, 14, 15]), + PK2: (pk2, 2, [1, 3, 10, 11, 14, 15]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 4, 7, 8, 9, 10, 11]), + PA1: (pa1, 1, [1, 2, 3, 4, 7, 8, 9, 10, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 4, 7, 8, 11, 12, 14]), + PA3: (pa3, 3, [1, 2, 3, 4, 7, 9, 10, 11, 14]), + PA4: (pa4, 4, [2, 5, 6, 7, 8, 12, 13, 14]), + PA5: (pa5, 5, [1, 3, 5, 8, 10, 14]), + PA6: (pa6, 6, [1, 2, 3, 5, 8, 9, 10, 11, 12, 13, 14]), + PA7: (pa7, 7, [1, 2, 3, 5, 8, 9, 11, 12]), + PA8: (pa8, 8, [0, 1, 2, 3, 4, 7, 10, 11, 12, 13, 14]), + PA9: (pa9, 9, [1, 2, 3, 4, 5, 7, 13, 14]), + PA10: (pa10, 10, [1, 2, 3, 7, 10, 11, 12, 13, 14]), + PA11: (pa11, 11, [1, 2, 3, 5, 6, 7, 9, 10, 14]), + PA12: (pa12, 12, [1, 2, 3, 5, 6, 7, 8, 9, 10, 14]), + PA13: (pa13, 13, [0], super::Debugger), + PA14: (pa14, 14, [0], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 4, 5, 6, 7, 8, 11, 13], super::Debugger), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 6, 8, 9, 10, 11, 14]), + PB1: (pb1, 1, [1, 2, 3, 6, 9, 10, 11, 14]), + PB2: (pb2, 2, [0, 2, 4, 6, 7, 8, 9, 10]), + PB3: (pb3, 3, [0, 1, 2, 5, 6, 8, 9, 10, 11], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 5, 6, 7, 8, 9, 11], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]), + PB6: (pb6, 6, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]), + PB7: (pb7, 7, [1, 2, 3, 4, 6, 7, 8, 11, 12, 13]), + PB8: (pb8, 8, [1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]), + PB10: (pb10, 10, [1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 14]), + PB11: (pb11, 11, [1, 2, 3, 4, 6, 7, 10, 11, 13, 14]), + PB12: (pb12, 12, [1, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14]), + PB13: (pb13, 13, [1, 3, 5, 6, 7, 9, 10, 11, 14]), + PB14: (pb14, 14, [1, 2, 3, 4, 5, 6, 7, 8, 9, 12]), + PB15: (pb15, 15, [0, 1, 2, 3, 4, 5, 6, 8, 9, 12]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [3, 6, 8, 10, 12, 14]), + PC1: (pc1, 1, [0, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12]), + PC2: (pc2, 2, [3, 5, 6, 10, 11, 12]), + PC3: (pc3, 3, [3, 5, 10, 11, 12]), + PC4: (pc4, 4, [3, 5, 9, 11, 12]), + PC5: (pc5, 5, [2, 3, 9, 10, 11, 12, 13]), + PC6: (pc6, 6, [1, 2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 14]), + PC7: (pc7, 7, [0, 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14]), + PC8: (pc8, 8, [0, 1, 2, 3, 7, 8, 9, 11, 12, 13]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14]), + PC10: (pc10, 10, [2, 3, 6, 7, 8, 9, 12, 13, 14]), + PC11: (pc11, 11, [2, 3, 6, 7, 8, 9, 12, 13]), + PC12: (pc12, 12, [0, 2, 6, 7, 8, 12, 13]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 6, 8, 9, 12]), + PD1: (pd1, 1, [3, 6, 8, 9, 12]), + PD2: (pd2, 2, [0, 2, 8, 12, 13]), + PD3: (pd3, 3, [3, 5, 7, 12, 13, 14]), + PD4: (pd4, 4, [2, 6, 7, 12]), + PD5: (pd5, 5, [2, 7, 12]), + PD6: (pd6, 6, [2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14]), + PD7: (pd7, 7, [3, 5, 6, 7, 9, 11, 12]), + PD8: (pd8, 8, [3, 6, 7, 9, 12]), + PD9: (pd9, 9, [3, 6, 7, 12]), + PD10: (pd10, 10, [3, 6, 7, 12, 14]), + PD11: (pd11, 11, [3, 4, 7, 9, 10, 12]), + PD12: (pd12, 12, [1, 2, 3, 4, 7, 9, 10, 12]), + PD13: (pd13, 13, [1, 2, 4, 9, 10, 12]), + PD14: (pd14, 14, [2, 6, 8, 12]), + PD15: (pd15, 15, [2, 6, 8, 12]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2, 3, 4, 8, 10, 12, 13]), + PE1: (pe1, 1, [1, 3, 8, 12, 13]), + PE2: (pe2, 2, [0, 2, 5, 6, 8, 9, 10, 11, 12]), + PE3: (pe3, 3, [0, 4, 6, 8, 12]), + PE4: (pe4, 4, [0, 2, 3, 4, 5, 6, 8, 10, 12, 13, 14]), + PE5: (pe5, 5, [0, 2, 3, 4, 5, 6, 8, 10, 12, 13, 14]), + PE6: (pe6, 6, [0, 1, 2, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14]), + PE7: (pe7, 7, [1, 3, 7, 10, 12]), + PE8: (pe8, 8, [1, 3, 7, 10, 12, 13]), + PE9: (pe9, 9, [1, 3, 7, 10, 12]), + PE10: (pe10, 10, [1, 3, 7, 10, 12]), + PE11: (pe11, 11, [1, 3, 5, 10, 12, 14]), + PE12: (pe12, 12, [1, 3, 5, 10, 12, 13, 14]), + PE13: (pe13, 13, [1, 3, 5, 10, 12, 13, 14]), + PE14: (pe14, 14, [1, 5, 10, 12, 14]), + PE15: (pe15, 15, [1, 12, 13, 14]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12]), + PF1: (pf1, 1, [4, 12]), + PF2: (pf2, 2, [4, 12]), + PF3: (pf3, 3, [12]), + PF4: (pf4, 4, [12]), + PF5: (pf5, 5, [12]), + PF6: (pf6, 6, [1, 5, 6, 7, 8, 9]), + PF7: (pf7, 7, [1, 5, 6, 7, 8, 9]), + PF8: (pf8, 8, [1, 5, 6, 7, 8, 9, 10]), + PF9: (pf9, 9, [1, 5, 6, 7, 8, 9, 10]), + PF10: (pf10, 10, [1, 2, 9, 10, 13, 14]), + PF11: (pf11, 11, [5, 10, 12, 13]), + PF12: (pf12, 12, [12]), + PF13: (pf13, 13, [3, 4, 12]), + PF14: (pf14, 14, [3, 4, 12]), + PF15: (pf15, 15, [4, 12]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [12]), + PG1: (pg1, 1, [12]), + PG2: (pg2, 2, [3, 11, 12]), + PG3: (pg3, 3, [3, 11, 12]), + PG4: (pg4, 4, [1, 11, 12]), + PG5: (pg5, 5, [1, 12]), + PG6: (pg6, 6, [1, 2, 10, 12, 13, 14]), + PG7: (pg7, 7, [2, 6, 7, 12, 13, 14]), + PG8: (pg8, 8, [3, 5, 7, 8, 11, 12, 14]), + PG9: (pg9, 9, [5, 7, 8, 9, 10, 12, 13]), + PG10: (pg10, 10, [2, 5, 9, 10, 12, 13, 14]), + PG11: (pg11, 11, [1, 2, 5, 8, 10, 11, 13, 14]), + PG12: (pg12, 12, [1, 2, 5, 7, 8, 9, 11, 12, 14]), + PG13: (pg13, 13, [0, 1, 2, 5, 7, 11, 12, 14]), + PG14: (pg14, 14, [0, 1, 5, 7, 9, 11, 12, 14]), + PG15: (pg15, 15, [7, 12, 13]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, []), + PH1: (ph1, 1, []), + PH2: (ph2, 2, [1, 9, 10, 11, 12, 14]), + PH3: (ph3, 3, [9, 10, 11, 12, 14]), + PH4: (ph4, 4, [4, 9, 10, 14]), + PH5: (ph5, 5, [4, 5, 12]), + PH6: (ph6, 6, [2, 4, 5, 11, 12, 13]), + PH7: (ph7, 7, [4, 5, 11, 12, 13]), + PH8: (ph8, 8, [2, 4, 12, 13, 14]), + PH9: (ph9, 9, [2, 4, 12, 13, 14]), + PH10: (ph10, 10, [2, 4, 12, 13, 14]), + PH11: (ph11, 11, [2, 4, 12, 13, 14]), + PH12: (ph12, 12, [2, 4, 12, 13, 14]), + PH13: (ph13, 13, [3, 8, 9, 12, 14]), + PH14: (ph14, 14, [3, 8, 9, 12, 13, 14]), + PH15: (ph15, 15, [3, 12, 13, 14]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 12, 13, 14]), + PI1: (pi1, 1, [3, 5, 11, 12, 13, 14]), + PI2: (pi2, 2, [3, 5, 12, 13, 14]), + PI3: (pi3, 3, [3, 5, 12, 13]), + PI4: (pi4, 4, [3, 10, 11, 12, 13, 14]), + PI5: (pi5, 5, [3, 10, 12, 13, 14]), + PI6: (pi6, 6, [3, 10, 12, 13, 14]), + PI7: (pi7, 7, [3, 10, 12, 13, 14]), + PI8: (pi8, 8, []), + PI9: (pi9, 9, [8, 9, 12, 14]), + PI10: (pi10, 10, [11, 12, 14]), + PI11: (pi11, 11, [9, 10]), + PI12: (pi12, 12, [14]), + PI13: (pi13, 13, [14]), + PI14: (pi14, 14, [14]), + PI15: (pi15, 15, [9, 14]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOJ, gpioj, PJ, 'J', PJn, [ + PJ0: (pj0, 0, [9, 14]), + PJ1: (pj1, 1, [14]), + PJ2: (pj2, 2, [13, 14]), + PJ3: (pj3, 3, [14]), + PJ4: (pj4, 4, [14]), + PJ5: (pj5, 5, [14]), + PJ6: (pj6, 6, [3, 14]), + PJ7: (pj7, 7, [0, 3, 14]), + PJ8: (pj8, 8, [1, 3, 8, 14]), + PJ9: (pj9, 9, [1, 3, 8, 14]), + PJ10: (pj10, 10, [1, 3, 5, 14]), + PJ11: (pj11, 11, [1, 3, 5, 14]), + PJ12: (pj12, 12, [0, 9, 14]), + PJ13: (pj13, 13, [9, 14]), + PJ14: (pj14, 14, [14]), + PJ15: (pj15, 15, [14]), +]); + +#[cfg(feature = "gpio-h747")] +gpio!(GPIOK, gpiok, PK, 'K', PKn, [ + PK0: (pk0, 0, [1, 3, 5, 14]), + PK1: (pk1, 1, [1, 3, 5, 14]), + PK2: (pk2, 2, [1, 3, 10, 11, 14]), + PK3: (pk3, 3, [14]), + PK4: (pk4, 4, [14]), + PK5: (pk5, 5, [14]), + PK6: (pk6, 6, [14]), + PK7: (pk7, 7, [14]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 4, 5, 7, 8, 9, 10, 15]), + PA1: (pa1, 1, [1, 2, 3, 4, 7, 8, 9, 10, 11, 14, 15]), + PA2: (pa2, 2, [1, 2, 4, 6, 7, 8, 12, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 4, 5, 7, 9, 10, 14, 15]), + PA4: (pa4, 4, [2, 5, 6, 7, 8, 13, 14, 15]), + PA5: (pa5, 5, [0, 1, 3, 5, 8, 10, 13, 14, 15]), + PA6: (pa6, 6, [1, 2, 3, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 8, 9, 10, 12, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 4, 7, 10, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 4, 5, 7, 13, 14, 15]), + PA10: (pa10, 10, [1, 3, 7, 10, 11, 12, 13, 14, 15]), + PA11: (pa11, 11, [1, 3, 5, 6, 7, 9, 14, 15]), + PA12: (pa12, 12, [1, 3, 5, 6, 7, 8, 9, 14, 15]), + PA13: (pa13, 13, [0, 15], super::Debugger), + PA14: (pa14, 14, [0, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 4, 5, 6, 7, 8, 9, 11, 14, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 4, 6, 8, 9, 10, 11, 14, 15]), + PB1: (pb1, 1, [1, 2, 3, 6, 9, 10, 11, 14, 15]), + PB2: (pb2, 2, [0, 2, 4, 6, 7, 9, 10, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 8, 9, 10, 11, 15], super::Debugger), + PB4: (pb4, 4, [1, 2, 5, 6, 7, 8, 9, 11, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 6, 7, 8, 11, 12, 13, 15]), + PB8: (pb8, 8, [1, 2, 3, 4, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 3, 4, 5, 6, 7, 9, 10, 14, 15]), + PB11: (pb11, 11, [1, 3, 4, 6, 7, 10, 14, 15]), + PB12: (pb12, 12, [1, 3, 4, 5, 6, 7, 9, 10, 11, 13, 14, 15]), + PB13: (pb13, 13, [1, 3, 4, 5, 6, 7, 9, 10, 12, 13, 14, 15]), + PB14: (pb14, 14, [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 4, 5, 6, 8, 9, 14, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [3, 6, 8, 9, 10, 11, 12, 14, 15]), + PC1: (pc1, 1, [0, 2, 3, 4, 5, 6, 9, 10, 12, 14, 15]), + PC2: (pc2, 2, [0, 3, 5, 6, 9, 10, 11, 12, 15]), + PC3: (pc3, 3, [0, 3, 5, 9, 10, 11, 12, 15]), + PC4: (pc4, 4, [3, 5, 9, 12, 14, 15]), + PC5: (pc5, 5, [2, 3, 4, 9, 10, 12, 13, 14, 15]), + PC6: (pc6, 6, [2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 14, 15]), + PC7: (pc7, 7, [0, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PC8: (pc8, 8, [0, 2, 3, 7, 8, 9, 10, 11, 12, 13, 15]), + PC9: (pc9, 9, [0, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15]), + PC10: (pc10, 10, [3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PC11: (pc11, 11, [3, 4, 6, 7, 8, 9, 12, 13, 14, 15]), + PC12: (pc12, 12, [0, 2, 4, 5, 6, 7, 8, 12, 13, 14, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 8, 9, 11, 12, 14, 15]), + PD1: (pd1, 1, [3, 8, 9, 12, 15]), + PD2: (pd2, 2, [0, 2, 4, 8, 9, 12, 13, 14, 15]), + PD3: (pd3, 3, [3, 5, 7, 12, 13, 14, 15]), + PD4: (pd4, 4, [7, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15]), + PD7: (pd7, 7, [3, 5, 6, 7, 9, 10, 11, 12, 15]), + PD8: (pd8, 8, [3, 7, 9, 12, 15]), + PD9: (pd9, 9, [3, 7, 12, 15]), + PD10: (pd10, 10, [3, 4, 7, 12, 14, 15]), + PD11: (pd11, 11, [3, 4, 7, 9, 10, 12, 15]), + PD12: (pd12, 12, [1, 2, 3, 4, 7, 9, 10, 12, 13, 15]), + PD13: (pd13, 13, [1, 2, 4, 9, 10, 11, 12, 13, 15]), + PD14: (pd14, 14, [2, 8, 11, 12, 15]), + PD15: (pd15, 15, [2, 8, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2, 4, 8, 10, 12, 13, 14, 15]), + PE1: (pe1, 1, [1, 8, 12, 13, 14, 15]), + PE2: (pe2, 2, [0, 2, 5, 6, 9, 11, 12, 15]), + PE3: (pe3, 3, [0, 4, 6, 11, 12, 15]), + PE4: (pe4, 4, [0, 2, 3, 4, 5, 6, 12, 13, 14, 15]), + PE5: (pe5, 5, [0, 2, 3, 4, 5, 6, 12, 13, 14, 15]), + PE6: (pe6, 6, [0, 1, 2, 4, 5, 6, 10, 11, 12, 13, 14, 15]), + PE7: (pe7, 7, [1, 3, 7, 10, 12, 15]), + PE8: (pe8, 8, [1, 3, 7, 10, 12, 13, 15]), + PE9: (pe9, 9, [1, 3, 7, 10, 12, 15]), + PE10: (pe10, 10, [1, 3, 7, 10, 12, 15]), + PE11: (pe11, 11, [1, 3, 5, 10, 11, 12, 14, 15]), + PE12: (pe12, 12, [1, 3, 5, 10, 12, 13, 14, 15]), + PE13: (pe13, 13, [1, 3, 5, 10, 12, 13, 14, 15]), + PE14: (pe14, 14, [1, 5, 10, 12, 14, 15]), + PE15: (pe15, 15, [1, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 9, 12, 15]), + PF1: (pf1, 1, [4, 9, 12, 15]), + PF2: (pf2, 2, [4, 9, 12, 15]), + PF3: (pf3, 3, [9, 12, 15]), + PF4: (pf4, 4, [9, 12, 15]), + PF5: (pf5, 5, [9, 12, 15]), + PF6: (pf6, 6, [1, 5, 6, 7, 10, 15]), + PF7: (pf7, 7, [1, 5, 6, 7, 10, 15]), + PF8: (pf8, 8, [1, 5, 6, 7, 9, 10, 15]), + PF9: (pf9, 9, [1, 5, 6, 7, 9, 10, 15]), + PF10: (pf10, 10, [1, 2, 4, 9, 13, 14, 15]), + PF11: (pf11, 11, [5, 9, 10, 12, 13, 15]), + PF12: (pf12, 12, [9, 12, 15]), + PF13: (pf13, 13, [3, 4, 12, 15]), + PF14: (pf14, 14, [3, 4, 12, 15]), + PF15: (pf15, 15, [4, 12, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [9, 11, 12, 15]), + PG1: (pg1, 1, [9, 11, 12, 15]), + PG2: (pg2, 2, [3, 11, 12, 15]), + PG3: (pg3, 3, [3, 11, 12, 15]), + PG4: (pg4, 4, [1, 11, 12, 15]), + PG5: (pg5, 5, [1, 12, 15]), + PG6: (pg6, 6, [1, 10, 12, 13, 14, 15]), + PG7: (pg7, 7, [6, 7, 9, 12, 13, 14, 15]), + PG8: (pg8, 8, [3, 5, 7, 8, 12, 14, 15]), + PG9: (pg9, 9, [5, 7, 8, 9, 10, 11, 12, 13, 15]), + PG10: (pg10, 10, [3, 5, 9, 10, 11, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 5, 8, 9, 10, 11, 13, 14, 15]), + PG12: (pg12, 12, [1, 3, 5, 7, 8, 9, 10, 11, 12, 14, 15]), + PG13: (pg13, 13, [0, 1, 5, 7, 10, 11, 12, 14, 15]), + PG14: (pg14, 14, [0, 1, 5, 7, 9, 10, 11, 12, 14, 15]), + PG15: (pg15, 15, [7, 9, 11, 12, 13, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [1, 9, 10, 12, 14, 15]), + PH3: (ph3, 3, [9, 10, 12, 14, 15]), + PH4: (ph4, 4, [4, 9, 10, 13, 14, 15]), + PH5: (ph5, 5, [4, 5, 12, 15]), + PH6: (ph6, 6, [2, 4, 5, 12, 13, 15]), + PH7: (ph7, 7, [4, 5, 12, 13, 15]), + PH8: (ph8, 8, [2, 4, 12, 13, 14, 15]), + PH9: (ph9, 9, [2, 4, 12, 13, 14, 15]), + PH10: (ph10, 10, [2, 4, 12, 13, 14, 15]), + PH11: (ph11, 11, [2, 4, 12, 13, 14, 15]), + PH12: (ph12, 12, [2, 4, 12, 13, 14, 15]), + PH13: (ph13, 13, [3, 8, 9, 12, 14, 15]), + PH14: (ph14, 14, [3, 8, 9, 12, 13, 14, 15]), + PH15: (ph15, 15, [3, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 12, 13, 14, 15]), + PI1: (pi1, 1, [3, 5, 11, 12, 13, 14, 15]), + PI2: (pi2, 2, [3, 5, 12, 13, 14, 15]), + PI3: (pi3, 3, [3, 5, 12, 13, 15]), + PI4: (pi4, 4, [3, 10, 11, 12, 13, 14, 15]), + PI5: (pi5, 5, [3, 10, 12, 13, 14, 15]), + PI6: (pi6, 6, [3, 10, 12, 13, 14, 15]), + PI7: (pi7, 7, [3, 10, 12, 13, 14, 15]), + PI8: (pi8, 8, [15]), + PI9: (pi9, 9, [3, 8, 9, 12, 14, 15]), + PI10: (pi10, 10, [3, 12, 13, 14, 15]), + PI11: (pi11, 11, [3, 9, 10, 13, 15]), + PI12: (pi12, 12, [3, 14, 15]), + PI13: (pi13, 13, [3, 14, 15]), + PI14: (pi14, 14, [3, 14, 15]), + PI15: (pi15, 15, [9, 14, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOJ, gpioj, PJ, 'J', PJn, [ + PJ0: (pj0, 0, [9, 14, 15]), + PJ1: (pj1, 1, [3, 14, 15]), + PJ2: (pj2, 2, [3, 14, 15]), + PJ3: (pj3, 3, [11, 14, 15]), + PJ4: (pj4, 4, [11, 14, 15]), + PJ5: (pj5, 5, [14, 15]), + PJ6: (pj6, 6, [3, 14, 15]), + PJ7: (pj7, 7, [0, 3, 14, 15]), + PJ8: (pj8, 8, [1, 3, 8, 14, 15]), + PJ9: (pj9, 9, [1, 3, 8, 14, 15]), + PJ10: (pj10, 10, [1, 3, 5, 14, 15]), + PJ11: (pj11, 11, [1, 3, 5, 14, 15]), + PJ12: (pj12, 12, [0, 9, 14, 15]), + PJ13: (pj13, 13, [9, 14, 15]), + PJ14: (pj14, 14, [14, 15]), + PJ15: (pj15, 15, [14, 15]), +]); + +#[cfg(feature = "gpio-h7a2")] +gpio!(GPIOK, gpiok, PK, 'K', PKn, [ + PK0: (pk0, 0, [1, 3, 5, 14, 15]), + PK1: (pk1, 1, [1, 3, 5, 14, 15]), + PK2: (pk2, 2, [1, 3, 10, 11, 14, 15]), + PK3: (pk3, 3, [3, 14, 15]), + PK4: (pk4, 4, [3, 14, 15]), + PK5: (pk5, 5, [3, 14, 15]), + PK6: (pk6, 6, [3, 14, 15]), + PK7: (pk7, 7, [14, 15]), +]); diff --git a/src/gpio/l0.rs b/src/gpio/l0.rs new file mode 100644 index 00000000..2d71ee0a --- /dev/null +++ b/src/gpio/l0.rs @@ -0,0 +1,303 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-l021")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 4, 5, 6, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5, 6]), + PA2: (pa2, 2, [0, 2, 4, 6, 7]), + PA3: (pa3, 3, [0, 2, 4, 6]), + PA4: (pa4, 4, [0, 1, 2, 3, 4, 5, 6, 7]), + PA5: (pa5, 5, [0, 1, 2, 5]), + PA6: (pa6, 6, [0, 1, 4, 6, 7]), + PA7: (pa7, 7, [0, 1, 4, 5, 6, 7]), + PA8: (pa8, 8, [0, 2, 3, 4, 5]), + PA9: (pa9, 9, [0, 1, 2, 4, 5, 7]), + PA10: (pa10, 10, [0, 1, 2, 4, 5, 7]), + PA11: (pa11, 11, [0, 1, 2, 4, 5, 7]), + PA12: (pa12, 12, [0, 2, 4, 7]), + PA13: (pa13, 13, [0, 1, 3, 5, 6, 7], super::Debugger), + PA14: (pa14, 14, [0, 1, 3, 4, 5, 6, 7], super::Debugger), + PA15: (pa15, 15, [0, 2, 3, 4, 5], super::Debugger), +]); + +#[cfg(feature = "gpio-l021")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 4, 5]), + PB1: (pb1, 1, [0, 1, 2, 4, 5]), + PB2: (pb2, 2, [2]), + PB3: (pb3, 3, [0, 2, 4], super::Debugger), + PB4: (pb4, 4, [0, 2], super::Debugger), + PB5: (pb5, 5, [0, 2, 3, 5]), + PB6: (pb6, 6, [0, 1, 2, 5, 6]), + PB7: (pb7, 7, [0, 1, 2, 5, 6]), + PB8: (pb8, 8, [0, 2, 4, 5]), + PB9: (pb9, 9, []), +]); + +#[cfg(feature = "gpio-l021")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); +/* +#[cfg(feature = "gpio-l021")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l031")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 4, 5, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5]), + PA2: (pa2, 2, [0, 2, 4, 6, 7]), + PA3: (pa3, 3, [0, 2, 4, 6]), + PA4: (pa4, 4, [0, 1, 4, 5]), + PA5: (pa5, 5, [0, 1, 2, 5]), + PA6: (pa6, 6, [0, 1, 4, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 4, 5, 6, 7]), + PA8: (pa8, 8, [0, 2, 3, 4, 5]), + PA9: (pa9, 9, [0, 1, 4, 5]), + PA10: (pa10, 10, [1, 4, 5]), + PA11: (pa11, 11, [0, 2, 4, 5, 7]), + PA12: (pa12, 12, [0, 2, 4, 7]), + PA13: (pa13, 13, [0, 1, 6], super::Debugger), + PA14: (pa14, 14, [0, 1, 3, 4, 6], super::Debugger), + PA15: (pa15, 15, [0, 2, 3, 4, 5], super::Debugger), +]); + +#[cfg(feature = "gpio-l031")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 4, 5]), + PB1: (pb1, 1, [0, 1, 4, 5]), + PB2: (pb2, 2, [2]), + PB3: (pb3, 3, [0, 2, 4], super::Debugger), + PB4: (pb4, 4, [0, 2, 4], super::Debugger), + PB5: (pb5, 5, [0, 2, 3, 4]), + PB6: (pb6, 6, [0, 1, 2, 5]), + PB7: (pb7, 7, [0, 1, 2]), + PB8: (pb8, 8, [4]), + PB9: (pb9, 9, [2, 4]), + PB10: (pb10, 10, [2, 6]), + PB11: (pb11, 11, [0, 2, 6]), + PB12: (pb12, 12, [0, 6]), + PB13: (pb13, 13, [0, 2, 5, 6]), + PB14: (pb14, 14, [0, 2, 5, 6]), + PB15: (pb15, 15, [0, 2]), +]); + +#[cfg(feature = "gpio-l031")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 2, 6]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-l031")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, []), + PH1: (ph1, 1, []), +]); +/* +#[cfg(feature = "gpio-l031")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l051")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [2, 3, 4, 5, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5]), + PA2: (pa2, 2, [0, 1, 2, 3, 4, 7]), + PA3: (pa3, 3, [0, 1, 2, 3, 4]), + PA4: (pa4, 4, [0, 3, 4, 5]), + PA5: (pa5, 5, [0, 2, 3, 5]), + PA6: (pa6, 6, [0, 1, 3, 4, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 3, 5, 6, 7]), + PA8: (pa8, 8, [0, 1, 2, 3, 4]), + PA9: (pa9, 9, [0, 1, 3, 4]), + PA10: (pa10, 10, [1, 3, 4]), + PA11: (pa11, 11, [0, 2, 3, 4, 7]), + PA12: (pa12, 12, [0, 2, 3, 4, 7]), + PA13: (pa13, 13, [0, 2], super::Debugger), + PA14: (pa14, 14, [0, 4], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4, 5], super::Debugger), +]); + +#[cfg(feature = "gpio-l051")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 3]), + PB1: (pb1, 1, [1, 3, 4]), + PB2: (pb2, 2, [2, 3]), + PB3: (pb3, 3, [0, 1, 2, 3, 4], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3, 4]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3]), + PB8: (pb8, 8, [1, 3, 4]), + PB9: (pb9, 9, [1, 2, 4, 5]), + PB10: (pb10, 10, [1, 2, 3, 4, 5, 6]), + PB11: (pb11, 11, [0, 1, 2, 3, 4, 6]), + PB12: (pb12, 12, [0, 1, 2, 3, 5, 6]), + PB13: (pb13, 13, [0, 1, 3, 4, 5, 6]), + PB14: (pb14, 14, [0, 1, 2, 3, 4, 5, 6]), + PB15: (pb15, 15, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-l051")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 1, 2, 3]), + PC1: (pc1, 1, [0, 1, 2, 3]), + PC2: (pc2, 2, [0, 1, 2, 3]), + PC3: (pc3, 3, [0, 1, 2, 3]), + PC4: (pc4, 4, [0, 1, 2]), + PC5: (pc5, 5, [1, 2, 3]), + PC6: (pc6, 6, [0, 1, 3]), + PC7: (pc7, 7, [0, 1, 3]), + PC8: (pc8, 8, [0, 1, 3]), + PC9: (pc9, 9, [0, 1, 2, 3]), + PC10: (pc10, 10, [0, 1]), + PC11: (pc11, 11, [0, 1]), + PC12: (pc12, 12, [1]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-l051")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD2: (pd2, 2, [0, 1]), +]); + +#[cfg(feature = "gpio-l051")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, []), +]); +/* +#[cfg(feature = "gpio-l051")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l071")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [2, 3, 4, 5, 6, 7]), + PA1: (pa1, 1, [0, 1, 2, 3, 4, 5, 6]), + PA2: (pa2, 2, [0, 1, 2, 3, 4, 6, 7]), + PA3: (pa3, 3, [0, 1, 2, 3, 4, 6]), + PA4: (pa4, 4, [0, 3, 4, 5]), + PA5: (pa5, 5, [0, 2, 3, 5]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 6, 7]), + PA7: (pa7, 7, [0, 1, 2, 3, 5, 6, 7]), + PA8: (pa8, 8, [0, 1, 2, 3, 4, 7]), + PA9: (pa9, 9, [0, 1, 3, 4, 6, 7]), + PA10: (pa10, 10, [1, 3, 4, 6]), + PA11: (pa11, 11, [0, 2, 3, 4, 7]), + PA12: (pa12, 12, [0, 2, 3, 4, 7]), + PA13: (pa13, 13, [0, 2, 6], super::Debugger), + PA14: (pa14, 14, [0, 4, 6], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 4, 5, 6], super::Debugger), +]); + +#[cfg(feature = "gpio-l071")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 2, 3]), + PB1: (pb1, 1, [1, 2, 3, 4]), + PB2: (pb2, 2, [2, 3, 7]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4, 5, 6, 7], super::Debugger), + PB5: (pb5, 5, [0, 1, 2, 3, 4, 5, 6]), + PB6: (pb6, 6, [0, 1, 2, 3]), + PB7: (pb7, 7, [0, 1, 2, 3, 6]), + PB8: (pb8, 8, [1, 3, 4]), + PB9: (pb9, 9, [1, 2, 4, 5]), + PB10: (pb10, 10, [1, 2, 3, 4, 5, 6, 7]), + PB11: (pb11, 11, [0, 1, 2, 3, 4, 6, 7]), + PB12: (pb12, 12, [0, 1, 2, 3, 5, 6]), + PB13: (pb13, 13, [0, 1, 2, 3, 4, 5, 6]), + PB14: (pb14, 14, [0, 1, 2, 3, 4, 5, 6]), + PB15: (pb15, 15, [0, 1, 2]), +]); + +#[cfg(feature = "gpio-l071")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 1, 2, 3, 6, 7]), + PC1: (pc1, 1, [0, 1, 2, 3, 6, 7]), + PC2: (pc2, 2, [0, 1, 2, 3]), + PC3: (pc3, 3, [0, 1, 2, 3]), + PC4: (pc4, 4, [0, 1, 2]), + PC5: (pc5, 5, [1, 2, 3]), + PC6: (pc6, 6, [0, 1, 2, 3]), + PC7: (pc7, 7, [0, 1, 2, 3]), + PC8: (pc8, 8, [0, 1, 2, 3]), + PC9: (pc9, 9, [0, 1, 2, 3, 7]), + PC10: (pc10, 10, [0, 1, 6]), + PC11: (pc11, 11, [0, 1, 6]), + PC12: (pc12, 12, [1, 2, 6]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, []), + PC15: (pc15, 15, []), +]); + +#[cfg(feature = "gpio-l071")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [0, 1]), + PD1: (pd1, 1, [1]), + PD2: (pd2, 2, [0, 1, 2, 6]), + PD3: (pd3, 3, [0, 1, 2]), + PD4: (pd4, 4, [0, 1]), + PD5: (pd5, 5, [0]), + PD6: (pd6, 6, [0]), + PD7: (pd7, 7, [0, 1]), + PD8: (pd8, 8, [0, 1]), + PD9: (pd9, 9, [0, 1]), + PD10: (pd10, 10, [1]), + PD11: (pd11, 11, [0, 1]), + PD12: (pd12, 12, [0, 1]), + PD13: (pd13, 13, [1]), + PD14: (pd14, 14, [1]), + PD15: (pd15, 15, [0, 1]), +]); + +#[cfg(feature = "gpio-l071")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 2]), + PE1: (pe1, 1, [1, 2]), + PE2: (pe2, 2, [1, 2]), + PE3: (pe3, 3, [0, 1, 2]), + PE4: (pe4, 4, [0, 2]), + PE5: (pe5, 5, [0, 2]), + PE6: (pe6, 6, [0, 2]), + PE7: (pe7, 7, [1, 6]), + PE8: (pe8, 8, [1, 6]), + PE9: (pe9, 9, [0, 1, 2, 6]), + PE10: (pe10, 10, [0, 1, 6]), + PE11: (pe11, 11, [0, 6]), + PE12: (pe12, 12, [0, 2]), + PE13: (pe13, 13, [1, 2]), + PE14: (pe14, 14, [1, 2]), + PE15: (pe15, 15, [1, 2]), +]); + +#[cfg(feature = "gpio-l071")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, []), + PH9: (ph9, 9, []), + PH10: (ph10, 10, []), +]); +/* +#[cfg(feature = "gpio-l071")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ diff --git a/src/gpio/l1.rs b/src/gpio/l1.rs new file mode 100644 index 00000000..b5f15a34 --- /dev/null +++ b/src/gpio/l1.rs @@ -0,0 +1,620 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Input as DefaultMode; + +#[cfg(feature = "gpio-l152x8")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 7, 14]), + PA1: (pa1, 1, [1, 7, 11, 14]), + PA2: (pa2, 2, [1, 3, 7, 11, 14]), + PA3: (pa3, 3, [1, 3, 7, 11, 14]), + PA4: (pa4, 4, [5, 7, 14]), + PA5: (pa5, 5, [1, 5, 14]), + PA6: (pa6, 6, [2, 3, 5, 11, 14]), + PA7: (pa7, 7, [2, 3, 5, 11, 14]), + PA8: (pa8, 8, [0, 7, 11, 14]), + PA9: (pa9, 9, [7, 11, 14]), + PA10: (pa10, 10, [7, 11, 14]), + PA11: (pa11, 11, [5, 7, 10, 14]), + PA12: (pa12, 12, [5, 7, 10, 14]), + PA13: (pa13, 13, [0, 14], super::Debugger), + PA14: (pa14, 14, [0, 14], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 11, 14], super::Debugger), +]); + +#[cfg(feature = "gpio-l152x8")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 11, 14]), + PB1: (pb1, 1, [2, 11, 14]), + PB2: (pb2, 2, []), + PB3: (pb3, 3, [0, 1, 5, 11], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 11, 14], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 11, 14]), + PB6: (pb6, 6, [2, 4, 7]), + PB7: (pb7, 7, [2, 4, 7]), + PB8: (pb8, 8, [2, 3, 4, 11]), + PB9: (pb9, 9, [2, 3, 4, 11]), + PB10: (pb10, 10, [1, 4, 7, 11]), + PB11: (pb11, 11, [1, 4, 7, 11]), + PB12: (pb12, 12, [3, 4, 5, 7, 11, 14]), + PB13: (pb13, 13, [3, 5, 7, 11, 14]), + PB14: (pb14, 14, [3, 5, 7, 11, 14]), + PB15: (pb15, 15, [0, 3, 5, 11, 14]), +]); + +#[cfg(feature = "gpio-l152x8")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [11, 14]), + PC1: (pc1, 1, [11, 14]), + PC2: (pc2, 2, [11, 14]), + PC3: (pc3, 3, [11, 14]), + PC4: (pc4, 4, [11, 14]), + PC5: (pc5, 5, [11, 14]), + PC6: (pc6, 6, [2, 11, 14]), + PC7: (pc7, 7, [2, 11, 14]), + PC8: (pc8, 8, [2, 11, 14]), + PC9: (pc9, 9, [2, 11, 14]), + PC10: (pc10, 10, [7, 11, 14]), + PC11: (pc11, 11, [7, 11, 14]), + PC12: (pc12, 12, [7, 11, 14]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, [0, 14]), + PC15: (pc15, 15, [0, 14]), +]); + +#[cfg(feature = "gpio-l152x8")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 5, 14]), + PD1: (pd1, 1, [5, 14]), + PD2: (pd2, 2, [2, 11, 14]), + PD3: (pd3, 3, [5, 7, 14]), + PD4: (pd4, 4, [5, 7, 14]), + PD5: (pd5, 5, [7, 14]), + PD6: (pd6, 6, [7, 14]), + PD7: (pd7, 7, [3, 7, 14]), + PD8: (pd8, 8, [7, 11, 14]), + PD9: (pd9, 9, [7, 11, 14]), + PD10: (pd10, 10, [7, 11, 14]), + PD11: (pd11, 11, [7, 11, 14]), + PD12: (pd12, 12, [2, 7, 11, 14]), + PD13: (pd13, 13, [2, 11, 14]), + PD14: (pd14, 14, [2, 11, 14]), + PD15: (pd15, 15, [2, 11, 14]), +]); + +#[cfg(feature = "gpio-l152x8")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 11, 14]), + PE1: (pe1, 1, [3, 11, 14]), + PE2: (pe2, 2, [0, 2, 11, 14]), + PE3: (pe3, 3, [0, 2, 11, 14]), + PE4: (pe4, 4, [0, 2, 14]), + PE5: (pe5, 5, [0, 3, 14]), + PE6: (pe6, 6, [0, 3, 14]), + PE7: (pe7, 7, [14]), + PE8: (pe8, 8, [14]), + PE9: (pe9, 9, [1, 14]), + PE10: (pe10, 10, [1, 14]), + PE11: (pe11, 11, [1, 14]), + PE12: (pe12, 12, [1, 5, 14]), + PE13: (pe13, 13, [5, 14]), + PE14: (pe14, 14, [5, 14]), + PE15: (pe15, 15, [5, 14]), +]); + +#[cfg(feature = "gpio-l152x8")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, [0]), + PH2: (ph2, 2, []), +]); + +#[cfg(feature = "gpio-l152xc")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 7, 14]), + PA1: (pa1, 1, [1, 2, 7, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 7, 11, 14]), + PA3: (pa3, 3, [1, 2, 3, 7, 11, 14]), + PA4: (pa4, 4, [5, 6, 7, 14]), + PA5: (pa5, 5, [1, 5, 14]), + PA6: (pa6, 6, [2, 3, 5, 11, 14]), + PA7: (pa7, 7, [2, 3, 5, 11, 14]), + PA8: (pa8, 8, [0, 7, 11, 14]), + PA9: (pa9, 9, [7, 11, 14]), + PA10: (pa10, 10, [7, 11, 14]), + PA11: (pa11, 11, [5, 7, 10, 14]), + PA12: (pa12, 12, [5, 7, 10, 14]), + PA13: (pa13, 13, [0, 14], super::Debugger), + PA14: (pa14, 14, [0, 14], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 6, 11, 14], super::Debugger), +]); + +#[cfg(feature = "gpio-l152xc")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 11, 14]), + PB1: (pb1, 1, [2, 11, 14]), + PB2: (pb2, 2, [14]), + PB3: (pb3, 3, [0, 1, 5, 6, 11], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 11, 14], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 11, 14]), + PB6: (pb6, 6, [2, 4, 7, 14]), + PB7: (pb7, 7, [2, 4, 7, 14]), + PB8: (pb8, 8, [2, 3, 4, 11]), + PB9: (pb9, 9, [2, 3, 4, 11]), + PB10: (pb10, 10, [1, 4, 7, 11]), + PB11: (pb11, 11, [1, 4, 7, 11]), + PB12: (pb12, 12, [3, 4, 5, 7, 11, 14]), + PB13: (pb13, 13, [3, 5, 7, 11, 14]), + PB14: (pb14, 14, [3, 5, 7, 11, 14]), + PB15: (pb15, 15, [0, 3, 5, 11, 14]), +]); + +#[cfg(feature = "gpio-l152xc")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [11, 14]), + PC1: (pc1, 1, [11, 14]), + PC2: (pc2, 2, [11, 14]), + PC3: (pc3, 3, [11, 14]), + PC4: (pc4, 4, [11, 14]), + PC5: (pc5, 5, [11, 14]), + PC6: (pc6, 6, [2, 5, 11, 14]), + PC7: (pc7, 7, [2, 6, 11, 14]), + PC8: (pc8, 8, [2, 11, 14]), + PC9: (pc9, 9, [2, 11, 14]), + PC10: (pc10, 10, [6, 7, 11, 14]), + PC11: (pc11, 11, [6, 7, 11, 14]), + PC12: (pc12, 12, [6, 7, 11, 14]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, [0, 14]), + PC15: (pc15, 15, [0, 14]), +]); + +#[cfg(feature = "gpio-l152xc")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 5, 14]), + PD1: (pd1, 1, [5, 14]), + PD2: (pd2, 2, [2, 11, 14]), + PD3: (pd3, 3, [5, 7, 14]), + PD4: (pd4, 4, [5, 7, 14]), + PD5: (pd5, 5, [7, 14]), + PD6: (pd6, 6, [7, 14]), + PD7: (pd7, 7, [3, 7, 14]), + PD8: (pd8, 8, [7, 11, 14]), + PD9: (pd9, 9, [7, 11, 14]), + PD10: (pd10, 10, [7, 11, 14]), + PD11: (pd11, 11, [7, 11, 14]), + PD12: (pd12, 12, [2, 7, 11, 14]), + PD13: (pd13, 13, [2, 11, 14]), + PD14: (pd14, 14, [2, 11, 14]), + PD15: (pd15, 15, [2, 11, 14]), +]); + +#[cfg(feature = "gpio-l152xc")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 11, 14]), + PE1: (pe1, 1, [3, 11, 14]), + PE2: (pe2, 2, [0, 2, 11, 14]), + PE3: (pe3, 3, [0, 2, 11, 14]), + PE4: (pe4, 4, [0, 2, 14]), + PE5: (pe5, 5, [0, 3, 14]), + PE6: (pe6, 6, [0, 3, 14]), + PE7: (pe7, 7, [14]), + PE8: (pe8, 8, [14]), + PE9: (pe9, 9, [1, 2, 14]), + PE10: (pe10, 10, [1, 14]), + PE11: (pe11, 11, [1, 14]), + PE12: (pe12, 12, [1, 5, 14]), + PE13: (pe13, 13, [5, 14]), + PE14: (pe14, 14, [5, 14]), + PE15: (pe15, 15, [5, 14]), +]); + +#[cfg(feature = "gpio-l152xc")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, [0]), + PH2: (ph2, 2, []), +]); + +#[cfg(feature = "gpio-l15xxa")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 7, 14]), + PA1: (pa1, 1, [1, 2, 7, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 7, 11, 14]), + PA3: (pa3, 3, [1, 2, 3, 7, 11, 14]), + PA4: (pa4, 4, [5, 6, 7, 14]), + PA5: (pa5, 5, [1, 5, 14]), + PA6: (pa6, 6, [2, 3, 5, 11, 14]), + PA7: (pa7, 7, [2, 3, 5, 11, 14]), + PA8: (pa8, 8, [0, 7, 11, 14]), + PA9: (pa9, 9, [7, 11, 14]), + PA10: (pa10, 10, [7, 11, 14]), + PA11: (pa11, 11, [5, 7, 10, 14]), + PA12: (pa12, 12, [5, 7, 10, 14]), + PA13: (pa13, 13, [0, 14], super::Debugger), + PA14: (pa14, 14, [0, 14], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 6, 11, 14], super::Debugger), +]); + +#[cfg(feature = "gpio-l15xxa")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 11, 14]), + PB1: (pb1, 1, [2, 11, 14]), + PB2: (pb2, 2, [14]), + PB3: (pb3, 3, [0, 1, 5, 6, 11], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 11, 14], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 11, 14]), + PB6: (pb6, 6, [2, 4, 7, 14]), + PB7: (pb7, 7, [2, 4, 7, 14]), + PB8: (pb8, 8, [2, 3, 4, 11]), + PB9: (pb9, 9, [2, 3, 4, 11]), + PB10: (pb10, 10, [1, 4, 7, 11]), + PB11: (pb11, 11, [1, 4, 7, 11]), + PB12: (pb12, 12, [3, 4, 5, 7, 11, 14]), + PB13: (pb13, 13, [3, 5, 7, 11, 14]), + PB14: (pb14, 14, [3, 5, 7, 11, 14]), + PB15: (pb15, 15, [0, 3, 5, 11, 14]), +]); + +#[cfg(feature = "gpio-l15xxa")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [11, 14]), + PC1: (pc1, 1, [11, 14]), + PC2: (pc2, 2, [11, 14]), + PC3: (pc3, 3, [11, 14]), + PC4: (pc4, 4, [11, 14]), + PC5: (pc5, 5, [11, 14]), + PC6: (pc6, 6, [2, 5, 11, 14]), + PC7: (pc7, 7, [2, 6, 11, 14]), + PC8: (pc8, 8, [2, 11, 14]), + PC9: (pc9, 9, [2, 11, 14]), + PC10: (pc10, 10, [6, 7, 11, 14]), + PC11: (pc11, 11, [6, 7, 11, 14]), + PC12: (pc12, 12, [6, 7, 11, 14]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, [0, 14]), + PC15: (pc15, 15, [0, 14]), +]); + +#[cfg(feature = "gpio-l15xxa")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 5, 14]), + PD1: (pd1, 1, [5, 14]), + PD2: (pd2, 2, [2, 11, 14]), + PD3: (pd3, 3, [5, 7, 14]), + PD4: (pd4, 4, [5, 7, 14]), + PD5: (pd5, 5, [7, 14]), + PD6: (pd6, 6, [7, 14]), + PD7: (pd7, 7, [3, 7, 14]), + PD8: (pd8, 8, [7, 11, 14]), + PD9: (pd9, 9, [7, 11, 14]), + PD10: (pd10, 10, [7, 11, 14]), + PD11: (pd11, 11, [7, 11, 14]), + PD12: (pd12, 12, [2, 7, 11, 14]), + PD13: (pd13, 13, [2, 11, 14]), + PD14: (pd14, 14, [2, 11, 14]), + PD15: (pd15, 15, [2, 11, 14]), +]); + +#[cfg(feature = "gpio-l15xxa")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 11, 14]), + PE1: (pe1, 1, [3, 11, 14]), + PE2: (pe2, 2, [0, 2, 11, 14]), + PE3: (pe3, 3, [0, 2, 11, 14]), + PE4: (pe4, 4, [0, 2, 14]), + PE5: (pe5, 5, [0, 3, 14]), + PE6: (pe6, 6, [0, 3, 14]), + PE7: (pe7, 7, [14]), + PE8: (pe8, 8, [14]), + PE9: (pe9, 9, [1, 2, 14]), + PE10: (pe10, 10, [1, 14]), + PE11: (pe11, 11, [1, 14]), + PE12: (pe12, 12, [1, 5, 14]), + PE13: (pe13, 13, [5, 14]), + PE14: (pe14, 14, [5, 14]), + PE15: (pe15, 15, [5, 14]), +]); + +#[cfg(feature = "gpio-l15xxa")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, [0]), + PH2: (ph2, 2, []), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 7, 14]), + PA1: (pa1, 1, [1, 2, 7, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 7, 11, 14]), + PA3: (pa3, 3, [1, 2, 3, 7, 11, 14]), + PA4: (pa4, 4, [5, 6, 7, 14]), + PA5: (pa5, 5, [1, 5, 14]), + PA6: (pa6, 6, [2, 3, 5, 11, 14]), + PA7: (pa7, 7, [2, 3, 5, 11, 14]), + PA8: (pa8, 8, [0, 7, 11, 14]), + PA9: (pa9, 9, [7, 11, 14]), + PA10: (pa10, 10, [7, 11, 14]), + PA11: (pa11, 11, [5, 7, 10, 14]), + PA12: (pa12, 12, [5, 7, 10, 14]), + PA13: (pa13, 13, [0, 14], super::Debugger), + PA14: (pa14, 14, [0, 14], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 6, 11, 14], super::Debugger), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [2, 11, 14]), + PB1: (pb1, 1, [2, 11, 14]), + PB2: (pb2, 2, [14]), + PB3: (pb3, 3, [0, 1, 5, 6, 11], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 11, 14], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 11, 14]), + PB6: (pb6, 6, [2, 4, 7, 14]), + PB7: (pb7, 7, [2, 4, 7, 12, 14]), + PB8: (pb8, 8, [2, 3, 4, 11, 12]), + PB9: (pb9, 9, [2, 3, 4, 11, 12]), + PB10: (pb10, 10, [1, 4, 7, 11]), + PB11: (pb11, 11, [1, 4, 7, 11]), + PB12: (pb12, 12, [3, 4, 5, 7, 11, 14]), + PB13: (pb13, 13, [3, 5, 7, 11, 14]), + PB14: (pb14, 14, [3, 5, 7, 11, 14]), + PB15: (pb15, 15, [0, 3, 5, 11, 14]), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [11, 14]), + PC1: (pc1, 1, [11, 14]), + PC2: (pc2, 2, [11, 14]), + PC3: (pc3, 3, [11, 14]), + PC4: (pc4, 4, [11, 14]), + PC5: (pc5, 5, [11, 14]), + PC6: (pc6, 6, [2, 5, 11, 12, 14]), + PC7: (pc7, 7, [2, 6, 11, 12, 14]), + PC8: (pc8, 8, [2, 11, 12, 14]), + PC9: (pc9, 9, [2, 11, 12, 14]), + PC10: (pc10, 10, [6, 7, 8, 11, 12, 14]), + PC11: (pc11, 11, [6, 7, 8, 11, 12, 14]), + PC12: (pc12, 12, [6, 7, 8, 11, 12, 14]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, [0, 14]), + PC15: (pc15, 15, [0, 14]), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 5, 12, 14]), + PD1: (pd1, 1, [5, 12, 14]), + PD2: (pd2, 2, [2, 8, 11, 12, 14]), + PD3: (pd3, 3, [5, 7, 12, 14]), + PD4: (pd4, 4, [5, 7, 12, 14]), + PD5: (pd5, 5, [7, 12, 14]), + PD6: (pd6, 6, [7, 12, 14]), + PD7: (pd7, 7, [3, 7, 12, 14]), + PD8: (pd8, 8, [7, 11, 12, 14]), + PD9: (pd9, 9, [7, 11, 12, 14]), + PD10: (pd10, 10, [7, 11, 12, 14]), + PD11: (pd11, 11, [7, 11, 12, 14]), + PD12: (pd12, 12, [2, 7, 11, 12, 14]), + PD13: (pd13, 13, [2, 11, 12, 14]), + PD14: (pd14, 14, [2, 11, 12, 14]), + PD15: (pd15, 15, [2, 11, 12, 14]), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 11, 12, 14]), + PE1: (pe1, 1, [3, 11, 12, 14]), + PE2: (pe2, 2, [0, 2, 11, 12, 14]), + PE3: (pe3, 3, [0, 2, 11, 12, 14]), + PE4: (pe4, 4, [0, 2, 12, 14]), + PE5: (pe5, 5, [0, 3, 12, 14]), + PE6: (pe6, 6, [0, 3, 14]), + PE7: (pe7, 7, [12, 14]), + PE8: (pe8, 8, [12, 14]), + PE9: (pe9, 9, [1, 12, 14]), + PE10: (pe10, 10, [1, 12, 14]), + PE11: (pe11, 11, [1, 12, 14]), + PE12: (pe12, 12, [1, 5, 12, 14]), + PE13: (pe13, 13, [5, 12, 14]), + PE14: (pe14, 14, [5, 12, 14]), + PE15: (pe15, 15, [5, 12, 14]), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [12]), + PF1: (pf1, 1, [12]), + PF2: (pf2, 2, [12]), + PF3: (pf3, 3, [12]), + PF4: (pf4, 4, [12]), + PF5: (pf5, 5, [12]), + PF6: (pf6, 6, [2, 14]), + PF7: (pf7, 7, [2, 14]), + PF8: (pf8, 8, [2, 14]), + PF9: (pf9, 9, [2, 14]), + PF10: (pf10, 10, [14]), + PF11: (pf11, 11, [14]), + PF12: (pf12, 12, [12, 14]), + PF13: (pf13, 13, [12, 14]), + PF14: (pf14, 14, [12, 14]), + PF15: (pf15, 15, [12, 14]), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [12, 14]), + PG1: (pg1, 1, [12, 14]), + PG2: (pg2, 2, [12, 14]), + PG3: (pg3, 3, [12, 14]), + PG4: (pg4, 4, [12, 14]), + PG5: (pg5, 5, [12]), + PG6: (pg6, 6, []), + PG7: (pg7, 7, []), + PG8: (pg8, 8, []), + PG9: (pg9, 9, [12]), + PG10: (pg10, 10, [12]), + PG11: (pg11, 11, []), + PG12: (pg12, 12, [12]), + PG13: (pg13, 13, [12]), + PG14: (pg14, 14, [12]), + PG15: (pg15, 15, []), +]); + +#[cfg(feature = "gpio-l162xd")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, [0]), + PH2: (ph2, 2, [12]), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [0, 1, 2, 7, 14]), + PA1: (pa1, 1, [1, 2, 7, 11, 14]), + PA2: (pa2, 2, [1, 2, 3, 7, 11, 14]), + PA3: (pa3, 3, [1, 2, 3, 7, 11, 14]), + PA4: (pa4, 4, [5, 6, 7, 14]), + PA5: (pa5, 5, [1, 5, 14]), + PA6: (pa6, 6, [2, 3, 5, 11, 14]), + PA7: (pa7, 7, [2, 3, 5, 11, 14]), + PA8: (pa8, 8, [0, 7, 11, 14]), + PA9: (pa9, 9, [7, 11, 14]), + PA10: (pa10, 10, [7, 11, 14]), + PA11: (pa11, 11, [5, 7, 10, 14]), + PA12: (pa12, 12, [5, 7, 10, 14]), + PA13: (pa13, 13, [0, 14], super::Debugger), + PA14: (pa14, 14, [0, 14], super::Debugger), + PA15: (pa15, 15, [0, 1, 5, 6, 11, 14], super::Debugger), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 2, 11, 14]), + PB1: (pb1, 1, [0, 2, 11, 14]), + PB2: (pb2, 2, [14]), + PB3: (pb3, 3, [0, 1, 5, 6, 11, 14], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 11, 14], super::Debugger), + PB5: (pb5, 5, [2, 4, 5, 6, 11, 14]), + PB6: (pb6, 6, [2, 4, 7, 14]), + PB7: (pb7, 7, [0, 2, 4, 7, 14]), + PB8: (pb8, 8, [2, 3, 4, 11]), + PB9: (pb9, 9, [2, 3, 4, 11]), + PB10: (pb10, 10, [1, 4, 7, 11]), + PB11: (pb11, 11, [1, 4, 7, 11]), + PB12: (pb12, 12, [3, 4, 5, 7, 11, 14]), + PB13: (pb13, 13, [3, 5, 7, 11, 14]), + PB14: (pb14, 14, [3, 5, 7, 11, 14]), + PB15: (pb15, 15, [0, 3, 5, 11, 14]), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [11, 14]), + PC1: (pc1, 1, [11, 14]), + PC2: (pc2, 2, [11, 14]), + PC3: (pc3, 3, [11, 14]), + PC4: (pc4, 4, [11, 14]), + PC5: (pc5, 5, [11, 14]), + PC6: (pc6, 6, [2, 5, 11, 14]), + PC7: (pc7, 7, [2, 6, 11, 14]), + PC8: (pc8, 8, [2, 11, 14]), + PC9: (pc9, 9, [2, 11, 14]), + PC10: (pc10, 10, [6, 7, 8, 11, 14]), + PC11: (pc11, 11, [6, 7, 8, 11, 14]), + PC12: (pc12, 12, [6, 7, 8, 11, 14]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, [0, 14]), + PC15: (pc15, 15, [0, 14]), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 5, 14]), + PD1: (pd1, 1, [5, 14]), + PD2: (pd2, 2, [2, 8, 11, 14]), + PD3: (pd3, 3, [5, 7, 14]), + PD4: (pd4, 4, [5, 7, 14]), + PD5: (pd5, 5, [7, 14]), + PD6: (pd6, 6, [7, 14]), + PD7: (pd7, 7, [3, 7, 14]), + PD8: (pd8, 8, [7, 11, 14]), + PD9: (pd9, 9, [7, 11, 14]), + PD10: (pd10, 10, [7, 11, 14]), + PD11: (pd11, 11, [7, 11, 14]), + PD12: (pd12, 12, [2, 7, 11, 14]), + PD13: (pd13, 13, [2, 11, 14]), + PD14: (pd14, 14, [2, 11, 14]), + PD15: (pd15, 15, [2, 11, 14]), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 3, 11, 14]), + PE1: (pe1, 1, [3, 11, 14]), + PE2: (pe2, 2, [0, 2, 11, 14]), + PE3: (pe3, 3, [0, 2, 11, 14]), + PE4: (pe4, 4, [0, 2, 14]), + PE5: (pe5, 5, [0, 3, 14]), + PE6: (pe6, 6, [0, 3, 14]), + PE7: (pe7, 7, [14]), + PE8: (pe8, 8, [14]), + PE9: (pe9, 9, [1, 14]), + PE10: (pe10, 10, [1, 14]), + PE11: (pe11, 11, [1, 14]), + PE12: (pe12, 12, [1, 5, 14]), + PE13: (pe13, 13, [5, 14]), + PE14: (pe14, 14, [5, 14]), + PE15: (pe15, 15, [5, 14]), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, []), + PF1: (pf1, 1, []), + PF2: (pf2, 2, []), + PF3: (pf3, 3, []), + PF4: (pf4, 4, []), + PF5: (pf5, 5, []), + PF6: (pf6, 6, [2, 14]), + PF7: (pf7, 7, [2, 14]), + PF8: (pf8, 8, [2, 14]), + PF9: (pf9, 9, [2, 14]), + PF10: (pf10, 10, [14]), + PF11: (pf11, 11, [14]), + PF12: (pf12, 12, [14]), + PF13: (pf13, 13, [14]), + PF14: (pf14, 14, [14]), + PF15: (pf15, 15, [14]), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [14]), + PG1: (pg1, 1, [14]), + PG2: (pg2, 2, [14]), + PG3: (pg3, 3, [14]), + PG4: (pg4, 4, [14]), + PG5: (pg5, 5, []), + PG6: (pg6, 6, []), + PG7: (pg7, 7, []), + PG8: (pg8, 8, []), + PG9: (pg9, 9, []), + PG10: (pg10, 10, []), + PG11: (pg11, 11, []), + PG12: (pg12, 12, []), + PG13: (pg13, 13, []), + PG14: (pg14, 14, []), + PG15: (pg15, 15, []), +]); + +#[cfg(feature = "gpio-l162xe")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [0]), + PH1: (ph1, 1, [0]), + PH2: (ph2, 2, []), +]); diff --git a/src/gpio/l4.rs b/src/gpio/l4.rs new file mode 100644 index 00000000..5a686484 --- /dev/null +++ b/src/gpio/l4.rs @@ -0,0 +1,637 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-l41x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 7, 12, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 7, 14, 15]), + PA2: (pa2, 2, [1, 7, 8, 10, 14, 15]), + PA3: (pa3, 3, [1, 7, 8, 10, 14, 15]), + PA4: (pa4, 4, [5, 7, 14, 15]), + PA5: (pa5, 5, [1, 2, 5, 14, 15]), + PA6: (pa6, 6, [1, 5, 6, 7, 8, 10, 14, 15]), + PA7: (pa7, 7, [1, 4, 5, 10, 15]), + PA8: (pa8, 8, [0, 1, 7, 14, 15]), + PA9: (pa9, 9, [1, 4, 7, 14, 15]), + PA10: (pa10, 10, [1, 4, 7, 10, 15]), + PA11: (pa11, 11, [1, 2, 5, 6, 7, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 7, 9, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l41x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [0, 1, 5, 7, 10, 12, 15]), + PB1: (pb1, 1, [0, 1, 7, 8, 10, 14, 15]), + PB2: (pb2, 2, [0, 1, 4, 15]), + PB3: (pb3, 3, [0, 1, 5, 7, 15], super::Debugger), + PB4: (pb4, 4, [0, 4, 5, 7, 9, 15], super::Debugger), + PB5: (pb5, 5, [0, 1, 4, 5, 7, 9, 14, 15]), + PB6: (pb6, 6, [0, 1, 4, 7, 9, 14, 15]), + PB7: (pb7, 7, [0, 1, 4, 7, 9, 15]), + PB8: (pb8, 8, [4, 14, 15]), + PB9: (pb9, 9, [1, 4, 5, 15]), + PB10: (pb10, 10, [1, 4, 5, 7, 8, 9, 10, 12, 15]), + PB11: (pb11, 11, [1, 4, 7, 8, 10, 15]), + PB12: (pb12, 12, [1, 4, 5, 7, 8, 9, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 7, 8, 9, 14, 15]), + PB14: (pb14, 14, [1, 4, 5, 7, 9, 14, 15]), + PB15: (pb15, 15, [0, 1, 5, 9, 14, 15]), +]); + +#[cfg(feature = "gpio-l41x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [0, 1, 4, 8, 14, 15]), + PC1: (pc1, 1, [0, 1, 4, 8, 15]), + PC2: (pc2, 2, [1, 5, 15]), + PC3: (pc3, 3, [1, 5, 14, 15]), + PC4: (pc4, 4, [7, 15]), + PC5: (pc5, 5, [7, 15]), + PC6: (pc6, 6, [9, 15]), + PC7: (pc7, 7, [9, 15]), + PC8: (pc8, 8, [9, 15]), + PC9: (pc9, 9, [9, 10, 15]), + PC10: (pc10, 10, [0, 7, 9, 15]), + PC11: (pc11, 11, [7, 9, 15]), + PC12: (pc12, 12, [0, 7, 9, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l41x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD2: (pd2, 2, [0, 7, 9, 15]), +]); + +#[cfg(feature = "gpio-l41x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH3: (ph3, 3, [15]), +]); +/* +#[cfg(feature = "gpio-l41x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 7, 12, 13, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 7, 11, 14, 15]), + PA2: (pa2, 2, [1, 7, 8, 10, 11, 12, 14, 15]), + PA3: (pa3, 3, [1, 7, 8, 10, 11, 13, 14, 15]), + PA4: (pa4, 4, [5, 6, 7, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 5, 14, 15]), + PA6: (pa6, 6, [1, 5, 6, 7, 8, 10, 11, 12, 14, 15]), + PA7: (pa7, 7, [1, 4, 5, 10, 11, 12, 15]), + PA8: (pa8, 8, [0, 1, 7, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [1, 4, 7, 11, 13, 14, 15]), + PA10: (pa10, 10, [1, 4, 7, 10, 11, 13, 15]), + PA11: (pa11, 11, [1, 2, 5, 6, 7, 9, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 12, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 12, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 9, 11, 12, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 5, 7, 10, 11, 12, 13, 15]), + PB1: (pb1, 1, [1, 7, 8, 10, 11, 14, 15]), + PB2: (pb2, 2, [0, 1, 4, 11, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 11, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 4, 5, 6, 7, 9, 11, 13, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 5, 6, 7, 9, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 4, 7, 9, 13, 14, 15]), + PB7: (pb7, 7, [1, 4, 7, 9, 11, 15]), + PB8: (pb8, 8, [4, 9, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 4, 5, 9, 11, 12, 13, 15]), + PB10: (pb10, 10, [1, 4, 5, 7, 8, 9, 10, 11, 12, 13, 15]), + PB11: (pb11, 11, [1, 4, 7, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [1, 3, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15]), + PB14: (pb14, 14, [1, 4, 5, 7, 9, 11, 12, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 5, 9, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 8, 11, 14, 15]), + PC1: (pc1, 1, [1, 4, 8, 11, 15]), + PC2: (pc2, 2, [1, 5, 11, 15]), + PC3: (pc3, 3, [1, 5, 11, 13, 14, 15]), + PC4: (pc4, 4, [7, 11, 15]), + PC5: (pc5, 5, [7, 11, 15]), + PC6: (pc6, 6, [9, 11, 12, 15]), + PC7: (pc7, 7, [9, 11, 12, 15]), + PC8: (pc8, 8, [9, 11, 12, 15]), + PC9: (pc9, 9, [9, 10, 11, 12, 15]), + PC10: (pc10, 10, [6, 7, 9, 11, 12, 15]), + PC11: (pc11, 11, [6, 7, 9, 11, 12, 15]), + PC12: (pc12, 12, [6, 7, 9, 11, 12, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 9, 15]), + PD1: (pd1, 1, [5, 9, 15]), + PD2: (pd2, 2, [7, 9, 11, 12, 15]), + PD3: (pd3, 3, [5, 7, 10, 15]), + PD4: (pd4, 4, [5, 7, 10, 15]), + PD5: (pd5, 5, [7, 10, 15]), + PD6: (pd6, 6, [7, 10, 13, 15]), + PD7: (pd7, 7, [7, 10, 15]), + PD8: (pd8, 8, [7, 11, 15]), + PD9: (pd9, 9, [7, 11, 15]), + PD10: (pd10, 10, [7, 9, 11, 15]), + PD11: (pd11, 11, [7, 9, 11, 14, 15]), + PD12: (pd12, 12, [7, 9, 11, 14, 15]), + PD13: (pd13, 13, [9, 11, 14, 15]), + PD14: (pd14, 14, [11, 15]), + PD15: (pd15, 15, [11, 15]), +]); + +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [11, 14, 15]), + PE1: (pe1, 1, [11, 15]), + PE2: (pe2, 2, [0, 9, 11, 13, 15]), + PE3: (pe3, 3, [0, 9, 11, 13, 15]), + PE4: (pe4, 4, [0, 9, 13, 15]), + PE5: (pe5, 5, [0, 9, 13, 15]), + PE6: (pe6, 6, [0, 13, 15]), + PE7: (pe7, 7, [1, 13, 15]), + PE8: (pe8, 8, [1, 13, 15]), + PE9: (pe9, 9, [1, 13, 15]), + PE10: (pe10, 10, [1, 9, 10, 13, 15]), + PE11: (pe11, 11, [1, 9, 10, 15]), + PE12: (pe12, 12, [1, 5, 9, 10, 15]), + PE13: (pe13, 13, [1, 5, 9, 10, 15]), + PE14: (pe14, 14, [1, 2, 3, 5, 10, 15]), + PE15: (pe15, 15, [1, 3, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH3: (ph3, 3, [15]), +]); +/* +#[cfg(feature = "gpio-l43x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 7, 8, 12, 13, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 7, 8, 14, 15]), + PA2: (pa2, 2, [1, 7, 8, 10, 12, 14, 15]), + PA3: (pa3, 3, [1, 7, 8, 10, 13, 14, 15]), + PA4: (pa4, 4, [5, 6, 7, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 5, 6, 14, 15]), + PA6: (pa6, 6, [1, 2, 5, 6, 7, 8, 10, 12, 14, 15]), + PA7: (pa7, 7, [1, 2, 4, 5, 6, 10, 12, 15]), + PA8: (pa8, 8, [0, 1, 6, 7, 13, 14, 15]), + PA9: (pa9, 9, [1, 4, 6, 7, 13, 14, 15]), + PA10: (pa10, 10, [1, 4, 7, 10, 13, 15]), + PA11: (pa11, 11, [1, 2, 5, 6, 7, 9, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 9, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 5, 6, 7, 10, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 6, 7, 8, 10, 14, 15]), + PB2: (pb2, 2, [0, 1, 4, 6, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 2, 4, 5, 6, 7, 9, 13, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 9, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 4, 5, 7, 8, 9, 13, 14, 15]), + PB7: (pb7, 7, [1, 4, 5, 7, 8, 9, 15]), + PB8: (pb8, 8, [4, 9, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 4, 5, 9, 12, 13, 15]), + PB10: (pb10, 10, [1, 3, 4, 5, 7, 8, 9, 10, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 7, 8, 10, 12, 15]), + PB12: (pb12, 12, [1, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PB14: (pb14, 14, [1, 4, 5, 6, 7, 9, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 5, 6, 9, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2, 4, 8, 14, 15]), + PC1: (pc1, 1, [0, 1, 2, 4, 8, 15]), + PC2: (pc2, 2, [1, 5, 6, 15]), + PC3: (pc3, 3, [1, 5, 13, 14, 15]), + PC4: (pc4, 4, [7, 15]), + PC5: (pc5, 5, [7, 15]), + PC6: (pc6, 6, [2, 6, 9, 12, 15]), + PC7: (pc7, 7, [2, 6, 9, 12, 15]), + PC8: (pc8, 8, [2, 9, 12, 15]), + PC9: (pc9, 9, [2, 9, 10, 12, 15]), + PC10: (pc10, 10, [0, 6, 7, 8, 9, 12, 15]), + PC11: (pc11, 11, [6, 7, 8, 9, 12, 15]), + PC12: (pc12, 12, [0, 6, 7, 9, 12, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 9, 15]), + PD1: (pd1, 1, [5, 9, 15]), + PD2: (pd2, 2, [0, 2, 7, 9, 12, 15]), + PD3: (pd3, 3, [5, 6, 7, 10, 15]), + PD4: (pd4, 4, [5, 6, 7, 10, 15]), + PD5: (pd5, 5, [7, 10, 15]), + PD6: (pd6, 6, [6, 7, 10, 13, 15]), + PD7: (pd7, 7, [6, 7, 10, 15]), + PD8: (pd8, 8, [7, 15]), + PD9: (pd9, 9, [7, 15]), + PD10: (pd10, 10, [7, 9, 15]), + PD11: (pd11, 11, [4, 7, 9, 14, 15]), + PD12: (pd12, 12, [4, 7, 9, 14, 15]), + PD13: (pd13, 13, [4, 9, 14, 15]), + PD14: (pd14, 14, [15]), + PD15: (pd15, 15, [15]), +]); + +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [14, 15]), + PE1: (pe1, 1, [15]), + PE2: (pe2, 2, [0, 2, 9, 13, 15]), + PE3: (pe3, 3, [0, 2, 9, 13, 15]), + PE4: (pe4, 4, [0, 2, 6, 9, 13, 15]), + PE5: (pe5, 5, [0, 2, 6, 9, 13, 15]), + PE6: (pe6, 6, [0, 2, 13, 15]), + PE7: (pe7, 7, [1, 6, 13, 15]), + PE8: (pe8, 8, [1, 6, 13, 15]), + PE9: (pe9, 9, [1, 6, 13, 15]), + PE10: (pe10, 10, [1, 9, 10, 13, 15]), + PE11: (pe11, 11, [1, 9, 10, 15]), + PE12: (pe12, 12, [1, 5, 9, 10, 15]), + PE13: (pe13, 13, [1, 5, 9, 10, 15]), + PE14: (pe14, 14, [1, 2, 3, 5, 10, 15]), + PE15: (pe15, 15, [1, 3, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH3: (ph3, 3, [15]), +]); +/* +#[cfg(feature = "gpio-l45x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 13, 14, 15]), + PA1: (pa1, 1, [1, 2, 7, 8, 11, 14, 15]), + PA2: (pa2, 2, [1, 2, 7, 11, 13, 14, 15]), + PA3: (pa3, 3, [1, 2, 7, 11, 14, 15]), + PA4: (pa4, 4, [5, 6, 7, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 3, 5, 14, 15]), + PA6: (pa6, 6, [1, 2, 3, 5, 7, 10, 11, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 5, 10, 11, 14, 15]), + PA8: (pa8, 8, [0, 1, 7, 10, 11, 14, 15]), + PA9: (pa9, 9, [1, 7, 11, 14, 15]), + PA10: (pa10, 10, [1, 7, 10, 11, 14, 15]), + PA11: (pa11, 11, [1, 2, 7, 9, 10, 12, 15]), + PA12: (pa12, 12, [1, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 15], super::Debugger), + PA14: (pa14, 14, [0, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 5, 6, 8, 9, 11, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 7, 10, 11, 12, 15]), + PB1: (pb1, 1, [1, 2, 3, 6, 7, 10, 11, 14, 15]), + PB2: (pb2, 2, [0, 1, 4, 6, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 11, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 2, 5, 6, 7, 8, 9, 11, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 6, 7, 9, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 6, 7, 8, 9, 11, 12, 13, 14, 15]), + PB8: (pb8, 8, [2, 4, 6, 9, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 4, 5, 6, 9, 11, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 4, 5, 6, 7, 8, 10, 11, 12, 13, 15]), + PB11: (pb11, 11, [1, 4, 6, 7, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [1, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15]), + PB14: (pb14, 14, [1, 3, 4, 5, 6, 7, 9, 11, 12, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 3, 5, 6, 9, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 6, 8, 11, 14, 15]), + PC1: (pc1, 1, [1, 4, 6, 8, 11, 15]), + PC2: (pc2, 2, [1, 5, 6, 11, 15]), + PC3: (pc3, 3, [1, 5, 11, 13, 14, 15]), + PC4: (pc4, 4, [7, 11, 15]), + PC5: (pc5, 5, [7, 11, 15]), + PC6: (pc6, 6, [2, 3, 6, 9, 11, 12, 13, 15]), + PC7: (pc7, 7, [2, 3, 6, 9, 11, 12, 13, 15]), + PC8: (pc8, 8, [2, 3, 9, 11, 12, 15]), + PC9: (pc9, 9, [1, 2, 3, 9, 10, 11, 12, 13, 14, 15]), + PC10: (pc10, 10, [6, 7, 8, 9, 11, 12, 13, 15]), + PC11: (pc11, 11, [6, 7, 8, 9, 11, 12, 13, 15]), + PC12: (pc12, 12, [6, 7, 8, 9, 11, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 6, 9, 12, 15]), + PD1: (pd1, 1, [5, 6, 9, 12, 15]), + PD2: (pd2, 2, [2, 7, 8, 9, 11, 12, 15]), + PD3: (pd3, 3, [5, 6, 7, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 12, 15]), + PD5: (pd5, 5, [7, 12, 15]), + PD6: (pd6, 6, [6, 7, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 12, 15]), + PD8: (pd8, 8, [7, 11, 12, 15]), + PD9: (pd9, 9, [7, 11, 12, 13, 15]), + PD10: (pd10, 10, [7, 9, 11, 12, 13, 15]), + PD11: (pd11, 11, [7, 9, 11, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 7, 9, 11, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 9, 11, 12, 14, 15]), + PD14: (pd14, 14, [2, 11, 12, 15]), + PD15: (pd15, 15, [2, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 11, 12, 14, 15]), + PE1: (pe1, 1, [11, 12, 14, 15]), + PE2: (pe2, 2, [0, 2, 9, 11, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 9, 11, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 6, 9, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 6, 9, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 12, 13, 15]), + PE9: (pe9, 9, [1, 6, 12, 13, 15]), + PE10: (pe10, 10, [1, 6, 9, 10, 12, 13, 15]), + PE11: (pe11, 11, [1, 6, 9, 10, 12, 15]), + PE12: (pe12, 12, [1, 5, 6, 9, 10, 12, 15]), + PE13: (pe13, 13, [1, 5, 6, 9, 10, 12, 15]), + PE14: (pe14, 14, [1, 2, 3, 5, 10, 12, 15]), + PE15: (pe15, 15, [1, 3, 5, 10, 12, 15]), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12, 15]), + PF1: (pf1, 1, [4, 12, 15]), + PF2: (pf2, 2, [4, 12, 15]), + PF3: (pf3, 3, [12, 15]), + PF4: (pf4, 4, [12, 15]), + PF5: (pf5, 5, [12, 15]), + PF6: (pf6, 6, [1, 2, 13, 15]), + PF7: (pf7, 7, [2, 13, 15]), + PF8: (pf8, 8, [2, 13, 15]), + PF9: (pf9, 9, [2, 13, 14, 15]), + PF10: (pf10, 10, [14, 15]), + PF11: (pf11, 11, [15]), + PF12: (pf12, 12, [12, 15]), + PF13: (pf13, 13, [6, 12, 15]), + PF14: (pf14, 14, [6, 9, 12, 15]), + PF15: (pf15, 15, [9, 12, 15]), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [9, 12, 15]), + PG1: (pg1, 1, [9, 12, 15]), + PG2: (pg2, 2, [5, 12, 13, 15]), + PG3: (pg3, 3, [5, 12, 13, 15]), + PG4: (pg4, 4, [5, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 12, 13, 15]), + PG6: (pg6, 6, [4, 8, 15]), + PG7: (pg7, 7, [4, 8, 12, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [6, 7, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 6, 7, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 6, 7, 13, 14, 15]), + PG12: (pg12, 12, [1, 6, 7, 12, 13, 15]), + PG13: (pg13, 13, [4, 7, 12, 15]), + PG14: (pg14, 14, [4, 12, 15]), + PG15: (pg15, 15, [1, 4, 15]), +]); + +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), +]); +/* +#[cfg(feature = "gpio-l47x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 13, 14, 15]), + PA1: (pa1, 1, [1, 2, 4, 5, 7, 8, 11, 14, 15]), + PA2: (pa2, 2, [1, 2, 7, 8, 10, 11, 13, 14, 15]), + PA3: (pa3, 3, [1, 2, 7, 8, 10, 11, 13, 14, 15]), + PA4: (pa4, 4, [5, 6, 7, 10, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 3, 5, 14, 15]), + PA6: (pa6, 6, [1, 2, 3, 4, 5, 7, 8, 10, 11, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 10, 11, 14, 15]), + PA8: (pa8, 8, [0, 1, 7, 10, 11, 12, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 5, 7, 11, 13, 14, 15]), + PA10: (pa10, 10, [1, 5, 7, 10, 11, 13, 14, 15]), + PA11: (pa11, 11, [1, 2, 5, 7, 9, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 12, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 10, 12, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 5, 7, 10, 11, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 3, 6, 7, 8, 10, 11, 14, 15]), + PB2: (pb2, 2, [0, 1, 4, 6, 11, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 10, 11, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 2, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB8: (pb8, 8, [2, 4, 6, 9, 10, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 4, 5, 6, 9, 10, 11, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 6, 7, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB14: (pb14, 14, [1, 3, 4, 5, 6, 7, 9, 11, 12, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 3, 5, 6, 9, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 2, 4, 6, 8, 11, 14, 15]), + PC1: (pc1, 1, [0, 1, 2, 3, 4, 6, 8, 10, 11, 13, 15]), + PC2: (pc2, 2, [1, 5, 6, 10, 11, 15]), + PC3: (pc3, 3, [1, 5, 10, 11, 13, 14, 15]), + PC4: (pc4, 4, [7, 10, 11, 15]), + PC5: (pc5, 5, [7, 11, 15]), + PC6: (pc6, 6, [2, 3, 6, 9, 10, 11, 12, 13, 15]), + PC7: (pc7, 7, [2, 3, 6, 9, 10, 11, 12, 13, 15]), + PC8: (pc8, 8, [2, 3, 9, 10, 11, 12, 15]), + PC9: (pc9, 9, [1, 2, 3, 4, 6, 9, 10, 11, 12, 13, 14, 15]), + PC10: (pc10, 10, [0, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC11: (pc11, 11, [5, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC12: (pc12, 12, [0, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 6, 9, 12, 15]), + PD1: (pd1, 1, [5, 6, 9, 12, 15]), + PD2: (pd2, 2, [0, 2, 7, 8, 9, 10, 11, 12, 15]), + PD3: (pd3, 3, [3, 4, 5, 6, 7, 10, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [4, 5, 6, 7, 10, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 10, 12, 15]), + PD8: (pd8, 8, [7, 10, 11, 12, 15]), + PD9: (pd9, 9, [7, 10, 11, 12, 13, 15]), + PD10: (pd10, 10, [7, 9, 11, 12, 13, 15]), + PD11: (pd11, 11, [4, 7, 9, 11, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 4, 7, 9, 11, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 4, 9, 11, 12, 14, 15]), + PD14: (pd14, 14, [2, 11, 12, 15]), + PD15: (pd15, 15, [2, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 10, 11, 12, 14, 15]), + PE1: (pe1, 1, [10, 11, 12, 14, 15]), + PE2: (pe2, 2, [0, 2, 9, 11, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 9, 11, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 6, 9, 10, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 6, 9, 10, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 10, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 12, 13, 15]), + PE9: (pe9, 9, [1, 6, 12, 13, 15]), + PE10: (pe10, 10, [1, 6, 9, 10, 12, 13, 15]), + PE11: (pe11, 11, [1, 6, 9, 10, 12, 15]), + PE12: (pe12, 12, [1, 5, 6, 9, 10, 12, 15]), + PE13: (pe13, 13, [1, 5, 6, 9, 10, 12, 15]), + PE14: (pe14, 14, [1, 2, 3, 5, 10, 12, 15]), + PE15: (pe15, 15, [1, 3, 5, 10, 12, 15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12, 15]), + PF1: (pf1, 1, [4, 12, 15]), + PF2: (pf2, 2, [4, 12, 15]), + PF3: (pf3, 3, [12, 15]), + PF4: (pf4, 4, [12, 15]), + PF5: (pf5, 5, [12, 15]), + PF6: (pf6, 6, [1, 2, 10, 13, 15]), + PF7: (pf7, 7, [2, 10, 13, 15]), + PF8: (pf8, 8, [2, 10, 13, 15]), + PF9: (pf9, 9, [2, 10, 13, 14, 15]), + PF10: (pf10, 10, [3, 10, 14, 15]), + PF11: (pf11, 11, [10, 15]), + PF12: (pf12, 12, [12, 15]), + PF13: (pf13, 13, [4, 6, 12, 15]), + PF14: (pf14, 14, [4, 6, 9, 12, 15]), + PF15: (pf15, 15, [4, 9, 12, 15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [9, 12, 15]), + PG1: (pg1, 1, [9, 12, 15]), + PG2: (pg2, 2, [5, 12, 13, 15]), + PG3: (pg3, 3, [5, 12, 13, 15]), + PG4: (pg4, 4, [5, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 12, 13, 15]), + PG6: (pg6, 6, [4, 8, 15]), + PG7: (pg7, 7, [4, 8, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [6, 7, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 6, 7, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 6, 7, 13, 14, 15]), + PG12: (pg12, 12, [1, 6, 7, 12, 13, 15]), + PG13: (pg13, 13, [4, 7, 12, 15]), + PG14: (pg14, 14, [4, 12, 15]), + PG15: (pg15, 15, [1, 4, 10, 15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [3, 15]), + PH3: (ph3, 3, [15]), + PH4: (ph4, 4, [4, 15]), + PH5: (ph5, 5, [4, 10, 15]), + PH6: (ph6, 6, [4, 10, 15]), + PH7: (ph7, 7, [4, 10, 15]), + PH8: (ph8, 8, [4, 10, 15]), + PH9: (ph9, 9, [4, 10, 15]), + PH10: (ph10, 10, [2, 10, 15]), + PH11: (ph11, 11, [2, 10, 15]), + PH12: (ph12, 12, [2, 10, 15]), + PH13: (ph13, 13, [3, 9, 15]), + PH14: (ph14, 14, [3, 10, 15]), + PH15: (ph15, 15, [3, 10, 15]), +]); + +#[cfg(feature = "gpio-l49x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 5, 10, 15]), + PI1: (pi1, 1, [5, 10, 15]), + PI2: (pi2, 2, [3, 5, 10, 15]), + PI3: (pi3, 3, [3, 5, 10, 15]), + PI4: (pi4, 4, [3, 10, 15]), + PI5: (pi5, 5, [3, 10, 15]), + PI6: (pi6, 6, [3, 10, 15]), + PI7: (pi7, 7, [3, 10, 15]), + PI8: (pi8, 8, [10, 15]), + PI9: (pi9, 9, [9, 15]), + PI10: (pi10, 10, [15]), + PI11: (pi11, 11, [15]), +]); diff --git a/src/gpio/l4p.rs b/src/gpio/l4p.rs new file mode 100644 index 00000000..ec2800ea --- /dev/null +++ b/src/gpio/l4p.rs @@ -0,0 +1,357 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 13, 14, 15]), + PA1: (pa1, 1, [1, 2, 4, 5, 7, 8, 10, 12, 14, 15]), + PA2: (pa2, 2, [1, 2, 7, 8, 10, 13, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 7, 8, 10, 13, 14, 15]), + PA4: (pa4, 4, [3, 5, 6, 7, 10, 11, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 3, 4, 5, 11, 14, 15]), + PA6: (pa6, 6, [2, 4, 5, 7, 8, 10, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 10, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 7, 10, 11, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 5, 7, 11, 13, 14, 15]), + PA10: (pa10, 10, [1, 3, 5, 7, 10, 11, 13, 14, 15]), + PA11: (pa11, 11, [1, 5, 7, 9, 10, 11, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 9, 10, 11, 15]), + PA13: (pa13, 13, [0, 1, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 10, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 5, 7, 10, 11, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 3, 6, 7, 8, 10, 11, 14, 15]), + PB2: (pb2, 2, [1, 4, 6, 10, 15]), + PB3: (pb3, 3, [0, 1, 3, 5, 6, 7, 10, 12, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 4, 5, 7, 9, 10, 11, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB8: (pb8, 8, [2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 7, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PB14: (pb14, 14, [1, 3, 4, 5, 6, 7, 9, 10, 11, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 3, 5, 6, 9, 10, 11, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 7, 8, 11, 12, 13, 14, 15]), + PC1: (pc1, 1, [0, 1, 3, 4, 8, 10, 13, 15]), + PC2: (pc2, 2, [1, 5, 6, 10, 11, 15]), + PC3: (pc3, 3, [1, 3, 5, 10, 13, 14, 15]), + PC4: (pc4, 4, [5, 7, 10, 15]), + PC5: (pc5, 5, [3, 4, 7, 11, 15]), + PC6: (pc6, 6, [2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC7: (pc7, 7, [2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC8: (pc8, 8, [2, 3, 9, 10, 12, 15]), + PC9: (pc9, 9, [0, 2, 3, 4, 6, 9, 10, 12, 13, 14, 15]), + PC10: (pc10, 10, [0, 4, 6, 7, 8, 9, 10, 12, 13, 15]), + PC11: (pc11, 11, [4, 5, 6, 7, 8, 9, 10, 12, 13, 15]), + PC12: (pc12, 12, [0, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 9, 11, 12, 15]), + PD1: (pd1, 1, [5, 9, 11, 12, 15]), + PD2: (pd2, 2, [0, 2, 7, 8, 9, 10, 12, 15]), + PD3: (pd3, 3, [3, 4, 5, 6, 7, 10, 11, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 8, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 8, 10, 12, 15]), + PD8: (pd8, 8, [7, 10, 11, 12, 15]), + PD9: (pd9, 9, [7, 10, 11, 12, 13, 15]), + PD10: (pd10, 10, [7, 9, 11, 12, 13, 15]), + PD11: (pd11, 11, [4, 7, 9, 11, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 4, 7, 9, 11, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 4, 9, 12, 14, 15]), + PD14: (pd14, 14, [2, 11, 12, 15]), + PD15: (pd15, 15, [2, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 10, 11, 12, 14, 15]), + PE1: (pe1, 1, [10, 11, 12, 14, 15]), + PE2: (pe2, 2, [0, 2, 3, 9, 11, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 3, 9, 11, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 6, 9, 10, 11, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 6, 9, 10, 11, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 3, 10, 11, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 11, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 11, 12, 13, 15]), + PE9: (pe9, 9, [1, 6, 10, 11, 12, 13, 15]), + PE10: (pe10, 10, [1, 9, 10, 11, 12, 13, 15]), + PE11: (pe11, 11, [1, 9, 10, 11, 12, 15]), + PE12: (pe12, 12, [1, 5, 9, 10, 11, 12, 15]), + PE13: (pe13, 13, [1, 5, 9, 10, 11, 12, 15]), + PE14: (pe14, 14, [1, 3, 5, 10, 11, 12, 15]), + PE15: (pe15, 15, [3, 5, 10, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 12, 15]), + PF1: (pf1, 1, [4, 5, 12, 15]), + PF2: (pf2, 2, [4, 5, 12, 15]), + PF3: (pf3, 3, [5, 12, 15]), + PF4: (pf4, 4, [5, 12, 15]), + PF5: (pf5, 5, [5, 12, 15]), + PF6: (pf6, 6, [1, 2, 10, 13, 15]), + PF7: (pf7, 7, [2, 10, 13, 15]), + PF8: (pf8, 8, [2, 10, 13, 15]), + PF9: (pf9, 9, [2, 10, 13, 14, 15]), + PF10: (pf10, 10, [3, 4, 6, 10, 13, 14, 15]), + PF11: (pf11, 11, [3, 9, 10, 15]), + PF12: (pf12, 12, [5, 11, 12, 15]), + PF13: (pf13, 13, [4, 11, 12, 15]), + PF14: (pf14, 14, [4, 9, 11, 12, 15]), + PF15: (pf15, 15, [4, 9, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [5, 9, 12, 15]), + PG1: (pg1, 1, [5, 9, 12, 15]), + PG2: (pg2, 2, [5, 11, 12, 13, 15]), + PG3: (pg3, 3, [5, 11, 12, 13, 15]), + PG4: (pg4, 4, [5, 11, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 11, 12, 13, 15]), + PG6: (pg6, 6, [3, 4, 8, 9, 15]), + PG7: (pg7, 7, [3, 4, 5, 6, 8, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [5, 6, 7, 11, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 5, 6, 7, 11, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 3, 6, 7, 11, 13, 14, 15]), + PG12: (pg12, 12, [1, 5, 6, 7, 11, 12, 13, 15]), + PG13: (pg13, 13, [4, 7, 11, 12, 15]), + PG14: (pg14, 14, [4, 11, 12, 15]), + PG15: (pg15, 15, [1, 4, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [3, 15]), + PH3: (ph3, 3, [15]), + PH4: (ph4, 4, [4, 5, 10, 15]), + PH5: (ph5, 5, [4, 10, 15]), + PH6: (ph6, 6, [4, 5, 10, 15]), + PH7: (ph7, 7, [4, 5, 10, 15]), + PH8: (ph8, 8, [4, 5, 10, 15]), + PH9: (ph9, 9, [4, 5, 10, 15]), + PH10: (ph10, 10, [2, 5, 10, 15]), + PH11: (ph11, 11, [2, 5, 10, 15]), + PH12: (ph12, 12, [2, 5, 10, 15]), + PH13: (ph13, 13, [3, 9, 15]), + PH14: (ph14, 14, [3, 10, 15]), + PH15: (ph15, 15, [3, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-l4p")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 3, 5, 10, 15]), + PI1: (pi1, 1, [5, 10, 15]), + PI2: (pi2, 2, [3, 5, 10, 15]), + PI3: (pi3, 3, [3, 5, 10, 15]), + PI4: (pi4, 4, [3, 10, 15]), + PI5: (pi5, 5, [3, 5, 10, 15]), + PI6: (pi6, 6, [3, 5, 10, 15]), + PI7: (pi7, 7, [3, 5, 10, 15]), + PI8: (pi8, 8, [5, 10, 15]), + PI9: (pi9, 9, [5, 9, 15]), + PI10: (pi10, 10, [5, 10, 15]), + PI11: (pi11, 11, [5, 10, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 13, 14, 15]), + PA1: (pa1, 1, [1, 2, 4, 5, 7, 8, 10, 14, 15]), + PA2: (pa2, 2, [1, 2, 7, 8, 10, 13, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 7, 8, 10, 13, 14, 15]), + PA4: (pa4, 4, [3, 5, 6, 7, 10, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 3, 5, 14, 15]), + PA6: (pa6, 6, [2, 4, 5, 7, 8, 10, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 10, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 7, 10, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 5, 7, 13, 14, 15]), + PA10: (pa10, 10, [1, 3, 5, 7, 10, 13, 14, 15]), + PA11: (pa11, 11, [1, 5, 7, 9, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 10, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 9, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 5, 7, 10, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 3, 6, 7, 8, 10, 14, 15]), + PB2: (pb2, 2, [0, 1, 4, 6, 10, 11, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 10, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 4, 5, 6, 7, 9, 10, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB8: (pb8, 8, [2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 6, 7, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [3, 4, 5, 6, 7, 8, 9, 13, 14, 15]), + PB13: (pb13, 13, [1, 4, 5, 6, 7, 8, 9, 13, 14, 15]), + PB14: (pb14, 14, [1, 3, 4, 5, 6, 7, 9, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 3, 5, 6, 9, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 6, 8, 13, 14, 15]), + PC1: (pc1, 1, [0, 1, 3, 4, 6, 8, 10, 13, 15]), + PC2: (pc2, 2, [1, 5, 6, 10, 15]), + PC3: (pc3, 3, [1, 3, 5, 10, 13, 14, 15]), + PC4: (pc4, 4, [7, 10, 15]), + PC5: (pc5, 5, [3, 7, 15]), + PC6: (pc6, 6, [2, 3, 6, 8, 9, 10, 11, 12, 13, 15]), + PC7: (pc7, 7, [2, 3, 6, 8, 9, 10, 11, 12, 13, 15]), + PC8: (pc8, 8, [2, 3, 9, 10, 12, 15]), + PC9: (pc9, 9, [0, 2, 3, 4, 6, 9, 10, 12, 13, 14, 15]), + PC10: (pc10, 10, [0, 6, 7, 8, 9, 10, 12, 13, 15]), + PC11: (pc11, 11, [4, 5, 6, 7, 8, 9, 10, 12, 13, 15]), + PC12: (pc12, 12, [0, 6, 7, 8, 9, 10, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 6, 9, 11, 12, 15]), + PD1: (pd1, 1, [5, 6, 9, 11, 12, 15]), + PD2: (pd2, 2, [0, 2, 7, 8, 9, 10, 12, 15]), + PD3: (pd3, 3, [3, 4, 5, 6, 7, 10, 11, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [3, 4, 5, 6, 7, 10, 11, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 10, 12, 15]), + PD8: (pd8, 8, [7, 10, 11, 12, 15]), + PD9: (pd9, 9, [7, 10, 11, 12, 13, 15]), + PD10: (pd10, 10, [7, 9, 11, 12, 13, 15]), + PD11: (pd11, 11, [4, 7, 9, 11, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 4, 7, 9, 11, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 4, 9, 12, 14, 15]), + PD14: (pd14, 14, [2, 11, 12, 15]), + PD15: (pd15, 15, [2, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 10, 11, 12, 14, 15]), + PE1: (pe1, 1, [10, 11, 12, 14, 15]), + PE2: (pe2, 2, [0, 2, 3, 9, 11, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 3, 9, 11, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 6, 9, 10, 11, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 6, 9, 10, 11, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 3, 10, 11, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 11, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 11, 12, 13, 15]), + PE9: (pe9, 9, [1, 6, 11, 12, 13, 15]), + PE10: (pe10, 10, [1, 6, 9, 10, 11, 12, 13, 15]), + PE11: (pe11, 11, [1, 6, 9, 10, 11, 12, 15]), + PE12: (pe12, 12, [1, 5, 6, 9, 10, 11, 12, 15]), + PE13: (pe13, 13, [1, 5, 6, 9, 10, 11, 12, 15]), + PE14: (pe14, 14, [1, 3, 5, 10, 11, 12, 15]), + PE15: (pe15, 15, [3, 5, 10, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 12, 15]), + PF1: (pf1, 1, [4, 5, 12, 15]), + PF2: (pf2, 2, [4, 5, 12, 15]), + PF3: (pf3, 3, [5, 12, 15]), + PF4: (pf4, 4, [5, 12, 15]), + PF5: (pf5, 5, [12, 15]), + PF6: (pf6, 6, [1, 2, 10, 13, 15]), + PF7: (pf7, 7, [2, 10, 13, 15]), + PF8: (pf8, 8, [2, 10, 13, 15]), + PF9: (pf9, 9, [2, 10, 13, 14, 15]), + PF10: (pf10, 10, [3, 6, 10, 13, 14, 15]), + PF11: (pf11, 11, [9, 10, 11, 15]), + PF12: (pf12, 12, [5, 11, 12, 15]), + PF13: (pf13, 13, [4, 6, 11, 12, 15]), + PF14: (pf14, 14, [4, 6, 9, 11, 12, 15]), + PF15: (pf15, 15, [4, 9, 11, 12, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [5, 9, 12, 15]), + PG1: (pg1, 1, [5, 9, 12, 15]), + PG2: (pg2, 2, [5, 12, 13, 15]), + PG3: (pg3, 3, [5, 12, 13, 15]), + PG4: (pg4, 4, [5, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 12, 13, 15]), + PG6: (pg6, 6, [3, 4, 8, 9, 11, 15]), + PG7: (pg7, 7, [3, 4, 5, 6, 8, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [5, 6, 7, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 5, 6, 7, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 3, 6, 7, 13, 14, 15]), + PG12: (pg12, 12, [1, 5, 6, 7, 12, 13, 15]), + PG13: (pg13, 13, [4, 7, 11, 12, 15]), + PG14: (pg14, 14, [4, 11, 12, 15]), + PG15: (pg15, 15, [1, 4, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [3, 15]), + PH3: (ph3, 3, [15]), + PH4: (ph4, 4, [4, 5, 15]), + PH5: (ph5, 5, [4, 10, 15]), + PH6: (ph6, 6, [4, 5, 10, 15]), + PH7: (ph7, 7, [4, 10, 15]), + PH8: (ph8, 8, [4, 5, 10, 15]), + PH9: (ph9, 9, [4, 5, 10, 15]), + PH10: (ph10, 10, [2, 5, 10, 15]), + PH11: (ph11, 11, [2, 5, 10, 15]), + PH12: (ph12, 12, [2, 5, 10, 15]), + PH13: (ph13, 13, [3, 9, 15]), + PH14: (ph14, 14, [3, 10, 15]), + PH15: (ph15, 15, [3, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-l4rx")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 3, 5, 10, 15]), + PI1: (pi1, 1, [5, 10, 15]), + PI2: (pi2, 2, [3, 5, 10, 15]), + PI3: (pi3, 3, [3, 5, 10, 15]), + PI4: (pi4, 4, [3, 10, 15]), + PI5: (pi5, 5, [3, 5, 10, 15]), + PI6: (pi6, 6, [3, 5, 10, 15]), + PI7: (pi7, 7, [3, 10, 15]), + PI8: (pi8, 8, [5, 10, 15]), + PI9: (pi9, 9, [5, 9, 15]), + PI10: (pi10, 10, [5, 15]), + PI11: (pi11, 11, [5, 15]), +]); diff --git a/src/gpio/l5.rs b/src/gpio/l5.rs new file mode 100644 index 00000000..91097179 --- /dev/null +++ b/src/gpio/l5.rs @@ -0,0 +1,158 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 7, 8, 13, 14, 15]), + PA1: (pa1, 1, [1, 2, 4, 5, 7, 8, 10, 14, 15]), + PA2: (pa2, 2, [1, 2, 7, 8, 10, 11, 13, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 7, 8, 10, 13, 14, 15]), + PA4: (pa4, 4, [3, 5, 6, 7, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 3, 5, 14, 15]), + PA6: (pa6, 6, [2, 5, 7, 8, 10, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 2, 3, 4, 5, 10, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 7, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 7, 13, 14, 15]), + PA10: (pa10, 10, [1, 3, 7, 10, 13, 14, 15]), + PA11: (pa11, 11, [1, 5, 7, 9, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 5, 7, 10, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 3, 6, 7, 8, 10, 14, 15]), + PB2: (pb2, 2, [1, 4, 6, 10, 11, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 10, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 2, 4, 5, 6, 7, 8, 9, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 4, 5, 7, 9, 12, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 4, 5, 7, 8, 9, 12, 13, 14, 15]), + PB8: (pb8, 8, [2, 3, 4, 5, 8, 9, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 8, 9, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 7, 8, 10, 12, 15]), + PB12: (pb12, 12, [3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PB13: (pb13, 13, [1, 2, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15]), + PB14: (pb14, 14, [1, 2, 3, 4, 5, 6, 7, 9, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 3, 5, 6, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 3, 4, 8, 12, 13, 14, 15]), + PC1: (pc1, 1, [0, 1, 3, 4, 8, 10, 13, 15]), + PC2: (pc2, 2, [1, 5, 6, 10, 15]), + PC3: (pc3, 3, [1, 2, 3, 5, 10, 13, 14, 15]), + PC4: (pc4, 4, [7, 10, 15]), + PC5: (pc5, 5, [3, 7, 15]), + PC6: (pc6, 6, [2, 3, 6, 8, 9, 12, 13, 15]), + PC7: (pc7, 7, [2, 3, 6, 8, 9, 12, 13, 15]), + PC8: (pc8, 8, [2, 3, 9, 12, 15]), + PC9: (pc9, 9, [0, 2, 3, 9, 10, 12, 13, 14, 15]), + PC10: (pc10, 10, [0, 2, 6, 7, 8, 9, 12, 13, 15]), + PC11: (pc11, 11, [2, 5, 6, 7, 8, 9, 11, 12, 13, 15]), + PC12: (pc12, 12, [0, 6, 7, 8, 9, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 9, 12, 15]), + PD1: (pd1, 1, [5, 9, 12, 15]), + PD2: (pd2, 2, [0, 2, 7, 8, 9, 12, 15]), + PD3: (pd3, 3, [3, 5, 6, 7, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 10, 12, 15]), + PD5: (pd5, 5, [7, 10, 12, 15]), + PD6: (pd6, 6, [3, 5, 6, 7, 10, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 10, 12, 15]), + PD8: (pd8, 8, [7, 12, 15]), + PD9: (pd9, 9, [7, 12, 13, 15]), + PD10: (pd10, 10, [7, 9, 12, 13, 15]), + PD11: (pd11, 11, [4, 7, 9, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 4, 7, 9, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 4, 9, 12, 14, 15]), + PD14: (pd14, 14, [2, 12, 15]), + PD15: (pd15, 15, [2, 12, 15]), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 12, 14, 15]), + PE1: (pe1, 1, [12, 14, 15]), + PE2: (pe2, 2, [0, 2, 3, 9, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 3, 9, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 6, 9, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 6, 9, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 3, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 12, 13, 15]), + PE9: (pe9, 9, [1, 6, 10, 12, 13, 15]), + PE10: (pe10, 10, [1, 9, 10, 12, 13, 15]), + PE11: (pe11, 11, [1, 9, 10, 12, 15]), + PE12: (pe12, 12, [1, 5, 9, 10, 12, 15]), + PE13: (pe13, 13, [1, 5, 9, 10, 12, 15]), + PE14: (pe14, 14, [1, 3, 5, 10, 12, 15]), + PE15: (pe15, 15, [3, 5, 10, 12, 15]), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 12, 15]), + PF1: (pf1, 1, [4, 12, 15]), + PF2: (pf2, 2, [4, 12, 15]), + PF3: (pf3, 3, [2, 12, 15]), + PF4: (pf4, 4, [2, 12, 15]), + PF5: (pf5, 5, [2, 12, 15]), + PF6: (pf6, 6, [1, 2, 10, 13, 15]), + PF7: (pf7, 7, [2, 10, 13, 15]), + PF8: (pf8, 8, [2, 10, 13, 15]), + PF9: (pf9, 9, [2, 10, 13, 14, 15]), + PF10: (pf10, 10, [3, 6, 13, 14, 15]), + PF11: (pf11, 11, [3, 15]), + PF12: (pf12, 12, [12, 15]), + PF13: (pf13, 13, [4, 12, 15]), + PF14: (pf14, 14, [4, 9, 12, 15]), + PF15: (pf15, 15, [4, 9, 12, 15]), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [9, 12, 15]), + PG1: (pg1, 1, [9, 12, 15]), + PG2: (pg2, 2, [5, 12, 13, 15]), + PG3: (pg3, 3, [5, 12, 13, 15]), + PG4: (pg4, 4, [5, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 12, 13, 15]), + PG6: (pg6, 6, [3, 4, 8, 11, 15]), + PG7: (pg7, 7, [3, 4, 6, 8, 11, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [6, 7, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 6, 7, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 3, 6, 7, 13, 14, 15]), + PG12: (pg12, 12, [1, 6, 7, 12, 13, 15]), + PG13: (pg13, 13, [4, 7, 12, 15]), + PG14: (pg14, 14, [4, 12, 15]), + PG15: (pg15, 15, [1, 4, 15]), +]); + +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH3: (ph3, 3, [15], super::Input), +]); +/* +#[cfg(feature = "gpio-l55x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ diff --git a/src/gpio/u5.rs b/src/gpio/u5.rs new file mode 100644 index 00000000..f570f3a5 --- /dev/null +++ b/src/gpio/u5.rs @@ -0,0 +1,374 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 6, 7, 8, 10, 12, 13, 14, 15]), + PA1: (pa1, 1, [0, 1, 2, 4, 5, 7, 8, 10, 14, 15]), + PA2: (pa2, 2, [1, 2, 5, 7, 8, 10, 11, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 7, 8, 10, 13, 14, 15]), + PA4: (pa4, 4, [3, 5, 6, 7, 10, 13, 14, 15]), + PA5: (pa5, 5, [0, 1, 2, 3, 4, 5, 7, 14, 15]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 7, 8, 10, 14, 15]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 7, 10, 13, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 5, 7, 10, 12, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 5, 7, 13, 14, 15]), + PA10: (pa10, 10, [0, 1, 2, 3, 5, 7, 10, 13, 14, 15]), + PA11: (pa11, 11, [1, 2, 5, 7, 9, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 9, 15]), + PA13: (pa13, 13, [0, 1, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 10, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 4, 5, 7, 10, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 3, 4, 6, 7, 8, 10, 14, 15]), + PB2: (pb2, 2, [1, 3, 4, 5, 6, 8, 10, 11, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 12, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 5, 6, 7, 9, 10, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15]), + PB8: (pb8, 8, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 5, 7, 8, 10, 12, 15]), + PB12: (pb12, 12, [1, 2, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PB13: (pb13, 13, [1, 2, 4, 5, 6, 7, 8, 9, 13, 14, 15]), + PB14: (pb14, 14, [1, 2, 3, 4, 5, 6, 7, 9, 12, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 5, 6, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 3, 4, 5, 6, 7, 8, 12, 13, 14, 15]), + PC1: (pc1, 1, [0, 1, 3, 4, 6, 7, 8, 10, 12, 13, 15]), + PC2: (pc2, 2, [1, 5, 6, 7, 9, 10, 15]), + PC3: (pc3, 3, [1, 2, 3, 5, 7, 9, 10, 13, 14, 15]), + PC4: (pc4, 4, [2, 7, 10, 15]), + PC5: (pc5, 5, [1, 3, 4, 7, 15]), + PC6: (pc6, 6, [0, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC7: (pc7, 7, [0, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + PC8: (pc8, 8, [0, 2, 3, 7, 9, 10, 12, 14, 15]), + PC9: (pc9, 9, [0, 1, 2, 3, 4, 7, 9, 12, 14, 15]), + PC10: (pc10, 10, [0, 2, 3, 6, 7, 8, 9, 10, 12, 13, 15]), + PC11: (pc11, 11, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC12: (pc12, 12, [0, 6, 7, 8, 9, 10, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [2, 3, 4, 5, 8, 9, 12, 15]), + PD1: (pd1, 1, [2, 4, 5, 8, 9, 12, 15]), + PD2: (pd2, 2, [0, 2, 4, 7, 8, 9, 10, 12, 13, 15]), + PD3: (pd3, 3, [2, 3, 4, 5, 6, 7, 8, 10, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 10, 12, 15]), + PD5: (pd5, 5, [5, 7, 10, 12, 15]), + PD6: (pd6, 6, [3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 10, 11, 12, 13, 15]), + PD8: (pd8, 8, [7, 8, 10, 12, 15]), + PD9: (pd9, 9, [2, 7, 8, 10, 12, 13, 14, 15]), + PD10: (pd10, 10, [2, 4, 7, 8, 9, 12, 13, 14, 15]), + PD11: (pd11, 11, [4, 7, 8, 9, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 4, 7, 8, 9, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 4, 7, 8, 9, 12, 13, 14, 15]), + PD14: (pd14, 14, [2, 7, 8, 12, 14, 15]), + PD15: (pd15, 15, [2, 7, 8, 12, 14, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 7, 8, 10, 12, 14, 15]), + PE1: (pe1, 1, [7, 8, 10, 12, 14, 15]), + PE2: (pe2, 2, [0, 2, 3, 7, 8, 9, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 3, 7, 8, 9, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 6, 7, 8, 9, 10, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 6, 8, 9, 10, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 3, 8, 10, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 8, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 8, 12, 13, 15]), + PE9: (pe9, 9, [1, 3, 6, 8, 10, 12, 13, 15]), + PE10: (pe10, 10, [1, 3, 6, 8, 9, 10, 12, 13, 15]), + PE11: (pe11, 11, [1, 5, 6, 8, 9, 10, 12, 15]), + PE12: (pe12, 12, [1, 5, 6, 8, 9, 10, 12, 15]), + PE13: (pe13, 13, [1, 5, 6, 8, 9, 10, 12, 15]), + PE14: (pe14, 14, [1, 2, 5, 8, 10, 12, 15]), + PE15: (pe15, 15, [1, 3, 5, 8, 10, 12, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [2, 4, 5, 7, 12, 15]), + PF1: (pf1, 1, [2, 4, 5, 7, 12, 15]), + PF2: (pf2, 2, [2, 4, 5, 7, 12, 15]), + PF3: (pf3, 3, [2, 3, 5, 6, 7, 8, 12, 15]), + PF4: (pf4, 4, [2, 3, 5, 6, 7, 8, 12, 15]), + PF5: (pf5, 5, [2, 5, 6, 12, 15]), + PF6: (pf6, 6, [1, 2, 4, 5, 10, 13, 15]), + PF7: (pf7, 7, [2, 9, 10, 13, 15]), + PF8: (pf8, 8, [2, 4, 9, 10, 13, 15]), + PF9: (pf9, 9, [2, 4, 10, 13, 14, 15]), + PF10: (pf10, 10, [3, 4, 6, 10, 11, 13, 14, 15]), + PF11: (pf11, 11, [3, 8, 10, 11, 13, 15]), + PF12: (pf12, 12, [5, 8, 12, 13, 15]), + PF13: (pf13, 13, [4, 8, 11, 12, 13, 15]), + PF14: (pf14, 14, [4, 8, 9, 12, 15]), + PF15: (pf15, 15, [4, 8, 9, 12, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [5, 9, 12, 15]), + PG1: (pg1, 1, [5, 9, 12, 15]), + PG2: (pg2, 2, [5, 12, 13, 15]), + PG3: (pg3, 3, [5, 12, 13, 15]), + PG4: (pg4, 4, [5, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 11, 12, 13, 15]), + PG6: (pg6, 6, [3, 4, 5, 7, 8, 11, 15]), + PG7: (pg7, 7, [3, 4, 5, 6, 8, 11, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [5, 6, 7, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 5, 6, 7, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 3, 6, 7, 13, 14, 15]), + PG12: (pg12, 12, [1, 5, 6, 7, 12, 13, 15]), + PG13: (pg13, 13, [4, 6, 7, 8, 12, 15]), + PG14: (pg14, 14, [1, 4, 8, 12, 15]), + PG15: (pg15, 15, [1, 4, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [3, 15]), + PH3: (ph3, 3, [15]), + PH4: (ph4, 4, [2, 4, 5, 10, 15]), + PH5: (ph5, 5, [2, 4, 10, 15]), + PH6: (ph6, 6, [2, 4, 5, 10, 15]), + PH7: (ph7, 7, [4, 5, 10, 15]), + PH8: (ph8, 8, [4, 5, 10, 15]), + PH9: (ph9, 9, [4, 5, 8, 10, 15]), + PH10: (ph10, 10, [2, 5, 8, 10, 15]), + PH11: (ph11, 11, [2, 5, 8, 10, 15]), + PH12: (ph12, 12, [2, 3, 5, 8, 10, 15]), + PH13: (ph13, 13, [3, 8, 9, 15]), + PH14: (ph14, 14, [3, 8, 9, 10, 15]), + PH15: (ph15, 15, [3, 5, 8, 10, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 3, 5, 8, 10, 15]), + PI1: (pi1, 1, [5, 6, 8, 10, 15]), + PI2: (pi2, 2, [3, 5, 6, 8, 10, 15]), + PI3: (pi3, 3, [3, 5, 6, 8, 10, 15]), + PI4: (pi4, 4, [3, 5, 8, 10, 15]), + PI5: (pi5, 5, [3, 5, 10, 15]), + PI6: (pi6, 6, [3, 5, 10, 15]), + PI7: (pi7, 7, [3, 5, 10, 15]), + PI8: (pi8, 8, [8, 15]), + PI9: (pi9, 9, [8, 15]), + PI10: (pi10, 10, [8, 15]), + PI11: (pi11, 11, [8, 15]), + PI12: (pi12, 12, [8, 15]), + PI13: (pi13, 13, [8, 15]), + PI14: (pi14, 14, [8, 15]), + PI15: (pi15, 15, [8, 15]), +]); + +#[cfg(feature = "gpio-u59x")] +gpio!(GPIOJ, gpioj, PJ, 'J', PJn, [ + PJ0: (pj0, 0, [4, 8, 15]), + PJ1: (pj1, 1, [4, 15]), + PJ2: (pj2, 2, [4, 15]), + PJ3: (pj3, 3, [7, 15]), + PJ4: (pj4, 4, [7, 15]), + PJ5: (pj5, 5, [7, 15]), + PJ6: (pj6, 6, [7, 15]), + PJ7: (pj7, 7, [7, 15]), + PJ8: (pj8, 8, [2, 15]), + PJ9: (pj9, 9, [2, 15]), + PJ10: (pj10, 10, [2, 15]), + PJ11: (pj11, 11, [15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 2, 3, 6, 7, 8, 10, 12, 13, 14, 15]), + PA1: (pa1, 1, [0, 1, 2, 4, 5, 7, 8, 10, 14, 15]), + PA2: (pa2, 2, [1, 2, 5, 7, 8, 10, 11, 14, 15]), + PA3: (pa3, 3, [1, 2, 3, 7, 8, 10, 13, 14, 15]), + PA4: (pa4, 4, [3, 5, 6, 7, 10, 13, 14, 15]), + PA5: (pa5, 5, [0, 1, 2, 3, 4, 5, 7, 14, 15]), + PA6: (pa6, 6, [0, 1, 2, 3, 4, 5, 7, 8, 10, 14, 15]), + PA7: (pa7, 7, [0, 1, 2, 3, 4, 5, 7, 10, 13, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 5, 7, 10, 12, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 5, 7, 13, 14, 15]), + PA10: (pa10, 10, [0, 1, 2, 3, 5, 7, 10, 13, 14, 15]), + PA11: (pa11, 11, [1, 2, 5, 7, 9, 10, 15]), + PA12: (pa12, 12, [1, 5, 6, 7, 9, 10, 15]), + PA13: (pa13, 13, [0, 1, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 10, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 3, 5, 6, 7, 8, 13, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [1, 2, 3, 4, 5, 7, 10, 12, 13, 15]), + PB1: (pb1, 1, [1, 2, 3, 4, 6, 7, 8, 10, 14, 15]), + PB2: (pb2, 2, [1, 3, 4, 5, 6, 10, 11, 15]), + PB3: (pb3, 3, [0, 1, 2, 3, 4, 5, 6, 7, 10, 12, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15]), + PB6: (pb6, 6, [1, 2, 3, 4, 5, 6, 7, 9, 10, 13, 14, 15]), + PB7: (pb7, 7, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15]), + PB8: (pb8, 8, [2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PB9: (pb9, 9, [1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15]), + PB10: (pb10, 10, [1, 2, 3, 4, 5, 7, 8, 9, 10, 12, 13, 15]), + PB11: (pb11, 11, [1, 3, 4, 5, 7, 8, 10, 12, 15]), + PB12: (pb12, 12, [1, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15]), + PB13: (pb13, 13, [1, 2, 4, 5, 6, 7, 8, 9, 13, 14, 15]), + PB14: (pb14, 14, [1, 2, 3, 4, 5, 6, 7, 9, 12, 13, 14, 15]), + PB15: (pb15, 15, [0, 1, 2, 3, 5, 6, 11, 12, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 3, 4, 5, 6, 8, 12, 13, 14, 15]), + PC1: (pc1, 1, [0, 1, 3, 4, 6, 8, 10, 12, 13, 15]), + PC2: (pc2, 2, [1, 5, 6, 9, 10, 15]), + PC3: (pc3, 3, [1, 2, 3, 5, 9, 10, 13, 14, 15]), + PC4: (pc4, 4, [7, 10, 15]), + PC5: (pc5, 5, [1, 3, 4, 7, 15]), + PC6: (pc6, 6, [0, 2, 3, 6, 8, 9, 10, 11, 12, 13, 15]), + PC7: (pc7, 7, [0, 2, 3, 6, 8, 9, 10, 11, 12, 13, 14, 15]), + PC8: (pc8, 8, [0, 2, 3, 9, 10, 12, 14, 15]), + PC9: (pc9, 9, [0, 1, 2, 3, 4, 9, 10, 12, 14, 15]), + PC10: (pc10, 10, [0, 2, 3, 6, 7, 8, 9, 10, 12, 13, 15]), + PC11: (pc11, 11, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15]), + PC12: (pc12, 12, [0, 6, 7, 8, 9, 10, 12, 13, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [3, 5, 9, 12, 15]), + PD1: (pd1, 1, [5, 9, 12, 15]), + PD2: (pd2, 2, [0, 2, 7, 8, 9, 10, 12, 13, 15]), + PD3: (pd3, 3, [3, 4, 5, 6, 7, 10, 12, 15]), + PD4: (pd4, 4, [5, 6, 7, 10, 12, 15]), + PD5: (pd5, 5, [5, 7, 10, 12, 15]), + PD6: (pd6, 6, [3, 4, 5, 6, 7, 10, 11, 12, 13, 15]), + PD7: (pd7, 7, [6, 7, 10, 11, 12, 13, 15]), + PD8: (pd8, 8, [7, 10, 12, 15]), + PD9: (pd9, 9, [2, 7, 10, 12, 13, 14, 15]), + PD10: (pd10, 10, [2, 7, 9, 12, 13, 14, 15]), + PD11: (pd11, 11, [4, 7, 9, 12, 13, 14, 15]), + PD12: (pd12, 12, [2, 4, 7, 9, 12, 13, 14, 15]), + PD13: (pd13, 13, [2, 4, 9, 12, 13, 14, 15]), + PD14: (pd14, 14, [2, 12, 14, 15]), + PD15: (pd15, 15, [2, 12, 14, 15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [2, 10, 12, 14, 15]), + PE1: (pe1, 1, [10, 12, 14, 15]), + PE2: (pe2, 2, [0, 2, 3, 9, 12, 13, 15]), + PE3: (pe3, 3, [0, 2, 3, 9, 12, 13, 15]), + PE4: (pe4, 4, [0, 2, 3, 6, 9, 10, 12, 13, 15]), + PE5: (pe5, 5, [0, 2, 3, 6, 9, 10, 12, 13, 15]), + PE6: (pe6, 6, [0, 2, 3, 10, 12, 13, 15]), + PE7: (pe7, 7, [1, 6, 12, 13, 15]), + PE8: (pe8, 8, [1, 6, 12, 13, 15]), + PE9: (pe9, 9, [1, 3, 6, 10, 12, 13, 15]), + PE10: (pe10, 10, [1, 3, 6, 9, 10, 12, 13, 15]), + PE11: (pe11, 11, [1, 5, 6, 9, 10, 12, 15]), + PE12: (pe12, 12, [1, 5, 6, 9, 10, 12, 15]), + PE13: (pe13, 13, [1, 5, 6, 9, 10, 12, 15]), + PE14: (pe14, 14, [1, 2, 5, 10, 12, 15]), + PE15: (pe15, 15, [1, 3, 5, 10, 12, 15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOF, gpiof, PF, 'F', PFn, [ + PF0: (pf0, 0, [4, 5, 12, 15]), + PF1: (pf1, 1, [4, 5, 12, 15]), + PF2: (pf2, 2, [2, 4, 5, 12, 15]), + PF3: (pf3, 3, [2, 5, 12, 15]), + PF4: (pf4, 4, [2, 5, 12, 15]), + PF5: (pf5, 5, [2, 5, 12, 15]), + PF6: (pf6, 6, [1, 2, 4, 5, 10, 13, 15]), + PF7: (pf7, 7, [2, 9, 10, 13, 15]), + PF8: (pf8, 8, [2, 4, 9, 10, 13, 15]), + PF9: (pf9, 9, [2, 4, 10, 13, 14, 15]), + PF10: (pf10, 10, [3, 4, 6, 10, 13, 14, 15]), + PF11: (pf11, 11, [3, 10, 13, 15]), + PF12: (pf12, 12, [5, 12, 13, 15]), + PF13: (pf13, 13, [4, 11, 12, 13, 15]), + PF14: (pf14, 14, [4, 9, 12, 15]), + PF15: (pf15, 15, [4, 9, 12, 15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOG, gpiog, PG, 'G', PGn, [ + PG0: (pg0, 0, [5, 9, 12, 15]), + PG1: (pg1, 1, [5, 9, 12, 15]), + PG2: (pg2, 2, [5, 12, 13, 15]), + PG3: (pg3, 3, [5, 12, 13, 15]), + PG4: (pg4, 4, [5, 12, 13, 15]), + PG5: (pg5, 5, [5, 8, 12, 13, 15]), + PG6: (pg6, 6, [3, 4, 5, 8, 11, 15]), + PG7: (pg7, 7, [3, 4, 5, 6, 8, 11, 12, 13, 15]), + PG8: (pg8, 8, [4, 8, 15]), + PG9: (pg9, 9, [5, 6, 7, 12, 13, 14, 15]), + PG10: (pg10, 10, [1, 5, 6, 7, 12, 13, 14, 15]), + PG11: (pg11, 11, [1, 3, 6, 7, 13, 14, 15]), + PG12: (pg12, 12, [1, 5, 6, 7, 12, 13, 15]), + PG13: (pg13, 13, [4, 6, 7, 12, 15]), + PG14: (pg14, 14, [1, 4, 12, 15]), + PG15: (pg15, 15, [1, 4, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH2: (ph2, 2, [3, 15]), + PH3: (ph3, 3, [15]), + PH4: (ph4, 4, [4, 5, 10, 15]), + PH5: (ph5, 5, [4, 10, 15]), + PH6: (ph6, 6, [4, 5, 10, 15]), + PH7: (ph7, 7, [4, 5, 10, 15]), + PH8: (ph8, 8, [4, 5, 10, 15]), + PH9: (ph9, 9, [4, 5, 10, 15]), + PH10: (ph10, 10, [2, 5, 10, 15]), + PH11: (ph11, 11, [2, 5, 10, 15]), + PH12: (ph12, 12, [2, 3, 5, 10, 15]), + PH13: (ph13, 13, [3, 9, 15]), + PH14: (ph14, 14, [3, 9, 10, 15]), + PH15: (ph15, 15, [3, 5, 10, 15]), +]); + +#[cfg(feature = "gpio-u5x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI0: (pi0, 0, [2, 3, 5, 10, 15]), + PI1: (pi1, 1, [5, 6, 10, 15]), + PI2: (pi2, 2, [3, 5, 6, 10, 15]), + PI3: (pi3, 3, [3, 5, 6, 10, 15]), + PI4: (pi4, 4, [3, 5, 10, 15]), + PI5: (pi5, 5, [3, 5, 10, 15]), + PI6: (pi6, 6, [3, 5, 10, 15]), + PI7: (pi7, 7, [3, 5, 10, 15]), + PI8: (pi8, 8, []), +]); diff --git a/src/gpio/wb.rs b/src/gpio/wb.rs new file mode 100644 index 00000000..feaf82ea --- /dev/null +++ b/src/gpio/wb.rs @@ -0,0 +1,329 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-wb35x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 12, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 15]), + PA2: (pa2, 2, [0, 1, 8, 15]), + PA3: (pa3, 3, [1, 8, 15]), + PA4: (pa4, 4, [5, 14, 15]), + PA5: (pa5, 5, [1, 2, 4, 5, 14, 15]), + PA6: (pa6, 6, [1, 5, 8, 15]), + PA7: (pa7, 7, [1, 5, 15]), + PA8: (pa8, 8, [0, 1, 7, 14, 15]), + PA9: (pa9, 9, [1, 4, 7, 15]), + PA10: (pa10, 10, [1, 4, 7, 9, 15]), + PA11: (pa11, 11, [1, 2, 5, 7, 15]), + PA12: (pa12, 12, [1, 5, 7, 8, 15]), + PA13: (pa13, 13, [0, 5, 9, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 5, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 5, 6, 9, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-wb35x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [6, 12, 15]), + PB1: (pb1, 1, [8, 14, 15]), + PB2: (pb2, 2, [0, 1, 5, 15]), + PB3: (pb3, 3, [0, 1, 5, 7, 15], super::Debugger), + PB4: (pb4, 4, [0, 5, 7, 9, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 5, 7, 8, 9, 15]), + PB6: (pb6, 6, [0, 1, 4, 5, 7, 9, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 9, 12, 15]), + PB8: (pb8, 8, [1, 4, 9, 15]), + PB9: (pb9, 9, [1, 4, 9, 15]), + PB10: (pb10, 10, [9, 15]), + PB12: (pb12, 12, [1, 9, 15]), + PB13: (pb13, 13, [1, 9, 15]), + PB14: (pb14, 14, [1, 15]), + PB15: (pb15, 15, [1, 15]), +]); + +#[cfg(feature = "gpio-wb35x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC1: (pc1, 1, [9, 15]), + PC13: (pc13, 13, []), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-wb35x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE4: (pe4, 4, [15]), +]); + +#[cfg(feature = "gpio-wb35x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH3: (ph3, 3, [0, 15]), +]); +/* +#[cfg(feature = "gpio-wb35x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-wb3x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 12, 13, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 15]), + PA2: (pa2, 2, [0, 1, 8, 10, 12, 15]), + PA3: (pa3, 3, [1, 3, 8, 10, 13, 15]), + PA4: (pa4, 4, [5, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 5, 13, 14, 15]), + PA6: (pa6, 6, [5, 8, 10, 12, 14, 15]), + PA7: (pa7, 7, [1, 4, 5, 10, 12, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 7, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 4, 7, 13, 15]), + PA10: (pa10, 10, [1, 3, 4, 7, 10, 13, 14, 15]), + PA11: (pa11, 11, [1, 5, 7, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 8, 10, 15]), + PA13: (pa13, 13, [0, 8, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 5, 6, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-wb3x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [6, 12, 15]), + PB1: (pb1, 1, [8, 14, 15]), + PB2: (pb2, 2, [1, 4, 5, 13, 15]), + PB3: (pb3, 3, [0, 1, 5, 7, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 4, 5, 7, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 5, 7, 8, 12, 13, 14, 15]), + PB6: (pb6, 6, [0, 1, 4, 7, 13, 14, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 14, 15]), + PB8: (pb8, 8, [1, 3, 4, 10, 13, 14, 15]), + PB9: (pb9, 9, [1, 3, 4, 8, 10, 13, 14, 15]), +]); + +#[cfg(feature = "gpio-wb3x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC13: (pc13, 13, []), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-wb3x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE4: (pe4, 4, [15]), +]); + +#[cfg(feature = "gpio-wb3x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH3: (ph3, 3, [0, 15]), +]); +/* +#[cfg(feature = "gpio-wb3x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 12, 13, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 11, 15]), + PA2: (pa2, 2, [0, 1, 8, 10, 11, 12, 15]), + PA3: (pa3, 3, [1, 3, 8, 10, 11, 13, 15]), + PA4: (pa4, 4, [5, 11, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 5, 13, 14, 15]), + PA6: (pa6, 6, [5, 8, 10, 11, 12, 14, 15]), + PA7: (pa7, 7, [1, 4, 5, 10, 11, 12, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 7, 11, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 4, 5, 7, 11, 13, 15]), + PA10: (pa10, 10, [1, 3, 4, 7, 10, 11, 13, 14, 15]), + PA11: (pa11, 11, [1, 5, 7, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 8, 10, 15]), + PA13: (pa13, 13, [0, 8, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 11, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 5, 6, 9, 11, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [6, 12, 15]), + PB1: (pb1, 1, [8, 14, 15]), + PB2: (pb2, 2, [1, 4, 5, 11, 13, 15]), + PB3: (pb3, 3, [0, 1, 5, 7, 11, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 4, 5, 7, 9, 11, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [0, 1, 4, 7, 9, 11, 13, 14, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 9, 11, 14, 15]), + PB8: (pb8, 8, [1, 3, 4, 10, 11, 13, 14, 15]), + PB9: (pb9, 9, [1, 3, 4, 5, 8, 9, 10, 11, 13, 14, 15]), + PB10: (pb10, 10, [1, 4, 5, 8, 9, 10, 11, 12, 13, 15]), + PB11: (pb11, 11, [1, 4, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [3, 4, 5, 8, 9, 11, 13, 15]), + PB13: (pb13, 13, [1, 4, 5, 8, 9, 11, 13, 15]), + PB14: (pb14, 14, [1, 4, 5, 9, 11, 13, 15]), + PB15: (pb15, 15, [0, 1, 5, 9, 11, 13, 15]), +]); + +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 8, 11, 14, 15]), + PC1: (pc1, 1, [1, 3, 4, 8, 11, 15]), + PC2: (pc2, 2, [1, 5, 11, 15]), + PC3: (pc3, 3, [1, 3, 5, 11, 13, 14, 15]), + PC4: (pc4, 4, [11, 15]), + PC5: (pc5, 5, [3, 11, 15]), + PC6: (pc6, 6, [9, 11, 15]), + PC7: (pc7, 7, [9, 11, 15]), + PC8: (pc8, 8, [9, 11, 15]), + PC9: (pc9, 9, [3, 9, 10, 11, 13, 15]), + PC10: (pc10, 10, [0, 9, 11, 15]), + PC11: (pc11, 11, [9, 11, 15]), + PC12: (pc12, 12, [0, 6, 9, 11, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 15]), + PD1: (pd1, 1, [5, 15]), + PD2: (pd2, 2, [0, 9, 11, 15]), + PD3: (pd3, 3, [3, 5, 10, 15]), + PD4: (pd4, 4, [5, 9, 10, 15]), + PD5: (pd5, 5, [9, 10, 13, 15]), + PD6: (pd6, 6, [3, 9, 10, 13, 15]), + PD7: (pd7, 7, [9, 10, 11, 15]), + PD8: (pd8, 8, [2, 11, 15]), + PD9: (pd9, 9, [0, 11, 15]), + PD10: (pd10, 10, [0, 9, 11, 15]), + PD11: (pd11, 11, [9, 11, 14, 15]), + PD12: (pd12, 12, [9, 11, 14, 15]), + PD13: (pd13, 13, [9, 11, 14, 15]), + PD14: (pd14, 14, [1, 11, 15]), + PD15: (pd15, 15, [1, 11, 15]), +]); + +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 9, 11, 14, 15]), + PE1: (pe1, 1, [9, 11, 14, 15]), + PE2: (pe2, 2, [0, 3, 9, 11, 13, 15]), + PE3: (pe3, 3, [15]), + PE4: (pe4, 4, [15]), +]); + +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH3: (ph3, 3, [0, 15]), +]); +/* +#[cfg(feature = "gpio-wb55x")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ + +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 12, 13, 14, 15]), + PA1: (pa1, 1, [1, 4, 5, 11, 15]), + PA2: (pa2, 2, [0, 1, 8, 10, 11, 12, 15]), + PA3: (pa3, 3, [1, 3, 8, 10, 11, 13, 15]), + PA4: (pa4, 4, [5, 11, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 5, 13, 14, 15]), + PA6: (pa6, 6, [5, 8, 10, 11, 12, 14, 15]), + PA7: (pa7, 7, [1, 4, 5, 10, 11, 12, 14, 15]), + PA8: (pa8, 8, [0, 1, 3, 7, 11, 13, 14, 15]), + PA9: (pa9, 9, [1, 3, 4, 5, 7, 11, 13, 15]), + PA10: (pa10, 10, [1, 3, 4, 7, 10, 11, 13, 14, 15]), + PA11: (pa11, 11, [1, 5, 7, 10, 12, 15]), + PA12: (pa12, 12, [1, 5, 7, 8, 10, 15]), + PA13: (pa13, 13, [0, 8, 10, 13, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 11, 13, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 5, 9, 11, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [6, 12, 15]), + PB1: (pb1, 1, [8, 14, 15]), + PB2: (pb2, 2, [1, 4, 5, 11, 13, 15]), + PB3: (pb3, 3, [0, 1, 5, 7, 11, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 4, 5, 7, 9, 11, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 5, 7, 8, 9, 11, 12, 13, 14, 15]), + PB6: (pb6, 6, [0, 1, 4, 7, 9, 11, 13, 14, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 9, 11, 14, 15]), + PB8: (pb8, 8, [1, 3, 4, 10, 11, 13, 14, 15]), + PB9: (pb9, 9, [1, 3, 4, 5, 8, 9, 10, 11, 13, 14, 15]), + PB10: (pb10, 10, [1, 4, 5, 8, 9, 10, 11, 12, 13, 15]), + PB11: (pb11, 11, [1, 4, 8, 10, 11, 12, 15]), + PB12: (pb12, 12, [3, 4, 5, 8, 9, 11, 13, 15]), + PB13: (pb13, 13, [1, 4, 5, 8, 9, 11, 13, 15]), + PB14: (pb14, 14, [1, 4, 5, 9, 11, 13, 15]), + PB15: (pb15, 15, [0, 1, 5, 9, 11, 13, 15]), +]); + +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 8, 11, 14, 15]), + PC1: (pc1, 1, [1, 3, 4, 8, 11, 15]), + PC2: (pc2, 2, [1, 5, 11, 15]), + PC3: (pc3, 3, [1, 3, 5, 11, 13, 14, 15]), + PC4: (pc4, 4, [11, 15]), + PC5: (pc5, 5, [3, 11, 15]), + PC6: (pc6, 6, [9, 11, 15]), + PC7: (pc7, 7, [9, 11, 15]), + PC8: (pc8, 8, [9, 11, 15]), + PC9: (pc9, 9, [3, 9, 10, 11, 13, 15]), + PC10: (pc10, 10, [0, 9, 11, 15]), + PC11: (pc11, 11, [9, 11, 15]), + PC12: (pc12, 12, [0, 6, 9, 11, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [6, 15]), + PC15: (pc15, 15, [6, 15]), +]); + +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOD, gpiod, PD, 'D', PDn, [ + PD0: (pd0, 0, [5, 15]), + PD1: (pd1, 1, [5, 15]), + PD2: (pd2, 2, [0, 9, 11, 15]), + PD3: (pd3, 3, [3, 5, 10, 15]), + PD4: (pd4, 4, [5, 9, 10, 15]), + PD5: (pd5, 5, [9, 10, 13, 15]), + PD6: (pd6, 6, [3, 9, 10, 13, 15]), + PD7: (pd7, 7, [9, 10, 11, 15]), + PD8: (pd8, 8, [2, 11, 15]), + PD9: (pd9, 9, [0, 11, 15]), + PD10: (pd10, 10, [0, 9, 11, 15]), + PD11: (pd11, 11, [9, 11, 14, 15]), + PD12: (pd12, 12, [9, 11, 14, 15]), + PD13: (pd13, 13, [9, 11, 14, 15]), + PD14: (pd14, 14, [1, 11, 15]), + PD15: (pd15, 15, [1, 11, 15]), +]); + +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOE, gpioe, PE, 'E', PEn, [ + PE0: (pe0, 0, [1, 9, 11, 14, 15]), + PE1: (pe1, 1, [9, 11, 14, 15]), + PE2: (pe2, 2, [0, 3, 9, 11, 13, 15]), + PE3: (pe3, 3, [15]), + PE4: (pe4, 4, [15]), +]); + +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH0: (ph0, 0, [15]), + PH1: (ph1, 1, [15]), + PH3: (ph3, 3, [0, 15]), +]); +/* +#[cfg(feature = "gpio-wb5mx")] +gpio!(GPIOI, gpioi, PI, 'I', PIn, [ + PI8: (pi8, 8, []), +]); +*/ diff --git a/src/gpio/wl.rs b/src/gpio/wl.rs new file mode 100644 index 00000000..9642da54 --- /dev/null +++ b/src/gpio/wl.rs @@ -0,0 +1,64 @@ +// auto-generated using codegen +// STM32CubeMX DB release: DB.6.0.50 +pub use super::*; + +pub use super::Analog as DefaultMode; + +#[cfg(feature = "gpio-wl")] +gpio!(GPIOA, gpioa, PA, 'A', PAn, [ + PA0: (pa0, 0, [1, 4, 5, 7, 12, 13, 14, 15]), + PA1: (pa1, 1, [1, 3, 4, 5, 7, 8, 13, 15]), + PA2: (pa2, 2, [0, 1, 7, 8, 12, 13, 15]), + PA3: (pa3, 3, [1, 5, 7, 8, 15]), + PA4: (pa4, 4, [1, 5, 7, 13, 14, 15]), + PA5: (pa5, 5, [1, 2, 3, 5, 13, 14, 15]), + PA6: (pa6, 6, [4, 5, 8, 12, 13, 14, 15]), + PA7: (pa7, 7, [1, 4, 5, 12, 13, 14, 15]), + PA8: (pa8, 8, [0, 1, 5, 7, 14, 15]), + PA9: (pa9, 9, [1, 3, 4, 5, 7, 15]), + PA10: (pa10, 10, [0, 1, 4, 5, 7, 13, 14, 15]), + PA11: (pa11, 11, [1, 3, 4, 5, 7, 12, 13, 15]), + PA12: (pa12, 12, [1, 3, 4, 5, 6, 7, 15]), + PA13: (pa13, 13, [0, 4, 8, 15], super::Debugger), + PA14: (pa14, 14, [0, 1, 4, 15], super::Debugger), + PA15: (pa15, 15, [0, 1, 2, 4, 5, 15], super::Debugger), +]); + +#[cfg(feature = "gpio-wl")] +gpio!(GPIOB, gpiob, PB, 'B', PBn, [ + PB0: (pb0, 0, [12, 15]), + PB1: (pb1, 1, [8, 14, 15]), + PB2: (pb2, 2, [1, 4, 5, 13, 15]), + PB3: (pb3, 3, [0, 1, 5, 6, 7, 13, 15], super::Debugger), + PB4: (pb4, 4, [0, 4, 5, 7, 13, 14, 15], super::Debugger), + PB5: (pb5, 5, [1, 4, 5, 6, 7, 12, 14, 15]), + PB6: (pb6, 6, [1, 4, 7, 14, 15]), + PB7: (pb7, 7, [1, 3, 4, 7, 14, 15]), + PB8: (pb8, 8, [1, 4, 6, 14, 15]), + PB9: (pb9, 9, [1, 4, 5, 8, 14, 15]), + PB10: (pb10, 10, [1, 4, 5, 8, 12, 15]), + PB11: (pb11, 11, [1, 4, 8, 12, 15]), + PB12: (pb12, 12, [3, 4, 5, 8, 15]), + PB13: (pb13, 13, [1, 4, 5, 8, 15]), + PB14: (pb14, 14, [1, 3, 4, 5, 15]), + PB15: (pb15, 15, [1, 4, 5, 15]), +]); + +#[cfg(feature = "gpio-wl")] +gpio!(GPIOC, gpioc, PC, 'C', PCn, [ + PC0: (pc0, 0, [1, 4, 8, 14, 15]), + PC1: (pc1, 1, [1, 3, 4, 8, 15]), + PC2: (pc2, 2, [1, 5, 15]), + PC3: (pc3, 3, [1, 5, 14, 15]), + PC4: (pc4, 4, [15]), + PC5: (pc5, 5, [15]), + PC6: (pc6, 6, [5, 15]), + PC13: (pc13, 13, [15]), + PC14: (pc14, 14, [15]), + PC15: (pc15, 15, [15]), +]); + +#[cfg(feature = "gpio-wl")] +gpio!(GPIOH, gpioh, PH, 'H', PHn, [ + PH3: (ph3, 3, [15]), +]); diff --git a/src/i2c.rs b/src/i2c.rs index c5eb6309..6bd1e090 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -15,6 +15,7 @@ mod hal_1; pub use common::{Address, Error, NoAcknowledgeSource}; use common::{Hal02Operation, Hal1Operation}; +#[cfg(feature = "dma")] pub mod dma; #[derive(Debug, Eq, PartialEq)] @@ -82,6 +83,16 @@ pub trait Instance: + Reset + gpio::alt::I2cCommon { + #[doc(hidden)] + #[inline(always)] + fn tx_peri_address() -> u32 { + unsafe { (*Self::ptr()).dr().as_ptr() as u32 } + } + #[doc(hidden)] + #[inline(always)] + fn rx_peri_address() -> u32 { + unsafe { (*Self::ptr()).dr().as_ptr() as u32 } + } } // Implemented by all I2C instances @@ -101,10 +112,16 @@ macro_rules! i2c { } i2c! { pac::I2C1: I2c1 } +#[cfg(feature = "i2c2")] i2c! { pac::I2C2: I2c2 } - #[cfg(feature = "i2c3")] i2c! { pac::I2C3: I2c3 } +#[cfg(feature = "i2c4")] +i2c! { pac::I2C4: I2c4 } +#[cfg(feature = "i2c5")] +i2c! { pac::I2C5: I2c5 } +#[cfg(feature = "i2c6")] +i2c! { pac::I2C6: I2c6 } pub trait I2cExt: Sized + Instance { fn i2c( @@ -658,3 +675,30 @@ macro_rules! transaction_impl { }; } use transaction_impl; + +impl embedded_hal_02::blocking::i2c::WriteIter for I2c { + type Error = Error; + + fn write(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> + where + B: IntoIterator, + { + self.write_iter(addr, bytes) + } +} + +impl embedded_hal_02::blocking::i2c::WriteIterRead for I2c { + type Error = Error; + + fn write_iter_read( + &mut self, + addr: u8, + bytes: B, + buffer: &mut [u8], + ) -> Result<(), Self::Error> + where + B: IntoIterator, + { + self.write_iter_read(addr, bytes, buffer) + } +} diff --git a/src/i2c/dma.rs b/src/i2c/dma.rs index 16918b5e..c4e97292 100644 --- a/src/i2c/dma.rs +++ b/src/i2c/dma.rs @@ -902,7 +902,7 @@ pub struct Rx { unsafe impl PeriAddress for Rx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*I2C::ptr()).dr().as_ptr() as u32 } + I2C::rx_peri_address() } type MemSize = u8; @@ -911,7 +911,7 @@ unsafe impl PeriAddress for Rx { unsafe impl PeriAddress for Tx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*I2C::ptr()).dr().as_ptr() as u32 } + I2C::tx_peri_address() } type MemSize = u8; diff --git a/src/i2c/hal_02.rs b/src/i2c/hal_02.rs index 0204394b..f493abc0 100644 --- a/src/i2c/hal_02.rs +++ b/src/i2c/hal_02.rs @@ -1,8 +1,6 @@ mod blocking { use super::super::{Error, I2c, Instance}; - use embedded_hal_02::blocking::i2c::{ - Operation, Read, Transactional, Write, WriteIter, WriteIterRead, WriteRead, - }; + use embedded_hal_02::blocking::i2c::{Operation, Read, Transactional, Write, WriteRead}; impl WriteRead for I2c { type Error = Error; @@ -17,22 +15,6 @@ mod blocking { } } - impl WriteIterRead for I2c { - type Error = Error; - - fn write_iter_read( - &mut self, - addr: u8, - bytes: B, - buffer: &mut [u8], - ) -> Result<(), Self::Error> - where - B: IntoIterator, - { - self.write_iter_read(addr, bytes, buffer) - } - } - impl Write for I2c { type Error = Error; @@ -41,17 +23,6 @@ mod blocking { } } - impl WriteIter for I2c { - type Error = Error; - - fn write(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> - where - B: IntoIterator, - { - self.write_iter(addr, bytes) - } - } - impl Read for I2c { type Error = Error; diff --git a/src/lib.rs b/src/lib.rs index df1031ef..3548e4d2 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -13,122 +13,241 @@ pub use embedded_hal_02 as hal_02; pub use nb; pub use nb::block; -#[cfg(feature = "stm32f401")] +#[cfg(feature = "svd-f0x0")] +pub use stm32f0::stm32f0x0 as pac; + +#[cfg(feature = "svd-f0x1")] +pub use stm32f0::stm32f0x1 as pac; + +#[cfg(feature = "svd-f0x2")] +pub use stm32f0::stm32f0x2 as pac; + +#[cfg(feature = "svd-f215")] +pub use stm32f2::stm32f215 as pac; + +#[cfg(feature = "svd-f217")] +pub use stm32f2::stm32f217 as pac; + +#[cfg(feature = "svd-f301")] +pub use stm32f3::stm32f301 as pac; + +#[cfg(feature = "svd-f302")] +pub use stm32f3::stm32f302 as pac; + +#[cfg(feature = "svd-f303")] +pub use stm32f3::stm32f303 as pac; + +#[cfg(feature = "svd-f373")] +pub use stm32f3::stm32f373 as pac; + +#[cfg(feature = "svd-f3x4")] +pub use stm32f3::stm32f3x4 as pac; + +#[cfg(feature = "svd-f401")] /// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f401 peripherals. pub use stm32f4::stm32f401 as pac; -#[cfg(feature = "stm32f405")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f405 peripherals. +#[cfg(feature = "svd-f405")] +/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f405/f415 peripherals. pub use stm32f4::stm32f405 as pac; -#[cfg(feature = "stm32f407")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f407 peripherals. +#[cfg(feature = "svd-f407")] +/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f407/f417 peripherals. pub use stm32f4::stm32f407 as pac; -#[cfg(feature = "stm32f410")] +#[cfg(feature = "svd-f410")] /// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f410 peripherals. pub use stm32f4::stm32f410 as pac; -#[cfg(feature = "stm32f411")] +#[cfg(feature = "svd-f411")] /// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f411 peripherals. pub use stm32f4::stm32f411 as pac; -#[cfg(feature = "stm32f412")] +#[cfg(feature = "svd-f412")] /// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f412 peripherals. pub use stm32f4::stm32f412 as pac; -#[cfg(feature = "stm32f413")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f413 peripherals. +#[cfg(feature = "svd-f413")] +/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f413/f423 peripherals. pub use stm32f4::stm32f413 as pac; -#[cfg(feature = "stm32f415")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f405 peripherals. -pub use stm32f4::stm32f405 as pac; - -#[cfg(feature = "stm32f417")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f407 peripherals. -pub use stm32f4::stm32f407 as pac; - -#[cfg(feature = "stm32f423")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f413 peripherals. -pub use stm32f4::stm32f413 as pac; - -#[cfg(feature = "stm32f427")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f427 peripherals. -pub use stm32f4::stm32f427 as pac; - -#[cfg(feature = "stm32f429")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f429 peripherals. -pub use stm32f4::stm32f429 as pac; - -#[cfg(feature = "stm32f437")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f427 peripherals. +#[cfg(feature = "svd-f427")] +/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f427/f437 peripherals. pub use stm32f4::stm32f427 as pac; -#[cfg(feature = "stm32f439")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f429 peripherals. +#[cfg(feature = "svd-f429")] +/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f429/f439 peripherals. pub use stm32f4::stm32f429 as pac; -#[cfg(feature = "stm32f446")] +#[cfg(feature = "svd-f446")] /// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f446 peripherals. pub use stm32f4::stm32f446 as pac; -#[cfg(feature = "stm32f469")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f469 peripherals. +#[cfg(feature = "svd-f469")] +/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f469/f479 peripherals. pub use stm32f4::stm32f469 as pac; -#[cfg(feature = "stm32f479")] -/// Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for the stm32f469 peripherals. -pub use stm32f4::stm32f469 as pac; +#[cfg(feature = "svd-f7x2")] +pub use stm32f7::stm32f7x2 as pac; + +#[cfg(feature = "svd-f7x3")] +pub use stm32f7::stm32f7x3 as pac; + +#[cfg(feature = "svd-f730")] +pub use stm32f7::stm32f730 as pac; + +#[cfg(feature = "svd-f745")] +pub use stm32f7::stm32f745 as pac; + +#[cfg(feature = "svd-f7x6")] +pub use stm32f7::stm32f7x6 as pac; + +#[cfg(feature = "svd-f765")] +pub use stm32f7::stm32f765 as pac; + +#[cfg(feature = "svd-f7x7")] +pub use stm32f7::stm32f7x7 as pac; + +#[cfg(feature = "svd-f7x9")] +pub use stm32f7::stm32f7x9 as pac; + +#[cfg(feature = "svd-g431")] +pub use stm32g4::stm32g431 as pac; + +#[cfg(feature = "svd-g441")] +pub use stm32g4::stm32g441 as pac; + +#[cfg(feature = "svd-g471")] +pub use stm32g4::stm32g471 as pac; + +#[cfg(feature = "svd-g473")] +pub use stm32g4::stm32g473 as pac; + +#[cfg(feature = "svd-g474")] +pub use stm32g4::stm32g474 as pac; + +#[cfg(feature = "svd-g483")] +pub use stm32g4::stm32g483 as pac; + +#[cfg(feature = "svd-g484")] +pub use stm32g4::stm32g484 as pac; + +#[cfg(feature = "svd-g491")] +pub use stm32g4::stm32g491 as pac; + +#[cfg(feature = "svd-g4a1")] +pub use stm32g4::stm32g4a1 as pac; + +#[cfg(feature = "svd-l4x1")] +pub use stm32l4::stm32l4x1 as pac; + +#[cfg(feature = "svd-l412")] +pub use stm32l4::stm32l412 as pac; + +#[cfg(feature = "svd-l4x2")] +pub use stm32l4::stm32l4x2 as pac; + +#[cfg(feature = "svd-l4x3")] +pub use stm32l4::stm32l4x3 as pac; + +#[cfg(feature = "svd-l4x5")] +pub use stm32l4::stm32l4x5 as pac; + +#[cfg(feature = "svd-l4x6")] +pub use stm32l4::stm32l4x6 as pac; + +#[cfg(feature = "svd-l4r9")] +pub use stm32l4::stm32l4r9 as pac; // Enable use of interrupt macro pub use crate::pac::interrupt; +#[cfg(any(feature = "f4", feature = "f7"))] +pub mod adc; +#[cfg(feature = "l4")] +#[path = "adc/l4.rs"] pub mod adc; +#[cfg(feature = "bb")] pub mod bb; #[cfg(all(feature = "can", any(feature = "can1", feature = "can2")))] pub mod can; +#[cfg(feature = "l4")] +#[path = "crc_l4.rs"] +pub mod crc; +#[cfg(feature = "f4")] pub mod crc32; #[cfg(feature = "dac")] pub mod dac; #[cfg(feature = "fmpi2c1")] pub mod fmpi2c; pub mod gpio; +#[cfg(feature = "i2c_v1")] +pub mod i2c; +#[cfg(feature = "i2c_v2")] +#[path = "fmpi2c.rs"] pub mod i2c; +#[cfg(feature = "f4")] pub mod i2s; #[cfg(all(feature = "usb_fs", feature = "otg-fs"))] pub mod otg_fs; #[cfg(all(any(feature = "usb_hs", docsrs), feature = "otg-hs"))] pub mod otg_hs; +#[cfg(feature = "f4")] #[cfg(feature = "rng")] pub mod rng; +#[cfg(feature = "dma")] pub mod dma; pub mod dwt; +#[cfg(feature = "f4")] +#[path = "flash/f4.rs"] pub mod flash; +#[cfg(feature = "f7")] +#[path = "flash/f7.rs"] +pub mod flash; +#[cfg(feature = "l4")] +#[path = "flash/l4.rs"] +pub mod flash; +#[cfg(any(feature = "fmc", feature = "fsmc"))] +#[cfg(feature = "f7")] +pub mod fmc; #[cfg(all(feature = "fsmc_lcd", any(feature = "fmc", feature = "fsmc")))] pub mod fsmc_lcd; +#[cfg(feature = "l4")] +pub mod lptimer; #[cfg(all(feature = "dma2d", feature = "ltdc"))] pub mod ltdc; pub mod prelude; +#[cfg(feature = "l4")] +#[path = "pwr/l4.rs"] +pub mod pwr; pub mod qei; #[cfg(feature = "quadspi")] pub mod qspi; pub mod rcc; +#[cfg(feature = "f4")] pub mod rtc; #[cfg(feature = "sai")] pub mod sai; #[cfg(all(feature = "sdio-host", feature = "sdio"))] pub mod sdio; pub mod serial; +#[cfg(not(feature = "f3"))] pub mod signature; +#[cfg(feature = "f3")] +pub mod signature_f3; pub mod spi; pub mod syscfg; pub mod time; pub mod timer; +#[cfg(feature = "l4")] +pub mod tsc; #[cfg(feature = "uart4")] pub mod uart; +#[cfg(feature = "usb")] +#[cfg(any(feature = "svd-l412", feature = "svd-l4x2", feature = "svd-l4x3",))] +pub mod usb; pub mod watchdog; mod sealed { @@ -222,3 +341,8 @@ pub trait Steal { /// no stolen instances are passed to such software. unsafe fn steal() -> Self; } + +#[allow(unused)] +use assert; +#[allow(unused)] +use unreachable; diff --git a/src/lptimer.rs b/src/lptimer.rs new file mode 100644 index 00000000..ff0d6a9e --- /dev/null +++ b/src/lptimer.rs @@ -0,0 +1,316 @@ +//! Low power timers +use crate::rcc::{Clocks, Enable, RccBus, Reset, CCIPR}; + +use crate::pac::{LPTIM1, LPTIM2, RCC}; + +/// Clock sources available for timers +pub enum ClockSource { + /// Use PCLK as clock source + PCLK = 0b00, + /// Use LSI as clock source + LSI = 0b01, + /// Use HSI16 as clock source + HSI16 = 0b10, + /// Use LSE as clock source + LSE = 0b11, +} + +/// The prescaler value to use for a timer +/// +/// Allow missing docs because the type is self explanatory +#[allow(missing_docs)] +pub enum PreScaler { + U1 = 0b000, + U2 = 0b001, + U4 = 0b010, + U8 = 0b011, + U16 = 0b100, + U32 = 0b101, + U64 = 0b110, + U128 = 0b111, +} + +/// Count modes that are available. +/// +/// All ClockSources currently supported require the Internal count mode +#[derive(PartialEq)] +pub enum CountMode { + /// Use an internal clock source (which also includes LSE) + Internal, + // External, +} + +/// All currently supported interrupt events +pub enum Event { + /// Occurs when the compare value is the same as the counter value + CompareMatch, + /// Occurs when the arr value is the same as the counter value. + /// When this event occurs, the counter value is set to 0 (by hardware) + AutoReloadMatch, +} + +/// Configuration of a low power timer +pub struct LowPowerTimerConfig { + clock_source: ClockSource, + prescaler: PreScaler, + count_mode: CountMode, + compare_value: u16, + arr_value: u16, +} + +impl Default for LowPowerTimerConfig { + fn default() -> Self { + Self { + clock_source: ClockSource::LSI, + prescaler: PreScaler::U1, + count_mode: CountMode::Internal, + compare_value: 0x0, + arr_value: 0xFFFF, + } + } +} + +impl LowPowerTimerConfig { + /// Select which clock source should be used + pub fn clock_source(mut self, clock_source: ClockSource) -> Self { + self.clock_source = clock_source; + self + } + + /// Select which prescaler value should be used + pub fn prescaler(mut self, prescaler: PreScaler) -> Self { + self.prescaler = prescaler; + self + } + + /// Select the count mode that should be used + pub fn count_mode(mut self, count_mode: CountMode) -> Self { + self.count_mode = count_mode; + self + } + + /// Set the value of the compare register + pub fn compare_value(mut self, compare_value: u16) -> Self { + self.compare_value = compare_value; + self + } + + /// Set the value of the auto reload register + pub fn arr_value(mut self, arr_value: u16) -> Self { + self.arr_value = arr_value; + self + } +} + +/// A low power hardware timer +/// +/// Supported things: +/// * Compare match +/// * Auto reload matches +pub struct LowPowerTimer { + lptim: LPTIM, +} + +macro_rules! hal { + ($timer_type: ident, $lptimX: ident, $timXsel: ident) => { + impl LowPowerTimer<$timer_type> { + #[inline(always)] + fn enable(&mut self) { + self.set_enable(true); + } + + #[inline(always)] + fn disable(&mut self) { + self.set_enable(false); + } + + #[inline(always)] + fn set_enable(&mut self, enabled: bool) { + self.lptim.cr.modify(|_, w| w.enable().bit(enabled)); + } + + #[inline(always)] + fn start_continuous_mode(&mut self) { + self.lptim.cr.modify(|_, w| w.cntstrt().set_bit()); + } + + /// Consume the LPTIM and produce a LowPowerTimer that encapsulates + /// said LPTIM. + /// + /// `config` contains details about the desired configuration for the + /// LowPowerTimer + /// + /// # Panics + /// This function panics if the value of ARR is less than or equal to CMP, + /// and if the clock source is HSI16, LSI, or LSE and that clock is not enabled. + pub fn $lptimX( + lptim: $timer_type, + config: LowPowerTimerConfig, + apb1rn: &mut <$timer_type as RccBus>::Bus, + ccipr: &mut CCIPR, + clocks: Clocks, + ) -> Self { + let LowPowerTimerConfig { + clock_source, + count_mode, + prescaler, + compare_value, + arr_value, + } = config; + + // ARR value must be strictly greater than CMP value + assert!(arr_value > compare_value); + + // The used clock source must actually be enabled + // PCLK is always on if a `Clocks` eixsts. + match clock_source { + ClockSource::LSE => assert!(clocks.lse()), + ClockSource::LSI => assert!(clocks.lsi()), + // Check if HSI16 is enabled + // This operation is sound, as it is an atomic memory access + // that does not modify the memory/read value + ClockSource::HSI16 => { + assert!(unsafe { (&*RCC::ptr()).cr.read().hsion().bit_is_set() }) + } + _ => {} + } + + <$timer_type>::enable(apb1rn); + <$timer_type>::reset(apb1rn); + + // This operation is sound as `ClockSource as u8` only produces valid values + ccipr + .ccipr() + .modify(|_, w| w.$timXsel().bits(clock_source as u8)); + + // This operation is sound as `PreScaler as u8` (which is the "unsafe" part) only + // produces valid values + lptim.cfgr.modify(|_, w| unsafe { + w.enc() + .clear_bit() + .countmode() + .bit(count_mode != CountMode::Internal) + .presc() + .bits(prescaler as u8) + .cksel() + .clear_bit() + }); + + let mut instance = LowPowerTimer { lptim }; + + instance.enable(); + + instance.start_continuous_mode(); + instance.set_autoreload(arr_value); + instance.set_compare_match(compare_value); + instance + } + + /// Enable interrupts for the specified event + pub fn listen(&mut self, event: Event) { + // LPTIM_IER may only be modified when LPTIM is disabled + self.disable(); + self.lptim.ier.modify(|_, w| match event { + Event::CompareMatch => w.cmpmie().set_bit(), + Event::AutoReloadMatch => w.arrmie().set_bit(), + }); + self.enable(); + self.start_continuous_mode(); + } + + /// Disable interrupts for the specified event + pub fn unlisten(&mut self, event: Event) { + // LPTIM_IER may only be modified when LPTIM is disabled + self.disable(); + self.lptim.ier.modify(|_, w| match event { + Event::CompareMatch => w.cmpmie().clear_bit(), + Event::AutoReloadMatch => w.arrmie().clear_bit(), + }); + self.enable(); + self.start_continuous_mode(); + } + + /// Check if the specified event has been triggered for this LowPowerTimer. + /// + /// If this function returns `true` for an `Event` that this LowPowerTimer is listening for, + /// [`LowPowerTimer::clear_event_flag`] must be called for that event to prevent the + /// interrupt from looping eternally. This is not done in a single function to + /// avoid using a mutable reference for an operation that does not require it. + pub fn is_event_triggered(&self, event: Event) -> bool { + let reg_val = self.lptim.isr.read(); + match event { + Event::CompareMatch => reg_val.cmpm().bit_is_set(), + Event::AutoReloadMatch => reg_val.arrm().bit_is_set(), + } + } + + /// Clear the interrupt flag for the specified event + pub fn clear_event_flag(&mut self, event: Event) { + self.lptim.icr.write(|w| match event { + Event::CompareMatch => w.cmpmcf().set_bit(), + Event::AutoReloadMatch => w.arrmcf().set_bit(), + }); + } + + /// Set the compare match field for this LowPowerTimer + #[inline] + pub fn set_compare_match(&mut self, value: u16) { + // clear compare register update ok flag + self.lptim.icr.write(|w| w.cmpokcf().set_bit()); + + // This operation is sound as compare_value is a u16, and there are 16 writeable bits + // Additionally, the LPTIM peripheral will always be in the enabled state when this code is called + self.lptim.cmp.write(|w| unsafe { w.bits(value as u32) }); + + // wait for compare register update ok interrupt to be signalled + // (see RM0394 Rev 4, sec 30.4.10 for further explanation and + // sec. 30.7.1, Bit 4 for register field description) + while self.lptim.isr.read().cmpok().bit_is_clear() {} + } + + /// Set auto reload register + /// has to be used _after_ enabling of lptim + #[inline(always)] + pub fn set_autoreload(&mut self, arr_value: u16) { + // clear autoreload register OK interrupt flag + self.lptim.icr.write(|w| w.arrokcf().set_bit()); + + // Write autoreload value + // This operation is sound as arr_value is a u16, and there are 16 writeable bits + self.lptim + .arr + .write(|w| unsafe { w.bits(arr_value as u32) }); + + // wait for autoreload write ok interrupt to be signalled + // (see RM0394 Rev 4, sec 30.4.10 for further explanation and + // sec. 30.7.1, Bit 4 for register field description) + while self.lptim.isr.read().arrok().bit_is_clear() {} + } + + /// Get the current counter value for this LowPowerTimer + #[inline] + pub fn get_counter(&self) -> u16 { + self.lptim.cnt.read().bits() as u16 + } + + /// Get the value of the ARR register for this + /// LowPowerTimer + #[inline] + pub fn get_arr(&self) -> u16 { + self.lptim.arr.read().bits() as u16 + } + + pub fn pause(&mut self) { + self.disable(); + } + + pub fn resume(&mut self) { + self.enable(); + self.start_continuous_mode(); + } + } + }; +} + +hal!(LPTIM1, lptim1, lptim1sel); +hal!(LPTIM2, lptim2, lptim2sel); diff --git a/src/ltdc.rs b/src/ltdc.rs index 4f5d5d0c..d877704b 100644 --- a/src/ltdc.rs +++ b/src/ltdc.rs @@ -294,7 +294,10 @@ impl DisplayController { w.pllsain().bits(best_plln as u16); w.pllsair().bits(best_pllr as u8) }); + #[cfg(feature = "f4")] rcc.dckcfgr().modify(|_, w| w.pllsaidivr().set(pllsaidivr)); + #[cfg(feature = "f7")] + rcc.dckcfgr1().modify(|_, w| w.pllsaidivr().set(pllsaidivr)); // Enable PLLSAI and wait for it rcc.cr().modify(|_, w| w.pllsaion().on()); diff --git a/src/otg_fs.rs b/src/otg_fs.rs index 92937e94..1a2ccc02 100644 --- a/src/otg_fs.rs +++ b/src/otg_fs.rs @@ -58,6 +58,8 @@ unsafe impl UsbPeripheral for USB { feature = "gpio-f413", feature = "gpio-f446", feature = "gpio-f469", + feature = "f7", + feature = "l4", ))] const ENDPOINT_COUNT: usize = 6; diff --git a/src/otg_hs.rs b/src/otg_hs.rs index f62a603b..2482b547 100644 --- a/src/otg_hs.rs +++ b/src/otg_hs.rs @@ -12,6 +12,8 @@ use crate::gpio::alt::otg_hs as alt; use crate::rcc::{Clocks, Enable, Reset}; use fugit::HertzU32 as Hertz; +#[cfg(feature = "usb_hs_phy")] +use synopsys_usb_otg::PhyType; pub use synopsys_usb_otg::UsbBus; use synopsys_usb_otg::UsbPeripheral; @@ -22,9 +24,14 @@ pub struct USB { pub pin_dm: alt::Dm, pub pin_dp: alt::Dp, pub hclk: Hertz, + #[cfg(feature = "usb_hs_phy")] + pub hse: Hertz, } impl USB { + /// Construct a USB peripheral wrapper. + /// + /// Call `UsbBus::new` to construct and initialize the USB peripheral driver. pub fn new( periphs: (pac::OTG_HS_GLOBAL, pac::OTG_HS_DEVICE, pac::OTG_HS_PWRCLK), pins: (impl Into, impl Into), @@ -34,9 +41,37 @@ impl USB { usb_global: periphs.0, usb_device: periphs.1, usb_pwrclk: periphs.2, + #[cfg(feature = "usb_hs_phy")] + usb_phy: None, pin_dm: pins.0.into(), pin_dp: pins.1.into(), hclk: clocks.hclk(), + #[cfg(feature = "usb_hs_phy")] + hse: clocks.hse().unwrap_or_else(|| 0.Hz()), + } + } + + #[cfg(feature = "usb_hs_phy")] + /// Construct a USB peripheral wrapper with internal HighSpeed PHY. + /// + /// Call `UsbBus::new` to construct and initialize the USB peripheral driver. + pub fn new_with_internal_hs_phy( + usb_global: pac::OTG_HS_GLOBAL, + usb_device: pac::OTG_HS_DEVICE, + usb_pwrclk: pac::OTG_HS_PWRCLK, + usb_phy: pac::USBPHYC, + pins: (PB14>, PB15>), + clocks: &Clocks, + ) -> Self { + Self { + usb_global, + usb_device, + usb_pwrclk, + usb_phy: Some(usb_phy), + pin_dm: pins.0, + pin_dp: pins.1, + hclk: pac::OTG_HS_GLOBAL::clock(clocks), + hse: clocks.hse().expect("HSE should be enabled"), } } } @@ -51,16 +86,23 @@ unsafe impl UsbPeripheral for USB { #[cfg(any(feature = "gpio-f417", feature = "gpio-f427"))] const ENDPOINT_COUNT: usize = 6; - #[cfg(any(feature = "gpio-f446", feature = "gpio-f469"))] + #[cfg(any(feature = "gpio-f446", feature = "gpio-f469", feature = "f7"))] const ENDPOINT_COUNT: usize = 9; fn enable() { - cortex_m::interrupt::free(|_| { - unsafe { - // Enable USB peripheral - pac::OTG_HS_GLOBAL::enable_unchecked(); - // Reset USB peripheral - pac::OTG_HS_GLOBAL::reset_unchecked(); + cortex_m::interrupt::free(|_| unsafe { + // Enable USB peripheral + pac::OTG_HS_GLOBAL::enable_unchecked(); + // Reset USB peripheral + pac::OTG_HS_GLOBAL::reset_unchecked(); + + #[cfg(feature = "usb_hs_phy")] + { + // Enable and reset HS PHY + let rcc = &*pac::RCC::ptr(); + rcc.ahb1enr.modify(|_, w| w.otghsulpien().enabled()); + pac::USBPHYC::enable_unchecked(); + pac::USBPHYC::reset_unchecked(); } }); } @@ -68,6 +110,58 @@ unsafe impl UsbPeripheral for USB { fn ahb_frequency_hz(&self) -> u32 { self.hclk.raw() } + + #[cfg(feature = "usb_hs_phy")] + #[inline(always)] + fn phy_type(&self) -> PhyType { + if self.usb_phy.is_some() { + PhyType::InternalHighSpeed + } else { + PhyType::InternalFullSpeed + } + } + + #[cfg(feature = "usb_hs_phy")] + // Setup LDO and PLL + fn setup_internal_hs_phy(&self) { + let phy = if let Some(phy) = self.usb_phy.as_ref() { + phy + } else { + // This should never happen as this function is only called when + // phy_type() is PhyType::InternalHighSpeed and it's possible only + // when self.usb_phy is not None + unreachable!() + }; + + // Calculate PLL1SEL + let pll1sel = match self.hse.raw() { + 12_000_000 => 0b000, + 12_500_000 => 0b001, + 16_000_000 => 0b011, + 24_000_000 => 0b100, + 25_000_000 => 0b101, + _ => panic!("HSE frequency is invalid for USBPHYC"), + }; + + // Turn on LDO + // For some reason setting the bit enables the LDO + phy.ldo.modify(|_, w| w.ldo_disable().set_bit()); + + // Busy wait until ldo_status becomes true + // Notice, this may hang + while phy.ldo.read().ldo_status().bit_is_clear() {} + + // Setup PLL + // This disables the the pll1 during tuning + phy.pll1.write(|w| unsafe { w.pll1sel().bits(pll1sel) }); + + phy.tune.modify(|r, w| unsafe { w.bits(r.bits() | 0xF13) }); + + phy.pll1.modify(|_, w| w.pll1en().set_bit()); + + // 2ms Delay required to get internal phy clock stable + cortex_m::asm::delay(432000); + } } pub type UsbBusType = UsbBus; diff --git a/src/prelude.rs b/src/prelude.rs index d3722cca..cf60b466 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -60,11 +60,16 @@ pub use crate::fmpi2c::I2cExt as _; pub use crate::gpio::outport::OutPort as _; pub use crate::gpio::ExtiPin as _stm32f4xx_hal_gpio_ExtiPin; pub use crate::gpio::GpioExt as _stm32f4xx_hal_gpio_GpioExt; +#[cfg(feature = "f4")] pub use crate::i2c::dma::I2CMasterHandleIT as _stm32f4xx_hal_i2c_dma_I2CMasterHandleIT; +#[cfg(feature = "f4")] pub use crate::i2c::dma::I2CMasterReadDMA as _stm32f4xx_hal_i2c_dma_I2CMasterReadDMA; +#[cfg(feature = "f4")] pub use crate::i2c::dma::I2CMasterWriteDMA as _stm32f4xx_hal_i2c_dma_I2CMasterWriteDMA; +#[cfg(feature = "f4")] pub use crate::i2c::dma::I2CMasterWriteReadDMA as _stm32f4xx_hal_i2c_dma_I2CMasterWriteReadDMA; pub use crate::i2c::I2cExt as _stm32f4xx_hal_i2c_I2cExt; +#[cfg(feature = "f4")] pub use crate::i2s::I2sExt as _stm32f4xx_hal_i2s_I2sExt; pub use crate::qei::QeiExt as _stm32f4xx_hal_QeiExt; pub use crate::rcc::RccExt as _stm32f4xx_hal_rcc_RccExt; diff --git a/src/pwr/l4.rs b/src/pwr/l4.rs new file mode 100644 index 00000000..fb00250d --- /dev/null +++ b/src/pwr/l4.rs @@ -0,0 +1,217 @@ +//! Power management + +use crate::pac::{pwr, PWR}; +use crate::rcc::{Clocks, Enable, APB1R1}; +use bitfield::{bitfield, BitRange}; +use cortex_m::peripheral::SCB; +use fugit::RateExtU32; + +/// PWR error +#[non_exhaustive] +#[derive(Debug)] +pub enum Error { + /// Power regulator con not be switched to the low-power voltage due to the system clock frequency being higher than 26MHz + SysClkTooHighVos, + /// System can not be switched to the low-power run mode due to the system clock frequency being higher than 2MHz + SysClkTooHighLpr, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VosRange { + #[doc = "High-Performance range, 1.2V, up to 80 MHz"] + HighPerformance = 0b01, + #[doc = "Low-power range, 1.0V, up to 26MHz"] + LowPower = 0b10, +} + +bitfield! { + pub struct WakeUpSource(u16); + impl Debug; + // The fields default to u16 + pub wkup1, set_wkup1: 0; + pub wkup2, set_wkup2: 1; + pub wkup3, set_wkup3: 2; + pub wkup4, set_wkup4: 3; + pub wkup5, set_wkup5: 4; + pub internal_wkup, set_internal_wkup: 15; +} + +pub struct Pwr { + pub cr1: CR1, + pub cr2: CR2, + pub cr3: CR3, + pub cr4: CR4, + pub scr: SCR, + pub sr1: SR1, +} + +impl Pwr { + /// Configures dynamic voltage regulator range + /// + /// Will panic if low-power range is selected for higher system clock + pub fn set_power_range(&mut self, range: VosRange, clocks: &Clocks) -> Result<(), Error> { + match range { + VosRange::HighPerformance => unsafe { + { + self.cr1 + .reg() + .modify(|_, w| w.vos().bits(VosRange::HighPerformance as u8)) + } + Ok(()) + }, + VosRange::LowPower => { + if clocks.sysclk() > 26.MHz::<1, 1>() { + Err(Error::SysClkTooHighVos) + } else { + unsafe { + self.cr1 + .reg() + .modify(|_, w| w.vos().bits(VosRange::LowPower as u8)) + } + Ok(()) + } + } + } + } + + /// Switches the system into low power run mode + pub fn low_power_run(&mut self, clocks: &Clocks) -> Result<(), Error> { + if clocks.sysclk() > 2.MHz::<1, 1>() { + Err(Error::SysClkTooHighLpr) + } else { + self.cr1.reg().modify(|_, w| w.lpr().set_bit()); + Ok(()) + } + } + + /// Enters 'Shutdown' low power mode. + pub fn shutdown(&mut self, wkup: &WakeUpSource, scb: &mut SCB) -> ! { + unsafe { + self.cr3.reg().modify(|_, w| w.bits(wkup.bit_range(0, 7))); + } + + if wkup.internal_wkup() { + // Can't apply directly due to the APC and RPS bits + self.cr3.reg().modify(|_, w| w.ewf().set_bit()) + } + scb.set_sleepdeep(); + self.scr.reg().write(|w| { + w.wuf1() + .set_bit() + .wuf2() + .set_bit() + .wuf3() + .set_bit() + .wuf4() + .set_bit() + .wuf5() + .set_bit() + .sbf() + .set_bit() + }); + unsafe { self.cr1.reg().modify(|_, w| w.lpms().bits(0b111)) }; + cortex_m::asm::dsb(); + cortex_m::asm::wfi(); + loop {} + } + + /// Returns the reason, why wakeup from shutdown happened. In case there is more then one, + /// a single random reason will be returned + pub fn read_wakeup_reason(&mut self) -> WakeUpSource { + WakeUpSource(self.sr1.reg().read().bits() as u16) + } +} + +/// Extension trait that constrains the `PWR` peripheral +pub trait PwrExt { + /// Constrains the `PWR` peripheral so it plays nicely with the other abstractions + fn constrain(self, _: &mut APB1R1) -> Pwr; +} + +impl PwrExt for PWR { + fn constrain(self, apb1r1: &mut APB1R1) -> Pwr { + // Enable the peripheral clock + PWR::enable(apb1r1); + Pwr { + cr1: CR1 { _0: () }, + cr2: CR2 { _0: () }, + cr3: CR3 { _0: () }, + cr4: CR4 { _0: () }, + scr: SCR { _0: () }, + sr1: SR1 { _0: () }, + } + } +} + +/// CR1 +pub struct CR1 { + _0: (), +} + +impl CR1 { + pub(crate) fn reg(&mut self) -> &pwr::CR1 { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*PWR::ptr()).cr1 } + } +} +/// CR2 +pub struct CR2 { + _0: (), +} + +impl CR2 { + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn reg(&mut self) -> &pwr::CR2 { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*PWR::ptr()).cr2 } + } +} +/// CR3 +pub struct CR3 { + _0: (), +} + +impl CR3 { + pub(crate) fn reg(&mut self) -> &pwr::CR3 { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*PWR::ptr()).cr3 } + } +} +/// CR4 +pub struct CR4 { + _0: (), +} + +impl CR4 { + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn reg(&mut self) -> &pwr::CR4 { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*PWR::ptr()).cr4 } + } +} + +/// SCR +pub struct SCR { + _0: (), +} + +impl SCR { + pub(crate) fn reg(&mut self) -> &pwr::SCR { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*PWR::ptr()).scr } + } +} + +/// SCR +pub struct SR1 { + _0: (), +} + +impl SR1 { + pub(crate) fn reg(&mut self) -> &pwr::SR1 { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*PWR::ptr()).sr1 } + } +} diff --git a/src/qei.rs b/src/qei.rs index 5a9c2e36..0a53ed58 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -105,7 +105,11 @@ macro_rules! hal { impl Instance for $TIM { fn setup_qei(&mut self) { // Configure TxC1 and TxC2 as captures + #[cfg(not(feature = "g4"))] self.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2()); + #[cfg(feature = "g4")] + self.ccmr1_input() + .write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) }); // enable and configure to capture on rising edge self.ccer().write(|w| { w.cc1e().set_bit().cc1p().clear_bit(); diff --git a/src/rcc/f0.rs b/src/rcc/f0.rs new file mode 100644 index 00000000..e013e7be --- /dev/null +++ b/src/rcc/f0.rs @@ -0,0 +1,624 @@ +use crate::pac::RCC; +use crate::time::Hertz; + +/// Extension trait that sets up the `RCC` peripheral +pub trait RccExt { + /// Configure the clocks of the RCC peripheral + fn configure(self) -> CFGR; +} + +impl RccExt for RCC { + fn configure(self) -> CFGR { + CFGR { + hclk: None, + pclk: None, + sysclk: None, + clock_src: SysClkSource::HSI, + /// CRS is only available on devices with HSI48 + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + crs: None, + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f072", + feature = "stm32f078", + ))] + usb_src: USBClockSource::HSI48, + #[cfg(feature = "stm32f070")] + usb_src: USBClockSource::Disabled, + rcc: self, + } + } +} + +/// Constrained RCC peripheral +pub struct Rcc { + pub clocks: Clocks, + pub(crate) regs: RCC, +} + +pub enum HSEBypassMode { + /// Not bypassed: for crystals + NotBypassed, + /// Bypassed: for external clock sources + Bypassed, +} +#[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f070", // Doesn't have HSI48 + feature = "stm32f072", + feature = "stm32f078", +))] +#[allow(clippy::upper_case_acronyms)] +pub enum USBClockSource { + #[cfg(feature = "stm32f070")] + /// USB peripheral's tranceiver is disabled + Disabled, + #[cfg(not(feature = "stm32f070"))] + /// HSI48 is used as USB peripheral tranceiver clock + HSI48, + /// PLL output is used as USB peripheral tranceiver clock + PLL, +} +/// RCC for F0x0 devices +#[cfg(any(feature = "stm32f030", feature = "stm32f070",))] +mod inner { + use crate::pac::{rcc::cfgr::SW_A, RCC}; + + pub(super) const HSI: u32 = 8_000_000; // Hz + + // Does PLLSRC have two bits? + #[cfg(any( + feature = "stm32f030x4", + feature = "stm32f030x6", + feature = "stm32f030x8", + // Reference Manual states HSI_PREDIV is not available on stm32f070/, but it actually + // seems to work, and also is referenced in its CMSIS header files stm32f070x6.h and stm32f070xb.h + // But, for now be conservative and mark it as not available. + feature = "stm32f070", + // It's also listed in the CMSIS headers for the f030xc, + feature = "stm32f030xc" + ))] + pub(super) const RCC_PLLSRC_PREDIV1_SUPPORT: bool = false; + + #[allow(clippy::upper_case_acronyms)] + pub(super) enum SysClkSource { + HSI, + /// High-speed external clock(freq,bypassed) + HSE(u32, super::HSEBypassMode), + } + + pub(super) fn get_freq(c_src: &SysClkSource) -> u32 { + // Select clock source based on user input and capability + // Highest selected frequency source available takes precedent. + match c_src { + SysClkSource::HSE(freq, _) => *freq, + _ => HSI, + } + } + + pub(super) fn enable_clock(rcc: &mut RCC, c_src: &SysClkSource) { + // Enable the requested clock + match c_src { + SysClkSource::HSE(_, bypassed) => { + match bypassed { + super::HSEBypassMode::NotBypassed => { + rcc.cr + .modify(|_, w| w.csson().on().hseon().on().hsebyp().not_bypassed()); + } + super::HSEBypassMode::Bypassed => { + rcc.cr + .modify(|_, w| w.csson().on().hseon().on().hsebyp().bypassed()); + } + } + while !rcc.cr.read().hserdy().bit_is_set() {} + } + SysClkSource::HSI => { + rcc.cr.write(|w| w.hsion().set_bit()); + while rcc.cr.read().hsirdy().bit_is_clear() {} + } + } + } + + pub(super) fn enable_pll( + rcc: &mut RCC, + c_src: &SysClkSource, + pllmul_bits: u8, + ppre_bits: u8, + hpre_bits: u8, + ) { + let pllsrc_bit: bool = match c_src { + SysClkSource::HSI => false, + SysClkSource::HSE(_, _) => true, + }; + + // Set PLL source and multiplier + rcc.cfgr + .modify(|_, w| w.pllsrc().bit(pllsrc_bit).pllmul().bits(pllmul_bits)); + + rcc.cr.modify(|_, w| w.pllon().set_bit()); + while rcc.cr.read().pllrdy().bit_is_clear() {} + + rcc.cfgr + .modify(|_, w| unsafe { w.ppre().bits(ppre_bits).hpre().bits(hpre_bits).sw().pll() }); + } + + pub(super) fn get_sww(c_src: &SysClkSource) -> SW_A { + match c_src { + SysClkSource::HSI => SW_A::HSI, + SysClkSource::HSE(_, _) => SW_A::HSE, + } + } +} +/// RCC for F0x1, F0x2, F0x8 devices +#[cfg(any( + feature = "stm32f031", + feature = "stm32f038", + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f051", + feature = "stm32f058", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", +))] +mod inner { + use crate::pac::{rcc::cfgr::SW_A, RCC}; + + pub(super) const HSI: u32 = 8_000_000; // Hz + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + pub(super) const HSI48: u32 = 48_000_000; // Hz + + // Does PLLSRC have two bits? + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + pub(super) const RCC_PLLSRC_PREDIV1_SUPPORT: bool = true; + #[cfg(any( + feature = "stm32f031", + feature = "stm32f038", + feature = "stm32f051", + feature = "stm32f058" + ))] + pub(super) const RCC_PLLSRC_PREDIV1_SUPPORT: bool = false; + + #[allow(clippy::upper_case_acronyms)] + pub(super) enum SysClkSource { + HSI, + /// High-speed external clock(freq,bypassed) + HSE(u32, super::HSEBypassMode), + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + HSI48, + } + + pub(super) fn get_freq(c_src: &SysClkSource) -> u32 { + // Select clock source based on user input and capability + // Highest selected frequency source available takes precedent. + match c_src { + SysClkSource::HSE(freq, _) => *freq, + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + SysClkSource::HSI48 => HSI48, + _ => HSI, + } + } + + pub(super) fn enable_clock(rcc: &mut RCC, c_src: &SysClkSource) { + // Enable the requested clock + match c_src { + SysClkSource::HSE(_, bypassed) => { + match bypassed { + super::HSEBypassMode::NotBypassed => { + rcc.cr + .modify(|_, w| w.csson().on().hseon().on().hsebyp().not_bypassed()); + } + super::HSEBypassMode::Bypassed => { + rcc.cr + .modify(|_, w| w.csson().on().hseon().on().hsebyp().bypassed()); + } + } + + while !rcc.cr.read().hserdy().bit_is_set() {} + } + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + SysClkSource::HSI48 => { + rcc.cr2.modify(|_, w| w.hsi48on().set_bit()); + while rcc.cr2.read().hsi48rdy().bit_is_clear() {} + } + SysClkSource::HSI => { + rcc.cr.write(|w| w.hsion().set_bit()); + while rcc.cr.read().hsirdy().bit_is_clear() {} + } + } + } + + pub(super) fn enable_pll( + rcc: &mut RCC, + c_src: &SysClkSource, + pllmul_bits: u8, + ppre_bits: u8, + hpre_bits: u8, + ) { + let pllsrc_bit: u8 = match (c_src, RCC_PLLSRC_PREDIV1_SUPPORT) { + (SysClkSource::HSI, false) => 0b00, // HSI/2 + (SysClkSource::HSI, true) => 0b01, // HSI/PREDIV + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + (SysClkSource::HSI48, _) => 0b11, + (SysClkSource::HSE(_, _), _) => 0b10, + }; + + // Set PLL source and multiplier + rcc.cfgr + .modify(|_, w| w.pllsrc().bits(pllsrc_bit).pllmul().bits(pllmul_bits)); + + rcc.cr.modify(|_, w| w.pllon().set_bit()); + while rcc.cr.read().pllrdy().bit_is_clear() {} + + rcc.cfgr + .modify(|_, w| unsafe { w.ppre().bits(ppre_bits).hpre().bits(hpre_bits).sw().pll() }); + } + + pub(super) fn get_sww(c_src: &SysClkSource) -> SW_A { + match c_src { + SysClkSource::HSI => SW_A::HSI, + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + SysClkSource::HSI48 => SW_A::HSI48, + SysClkSource::HSE(_, _) => SW_A::HSE, + } + } +} + +use self::inner::SysClkSource; + +pub struct CFGR { + hclk: Option, + pclk: Option, + sysclk: Option, + clock_src: SysClkSource, + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f070", + feature = "stm32f072", + feature = "stm32f078", + ))] + usb_src: USBClockSource, + /// CRS is only available on devices with HSI48 + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + crs: Option, + rcc: RCC, +} + +impl CFGR { + pub fn hse(mut self, freq: F, bypass: HSEBypassMode) -> Self + where + F: Into, + { + self.clock_src = SysClkSource::HSE(freq.into().0, bypass); + self + } + + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + pub fn hsi48(mut self) -> Self { + self.clock_src = SysClkSource::HSI48; + self + } + + pub fn hclk(mut self, freq: F) -> Self + where + F: Into, + { + self.hclk = Some(freq.into().0); + self + } + + pub fn pclk(mut self, freq: F) -> Self + where + F: Into, + { + self.pclk = Some(freq.into().0); + self + } + + pub fn sysclk(mut self, freq: F) -> Self + where + F: Into, + { + self.sysclk = Some(freq.into().0); + self + } + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f070", + feature = "stm32f072", + feature = "stm32f078", + ))] + /// Set the USB clock source (only valid for STM32F0xx with USB) + pub fn usbsrc(mut self, src: USBClockSource) -> Self { + self.usb_src = src; + self + } + + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + pub fn enable_crs(mut self, crs: crate::pac::CRS) -> Self { + self.crs = Some(crs); + self + } + + pub fn freeze(mut self, flash: &mut crate::pac::FLASH) -> Rcc { + // Default to lowest frequency clock on all systems. + let sysclk = self.sysclk.unwrap_or(self::inner::HSI); + + let r_sysclk; // The "real" sysclock value, calculated below + let pllmul_bits; + + // Select clock source based on user input and capability + // Highest selected frequency source available takes precedent. + // For F04x, F07x, F09x parts, use HSI48 if requested. + let src_clk_freq = self::inner::get_freq(&self.clock_src); + + // Pll check + if sysclk == src_clk_freq { + // Bypass pll if src clk and requested sysclk are the same, to save power. + // The only reason to override this behaviour is if the sysclk source were HSI, and you + // were running the USB off the PLL... + pllmul_bits = None; + r_sysclk = src_clk_freq; + } else { + // FIXME: This assumes reset value of prediv (/1). + // There is no logic to set plldiv to any value other than 1. + // Note that for some models, HSI is fixed by hardware to divide by two. + let pllprediv = match (&self.clock_src, self::inner::RCC_PLLSRC_PREDIV1_SUPPORT) { + (self::inner::SysClkSource::HSI, false) => 2, + (_, _) => 1, + }; + // Find PLL multiplier that creates freq closest to target + let pllmul = (2 * pllprediv * self.sysclk.unwrap_or(src_clk_freq) + src_clk_freq) + / src_clk_freq + / 2; + let pllmul = core::cmp::min(core::cmp::max(pllmul, 2), 16); + r_sysclk = pllmul * src_clk_freq / pllprediv; + + pllmul_bits = Some(pllmul as u8 - 2) + } + + let hpre_bits = self + .hclk + .map(|hclk| match r_sysclk / hclk { + 0 => unreachable!(), + 1 => 0b0111, + 2 => 0b1000, + 3..=5 => 0b1001, + 6..=11 => 0b1010, + 12..=39 => 0b1011, + 40..=95 => 0b1100, + 96..=191 => 0b1101, + 192..=383 => 0b1110, + _ => 0b1111, + }) + .unwrap_or(0b0111); + + let hclk = r_sysclk / (1 << (hpre_bits - 0b0111)); + + let ppre_bits = self + .pclk + .map(|pclk| match hclk / pclk { + 0 => unreachable!(), + 1 => 0b011, + 2 => 0b100, + 3..=5 => 0b101, + 6..=11 => 0b110, + _ => 0b111, + }) + .unwrap_or(0b011); + + let ppre: u8 = 1 << (ppre_bits - 0b011); + let pclk = hclk / cast::u32(ppre); + + // adjust flash wait states + unsafe { + flash.acr.write(|w| { + w.latency().bits(if r_sysclk <= 24_000_000 { + 0b000 + } else if r_sysclk <= 48_000_000 { + 0b001 + } else { + 0b010 + }) + }) + } + + // Enable the requested clock + self::inner::enable_clock(&mut self.rcc, &self.clock_src); + + // Only need to set USBSW if MCU has USB HW + #[cfg(feature = "stm32f070")] + { + match self.usb_src { + USBClockSource::Disabled => self.rcc.cfgr3.modify(|_, w| w.usbsw().clear_bit()), + USBClockSource::PLL => self.rcc.cfgr3.modify(|_, w| w.usbsw().set_bit()), + } + } + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f072", + feature = "stm32f078", + ))] + match self.usb_src { + USBClockSource::HSI48 => self.rcc.cfgr3.modify(|_, w| w.usbsw().clear_bit()), + USBClockSource::PLL => self.rcc.cfgr3.modify(|_, w| w.usbsw().set_bit()), + } + // Set up rcc based on above calculated configuration. + + // Enable PLL + if let Some(pllmul_bits) = pllmul_bits { + self::inner::enable_pll( + &mut self.rcc, + &self.clock_src, + pllmul_bits, + ppre_bits, + hpre_bits, + ); + } else { + let sw_var = self::inner::get_sww(&self.clock_src); + + // CRS is only available on devices with HSI48 + #[cfg(any( + feature = "stm32f042", + feature = "stm32f048", + feature = "stm32f071", + feature = "stm32f072", + feature = "stm32f078", + feature = "stm32f091", + feature = "stm32f098", + ))] + match self.crs { + Some(crs) => { + self.rcc.apb1enr.modify(|_, w| w.crsen().set_bit()); + + // Initialize clock recovery + // Set autotrim enabled. + crs.cr.modify(|_, w| w.autotrimen().set_bit()); + // Enable CR + crs.cr.modify(|_, w| w.cen().set_bit()); + } + _ => {} + } + + // use HSI as source + self.rcc.cfgr.modify(|_, w| unsafe { + w.ppre() + .bits(ppre_bits) + .hpre() + .bits(hpre_bits) + .sw() + .variant(sw_var) + }); + } + Rcc { + clocks: Clocks { + hclk: Hertz(hclk), + pclk: Hertz(pclk), + sysclk: Hertz(sysclk), + }, + regs: self.rcc, + } + } +} + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no longer be changed +#[derive(Clone, Copy)] +pub struct Clocks { + hclk: Hertz, + pclk: Hertz, + sysclk: Hertz, +} + +impl Clocks { + /// Returns the frequency of the AHB + pub fn hclk(&self) -> Hertz { + self.hclk + } + + /// Returns the frequency of the APB + pub fn pclk(&self) -> Hertz { + self.pclk + } + + /// Returns the system (core) frequency + pub fn sysclk(&self) -> Hertz { + self.sysclk + } +} diff --git a/src/rcc/f2/mod.rs b/src/rcc/f2/mod.rs new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/src/rcc/f2/mod.rs @@ -0,0 +1 @@ + diff --git a/src/rcc/f3/enable.rs b/src/rcc/f3/enable.rs new file mode 100644 index 00000000..b16c3deb --- /dev/null +++ b/src/rcc/f3/enable.rs @@ -0,0 +1,189 @@ +use super::*; + +macro_rules! bus_enable { + ($PER:ident => $en:ident) => { + impl Enable for crate::pac::$PER { + #[inline(always)] + fn enable(bus: &mut Self::Bus) { + bus.enr().modify(|_, w| w.$en().set_bit()); + } + #[inline(always)] + fn disable(bus: &mut Self::Bus) { + bus.enr().modify(|_, w| w.$en().clear_bit()); + } + #[inline(always)] + fn is_enabled() -> bool { + Self::Bus::new().enr().read().$en().bit_is_set() + } + #[inline(always)] + fn is_disabled() -> bool { + Self::Bus::new().enr().read().$en().bit_is_clear() + } + #[inline(always)] + unsafe fn enable_unchecked() { + Self::enable(&mut Self::Bus::new()); + } + #[inline(always)] + unsafe fn disable_unchecked() { + Self::disable(&mut Self::Bus::new()); + } + } + }; +} +macro_rules! bus_reset { + ($PER:ident => $rst:ident) => { + impl Reset for crate::pac::$PER { + #[inline(always)] + fn reset(bus: &mut Self::Bus) { + bus.rstr().modify(|_, w| w.$rst().set_bit()); + bus.rstr().modify(|_, w| w.$rst().clear_bit()); + } + #[inline(always)] + unsafe fn reset_unchecked() { + Self::reset(&mut Self::Bus::new()); + } + } + }; +} + +macro_rules! bus { + ($($PER:ident => ($busX:ty, $($en:ident)?, $($rst:ident)?),)+) => { + $( + impl crate::Sealed for crate::pac::$PER {} + impl RccBus for crate::pac::$PER { + type Bus = $busX; + } + $(bus_enable!($PER => $en);)? + $(bus_reset!($PER => $rst);)? + )+ + }; +} + +bus! { + DMA1 => (AHB, dma1en,), // 0 + CRC => (AHB, crcen,), // 6 + GPIOA => (AHB, iopaen, ioparst), // 17 + GPIOB => (AHB, iopben, iopbrst), // 18 + GPIOC => (AHB, iopcen, iopcrst), // 19 + GPIOD => (AHB, iopden, iopdrst), // 20 + GPIOF => (AHB, iopfen, iopfrst), // 22 + TSC => (AHB, tscen, tscrst), // 24 + + TIM2 => (APB1, tim2en, tim2rst), // 0 + TIM6 => (APB1, tim6en, tim6rst), // 4 + WWDG => (APB1, wwdgen, wwdgrst), // 11 + USART2 => (APB1, usart2en, usart2rst), // 17 + USART3 => (APB1, usart3en, usart3rst), // 18 + I2C1 => (APB1, i2c1en, i2c1rst), // 21 + PWR => (APB1, pwren, pwrrst), // 28 + + SYSCFG => (APB2, syscfgen, syscfgrst), // 0 + USART1 => (APB2, usart1en, usart1rst), // 14 + TIM15 => (APB2, tim15en, tim15rst), // 16 + TIM16 => (APB2, tim16en, tim16rst), // 17 + TIM17 => (APB2, tim17en, tim17rst), // 18 +} + +#[cfg(any( + feature = "svd-f301", + feature = "svd-f302", + feature = "svd-f303", + feature = "svd-f373", +))] +bus! { + SPI2 => (APB1, spi2en, spi2rst), // 14 + SPI3 => (APB1, spi3en, spi3rst), // 15 + I2C2 => (APB1, i2c2en, i2c2rst), // 22 +} + +#[cfg(any(feature = "svd-f302", feature = "svd-f303", feature = "svd-f373"))] +bus! { + DMA2 => (AHB, dma2en,), // 1 + GPIOE => (AHB, iopeen, ioperst), // 21 + TIM4 => (APB1, tim4en, tim4rst), // 2 + USB => (APB1, usben, usbrst), // 23 +} + +#[cfg(any( + feature = "svd-f302", + feature = "svd-f303", + feature = "svd-f373", + feature = "svd-f3x4" +))] +bus! { + TIM3 => (APB1, tim3en, tim3rst), // 1 + CAN => (APB1, canen, canrst), // 25 + SPI1 => (APB2, spi1en, spi1rst), // 12 +} + +#[cfg(feature = "svd-f301")] +bus! { + ADC1_2 => (AHB, adc1en, adc1rst), // 28 +} + +#[cfg(any(feature = "svd-f302", feature = "svd-f303", feature = "svd-f3x4"))] +bus! { + ADC1_2 => (AHB, adc12en, adc12rst), // 28 +} + +#[cfg(any(feature = "svd-f302", feature = "svd-f303"))] +bus! { + FMC => (AHB, fmcen, fmcrst), // 5 + SPI4 => (APB2, spi4en, spi4rst), // 15 + GPIOH => (AHB, iophen, iophrst), // 16 + UART4 => (APB1, uart4en, uart4rst), // 19 + UART5 => (APB1, uart5en, uart5rst), // 20 + GPIOG => (AHB, iopgen, iopgrst), // 23 +} + +#[cfg(any( + feature = "svd-f301", + feature = "svd-f302", + feature = "svd-f303", + feature = "svd-f3x4" +))] +bus! { + TIM1 => (APB2, tim1en, tim1rst), // 11 +} + +bus! { + DAC1 => (APB1, dac1en, dac1rst), // 29 +} + +#[cfg(any(feature = "svd-f303", feature = "svd-f373", feature = "svd-f3x4"))] +bus! { + TIM7 => (APB1, tim7en, tim7rst), // 5 + DAC2 => (APB1, dac2en,), // 26 +} + +#[cfg(any(feature = "svd-f301", feature = "svd-f302", feature = "svd-f303"))] +bus! { + I2C3 => (APB1, i2c3en, i2c3rst), // 30 +} + +#[cfg(feature = "svd-f303")] +bus! { + TIM8 => (APB2, tim8en, tim8rst), // 13 + TIM20 => (APB2, tim20en, tim20rst), // 20 + ADC3_4 => (AHB, adc34en, adc34rst), // 29 +} + +#[cfg(feature = "svd-f373")] +bus! { + TIM5 => (APB1, tim5en, tim5rst), // 3 + TIM12 => (APB1, tim12en, tim12rst), // 6 + TIM13 => (APB1, tim13en, tim13rst), // 7 + TIM14 => (APB1, tim14en, tim14rst), // 8 + TIM18 => (APB1, tim18en, tim18rst), // 9 + CEC => (APB1, cecen, cecrst), // 30 + TIM19 => (APB2, tim19en, tim19rst), // 19 + DBGMCU => (APB2, dbgmcuen,), // 22 + SDADC1 => (APB2, sdadc1en, sdadc1rst), // 24 + SDADC2 => (APB2, sdadc2en, sdadc2rst), // 25 + SDADC3 => (APB2, sdadc3en, sdadc3rst), // 26 +} + +#[cfg(feature = "svd-f3x4")] +bus! { + HRTIM_COMMON => (APB2, hrtim1en, hrtim1rst), // 29 +} diff --git a/src/rcc/f3/mod.rs b/src/rcc/f3/mod.rs new file mode 100644 index 00000000..7e7e13a8 --- /dev/null +++ b/src/rcc/f3/mod.rs @@ -0,0 +1,967 @@ +//! # Reset and Clock Control +//! +//! The most important function this module +//! delivers is the clock configuration. +//! +//! To configure the clock, we first have to obtain the +//! device peripherals. +//! +//! ``` +//! # use cortex_m_rt::entry; +//! # use stm32f3xx-hal::{prelude::*, time::rate::*}; +//! +//! # #[entry] +//! # fn main() -> ! { +//! // Get our peripherals +//! let dp = pac::Peripherals::take().unwrap(); +//! +//! let mut flash = dp.FLASH.constrain(); +//! let mut rcc = dp.RCC.constrain(); +//! # } +//! ``` +//! +//! After that we can configure the clock +//! +//! ``` +//! # use cortex_m_rt::entry; +//! # use stm32f3xx-hal::{prelude::*, time::rate::*}; +//! # +//! # #[entry] +//! # fn main() -> ! { +//! # let dp = pac::Peripherals::take().unwrap(); +//! +//! # let mut flash = dp.FLASH.constrain(); +//! # let mut rcc = dp.RCC.constrain(); +//! let clocks = rcc.cfgr +//! // Using the external oscillator +//! // Set the frequency to that of the external oscillator +//! .use_hse(8.MHz()) +//! // Set the frequency for the AHB bus, +//! // which the root of every following clock peripheral +//! .hclk(48.MHz()) +//! // The sysclk is equivalent to the core clock +//! .sysclk(48.MHz()) +//! // The following are peripheral clocks, which are both +//! // needed to configure specific peripherals. +//! // Looking at the peripheral function parameters +//! // should give more insight, which peripheral clock is needed. +//! .pclk1(12.MHz()) +//! .pclk2(12.MHz()) +//! // Freeze / apply the configuration and setup all clocks +//! .freeze(&mut flash.acr); +//! # } +//! ``` +//! +//! All fields can be omitted and will internally be set to a calculated default. +//! For more details read the documentation of the [`CFGR`] methods to +//! find out how to setup the clock. + +use crate::pac::{ + rcc::{self, cfgr, cfgr2}, + RCC, +}; + +use fugit::HertzU32 as Hertz; +use fugit::RateExtU32; + +use core::convert::TryInto; + +use crate::flash::ACR; + +impl crate::Sealed for RCC {} + +/// Extension trait that constrains the []`RCC`] peripheral +pub trait RccExt: crate::Sealed { + /// Constrains the [`RCC`] peripheral. + /// + /// Consumes the [`pac::RCC`] peripheral and converts it to a [`HAL`] internal type + /// constraining it's public access surface to fit the design of the `HAL`. + /// + /// [`pac::RCC`]: `crate::pac::RCC` + /// [`HAL`]: `crate` + fn constrain(self) -> Rcc; +} + +mod enable; + +impl RccExt for RCC { + fn constrain(self) -> Rcc { + Rcc { + ahb: AHB { _0: () }, + apb1: APB1 { _0: () }, + apb2: APB2 { _0: () }, + bdcr: BDCR { _0: () }, + cfgr: CFGR::default(), + } + } +} + +/// Constrained RCC peripheral +/// +/// An instance of this struct is acquired by calling the [`constrain`](RccExt::constrain) function +/// on the [`RCC`](crate::pac::RCC) struct. +/// +/// ``` +/// let dp = pac::Peripherals::take().unwrap(); +/// let rcc = dp.RCC.constrain(); +/// ``` +pub struct Rcc { + /// AMBA High-performance Bus (AHB) registers + pub ahb: AHB, + /// Advanced Peripheral Bus 1 (APB1) registers + pub apb1: APB1, + /// Advanced Peripheral Bus 2 (APB2) registers + pub apb2: APB2, + /// RCC Backup Domain + pub bdcr: BDCR, + /// Clock configuration + pub cfgr: CFGR, +} + +/// AMBA High-performance Bus (AHB) registers +/// +/// An instance of this struct is acquired from the [`RCC`](crate::pac::RCC) struct. +/// +/// ``` +/// let dp = pac::Peripherals::take().unwrap(); +/// let rcc = dp.RCC.constrain(); +/// use_ahb(&mut rcc.ahb) +/// ``` +pub struct AHB { + _0: (), +} + +/// Advanced Peripheral Bus 1 (APB1) registers +/// +/// An instance of this struct is acquired from the [`RCC`](crate::pac::RCC) struct. +/// +/// ``` +/// let dp = pac::Peripherals::take().unwrap(); +/// let rcc = dp.RCC.constrain(); +/// use_apb1(&mut rcc.apb1) +/// ``` +pub struct APB1 { + _0: (), +} + +/// Advanced Peripheral Bus 2 (APB2) registers +/// +/// An instance of this struct is acquired from the [`RCC`](crate::pac::RCC) struct. +/// +/// ``` +/// let dp = pac::Peripherals::take().unwrap(); +/// let rcc = dp.RCC.constrain(); +/// use_apb2(&mut rcc.apb2) +/// ``` +pub struct APB2 { + _0: (), +} + +macro_rules! bus_struct { + ($($busX:ident => ($EN:ident, $en:ident, $RST:ident, $rst:ident),)+) => { + $( + impl $busX { + fn new() -> Self { + Self { _0: () } + } + + #[allow(unused)] + fn enr(&self) -> &rcc::$EN { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).$en } + } + + #[allow(unused)] + fn rstr(&self) -> &rcc::$RST { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).$rst } + } + } + )+ + }; +} + +bus_struct! { + AHB => (AHBENR, ahbenr, AHBRSTR, ahbrstr), + APB1 => (APB1ENR, apb1enr, APB1RSTR, apb1rstr), + APB2 => (APB2ENR, apb2enr, APB2RSTR, apb2rstr), +} + +/// Bus associated to peripheral +pub trait RccBus: crate::Sealed { + /// The underlying bus peripheral + type Bus; +} + +/// Enable/disable peripheral +pub trait Enable: RccBus { + /// Enables peripheral + fn enable(bus: &mut Self::Bus); + + /// Disables peripheral + fn disable(bus: &mut Self::Bus); + + /// Check if peripheral enabled + fn is_enabled() -> bool; + + /// Check if peripheral disabled + fn is_disabled() -> bool; + + /// Enables peripheral + /// + /// # Safety + /// + /// Takes access to RCC internally, so you have to make sure + /// you don't have race condition accessing RCC registers + unsafe fn enable_unchecked(); + + /// Disables peripheral + /// + /// # Safety + /// + /// Takes access to RCC internally, so you have to make sure + /// you don't have race condition accessing RCC registers + unsafe fn disable_unchecked(); +} + +/// Reset peripheral +pub trait Reset: RccBus { + /// Resets peripheral + fn reset(bus: &mut Self::Bus); + + /// # Safety + /// + /// Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked(); +} + +/// Frequency on bus that peripheral is connected in +pub trait BusClock { + /// Calculates frequency depending on `Clock` state + fn clock(clocks: &Clocks) -> Hertz; +} + +impl BusClock for T +where + T: RccBus, + T::Bus: BusClock, +{ + fn clock(clocks: &Clocks) -> Hertz { + T::Bus::clock(clocks) + } +} + +impl BusClock for AHB { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} +impl BusClock for APB1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk1 + } +} +impl BusClock for APB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk2 + } +} + +/// Frequency on bus that timer is connected in +pub trait BusTimerClock { + /// Calculates base frequency of timer depending on `Clock` state + fn timer_clock(clocks: &Clocks) -> Hertz; +} + +impl BusTimerClock for T +where + T: RccBus, + T::Bus: BusTimerClock, +{ + fn timer_clock(clocks: &Clocks) -> Hertz { + T::Bus::timer_clock(clocks) + } +} + +impl BusTimerClock for APB1 { + fn timer_clock(clocks: &Clocks) -> Hertz { + let pclk_mul = if clocks.ppre1 > 1 { 2 } else { 1 }; + clocks.pclk1 * pclk_mul + } +} +impl BusTimerClock for APB2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + let pclk_mul = if clocks.ppre2 > 1 { 2 } else { 1 }; + clocks.pclk2 * pclk_mul + } +} + +/// Frequency of interal hardware RC oscillator (HSI OSC) +pub const HSI: Hertz = Hertz::Hz(8_000_000); +/// Frequency of external 32.768 kHz oscillator (LSE OSC) +pub const LSE: Hertz = Hertz::Hz(32_768); + +// some microcontrollers do not have USB +#[cfg(any(feature = "stm32f301", feature = "stm32f318", feature = "stm32f334",))] +mod usb_clocking { + use crate::rcc::PllConfig; + + pub(crate) fn is_valid( + _sysclk: u32, + _hse: Option, + _pclk1: u32, + _pll_config: &Option, + ) -> (bool, bool) { + (false, false) + } + + pub(crate) fn set_usbpre(w: &mut W, _: bool) -> &mut W { + w + } +} + +#[cfg(not(any(feature = "stm32f301", feature = "stm32f318", feature = "stm32f334",)))] +mod usb_clocking { + use crate::pac::rcc::cfgr; + use crate::rcc::PllConfig; + + /// Check for all clock options to be + pub(crate) fn is_valid( + sysclk: u32, + hse: Option, + pclk1: u32, + pll_config: &Option, + ) -> (cfgr::USBPRE_A, bool) { + // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the + // PLL output frequency is a supported one. + // usbpre == false: divide clock by 1.5, otherwise no division + let usb_ok = hse.is_some() && pll_config.is_some(); + // The APB1 clock must have a minimum frequency of 10 MHz to avoid data overrun/underrun + // problems. [RM0316 32.5.2] + if pclk1 >= 10_000_000 { + match (usb_ok, sysclk) { + (true, 72_000_000) => (cfgr::USBPRE_A::Div15, true), + (true, 48_000_000) => (cfgr::USBPRE_A::Div1, true), + _ => (cfgr::USBPRE_A::Div1, false), + } + } else { + (cfgr::USBPRE_A::Div1, false) + } + } + + pub(crate) fn set_usbpre(w: &mut cfgr::W, usb_prescale: cfgr::USBPRE_A) -> &mut cfgr::W { + w.usbpre().variant(usb_prescale) + } +} + +/// Backup Domain Control register (RCC_BDCR) +pub struct BDCR { + _0: (), +} + +impl BDCR { + #[allow(unused)] + pub(crate) fn bdcr(&mut self) -> &rcc::BDCR { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).bdcr } + } +} + +/// Clock configuration +/// +/// An instance of this struct is acquired from the [`RCC`](crate::pac::RCC) struct. +/// +/// ``` +/// let dp = pac::Peripherals::take().unwrap(); +/// let rcc = dp.RCC.constrain(); +/// use_cfgr(&mut rcc.cfgr) +/// ``` +pub struct CFGR { + hse: Option, + hse_bypass: bool, + pll_bypass: bool, + css: bool, + hclk: Option, + pclk1: Option, + pclk2: Option, + sysclk: Option, +} + +impl Default for CFGR { + fn default() -> Self { + Self { + hse: None, + hse_bypass: false, + pll_bypass: true, + css: false, + hclk: None, + pclk1: None, + pclk2: None, + sysclk: None, + } + } +} + +pub(crate) struct PllConfig { + src: cfgr::PLLSRC_A, + mul: cfgr::PLLMUL_A, + div: Option, +} + +/// Determine the [greatest common divisor](https://en.wikipedia.org/wiki/Greatest_common_divisor) +/// +/// This function is based on the [Euclidean algorithm](https://en.wikipedia.org/wiki/Euclidean_algorithm). +// TODO(Sh3Rm4n): As num-traits is a indirecty dependecy of this crate through embedded-time, +// use its implementation instead. +fn gcd(mut a: u32, mut b: u32) -> u32 { + while b != 0 { + let r = a % b; + a = b; + b = r; + } + a +} + +/// Convert pll multiplier into equivalent register field type +fn into_pll_mul(mul: u8) -> cfgr::PLLMUL_A { + match mul { + 2 => cfgr::PLLMUL_A::Mul2, + 3 => cfgr::PLLMUL_A::Mul3, + 4 => cfgr::PLLMUL_A::Mul4, + 5 => cfgr::PLLMUL_A::Mul5, + 6 => cfgr::PLLMUL_A::Mul6, + 7 => cfgr::PLLMUL_A::Mul7, + 8 => cfgr::PLLMUL_A::Mul8, + 9 => cfgr::PLLMUL_A::Mul9, + 10 => cfgr::PLLMUL_A::Mul10, + 11 => cfgr::PLLMUL_A::Mul11, + 12 => cfgr::PLLMUL_A::Mul12, + 13 => cfgr::PLLMUL_A::Mul13, + 14 => cfgr::PLLMUL_A::Mul14, + 15 => cfgr::PLLMUL_A::Mul15, + 16 => cfgr::PLLMUL_A::Mul16, + _ => crate::unreachable!(), + } +} + +/// Convert pll divisor into equivalent register field type +fn into_pre_div(div: u8) -> cfgr2::PREDIV_A { + match div { + 1 => cfgr2::PREDIV_A::Div1, + 2 => cfgr2::PREDIV_A::Div2, + 3 => cfgr2::PREDIV_A::Div3, + 4 => cfgr2::PREDIV_A::Div4, + 5 => cfgr2::PREDIV_A::Div5, + 6 => cfgr2::PREDIV_A::Div6, + 7 => cfgr2::PREDIV_A::Div7, + 8 => cfgr2::PREDIV_A::Div8, + 9 => cfgr2::PREDIV_A::Div9, + 10 => cfgr2::PREDIV_A::Div10, + 11 => cfgr2::PREDIV_A::Div11, + 12 => cfgr2::PREDIV_A::Div12, + 13 => cfgr2::PREDIV_A::Div13, + 14 => cfgr2::PREDIV_A::Div14, + 15 => cfgr2::PREDIV_A::Div15, + 16 => cfgr2::PREDIV_A::Div16, + _ => crate::unreachable!(), + } +} + +impl CFGR { + /// Uses `HSE` (external oscillator) instead of `HSI` (internal RC oscillator) as the clock source. + pub fn use_hse(mut self, freq: Hertz) -> Self { + self.hse = Some(freq.raw()); + self + } + + /// Set this to disallow bypass the PLLCLK for the systemclock generation. + pub fn use_pll(mut self) -> Self { + self.pll_bypass = false; + self + } + + /// Enable `HSE` bypass. + /// + /// Uses user provided clock signal instead of an external oscillator. + /// `OSC_OUT` pin is free and can be used as GPIO. + /// + /// No effect if `HSE` is not enabled. + pub fn bypass_hse(mut self) -> Self { + self.hse_bypass = true; + self + } + + /// Enable `CSS` (Clock Security System). + /// + /// System clock is automatically switched to `HSI` and an interrupt (`CSSI`) is generated + /// when `HSE` clock failure is detected. + /// + /// No effect if `HSE` is not enabled. + pub fn enable_css(mut self) -> Self { + self.css = true; + self + } + + /// Sets a frequency for the AHB bus. + pub fn hclk(mut self, freq: Hertz) -> Self { + self.hclk = Some(freq.raw()); + self + } + + /// Sets a frequency for the `APB1` bus + /// + /// - Maximal supported frequency: 36 Mhz + /// + /// If not manually set, it will be set to [`CFGR::sysclk`] frequency + /// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz + pub fn pclk1(mut self, freq: Hertz) -> Self { + self.pclk1 = Some(freq.raw()); + self + } + + /// Sets a frequency for the `APB2` bus + /// + /// # Resolution and Limits + /// + /// - Maximal supported frequency with HSE: 72 Mhz + /// - Maximal supported frequency without HSE: 64 Mhz + pub fn pclk2(mut self, freq: Hertz) -> Self { + self.pclk2 = Some(freq.raw()); + self + } + + /// Sets the system (core) frequency + /// + /// # Resolution and Limits + /// + /// - Maximal supported frequency with `HSE`: 72 Mhz + /// - Maximal supported frequency without `HSE`: 64 Mhz + /// + /// If [`CFGR::use_hse`] is not set, `HSI / 2` will be used. + /// Only multiples of (HSI / 2) (4 Mhz) are allowed. + /// + /// This is true for devices **except** the following devices, + /// as these allow finer resolutions + /// even when using the internal oscillator: + /// + /// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398] + pub fn sysclk(mut self, freq: Hertz) -> Self { + self.sysclk = Some(freq.raw()); + self + } + + /// Calculate the values for the pll multiplier (`PLLMUL`) and the pll divisior (`PLLDIV`). + /// + /// These values are chosen depending on the chosen system clock (SYSCLK) and the frequency of the + /// oscillator clock (`HSE` / `HSI`). + /// + /// For these devices, `PLL_SRC` can selected between the internal oscillator (`HSI`) and + /// the external oscillator (`HSE`). + /// + /// HSI is divided by 2 before its transferred to `PLL_SRC`. + /// HSE can be divided between `1..16`, before it is transferred to `PLL_SRC`. + /// After this system clock frequency (`SYSCLK`) can be changed via multiplier. + /// The value can be multiplied with `2..16`. + /// + /// To determine the optimal values, if `HSE` is chosen as `PLL_SRC`, the greatest common divisor + /// is calculated and the limitations of the possible values are taken into consideration. + /// + /// `HSI` is simpler to calculate, but the possible system clocks are less than `HSE`, because the + /// division is not configurable. + #[cfg(not(feature = "gpio-f303e"))] + fn calc_pll(&self, sysclk: u32) -> (u32, PllConfig) { + let pllsrcclk = self.hse.unwrap_or(HSI.to_Hz() / 2); + // Get the optimal value for the pll divisor (PLL_DIV) and multiplier (PLL_MUL) + // Only for HSE PLL_DIV can be changed + let (pll_mul, pll_div): (u32, Option) = if self.hse.is_some() { + // Get the optimal value for the pll divisor (PLL_DIV) and multiplier (PLL_MUL) + // with the greatest common divisor calculation. + let common_divisor = gcd(sysclk, pllsrcclk); + let mut multiplier = sysclk / common_divisor; + let mut divisor = pllsrcclk / common_divisor; + + // Check if the multiplier can be represented by PLL_MUL + if multiplier == 1 { + // PLL_MUL minimal value is 2 + multiplier *= 2; + divisor *= 2; + } + + // PLL_MUL maximal value is 16 + crate::assert!(multiplier <= 16); + + // PRE_DIV maximal value is 16 + crate::assert!(divisor <= 16); + + (multiplier, Some(divisor)) + } + // HSI division is always divided by 2 and has no adjustable division + else { + let pll_mul = sysclk / pllsrcclk; + crate::assert!(pll_mul <= 16); + (pll_mul, None) + }; + + let sysclk = (pllsrcclk / pll_div.unwrap_or(1)) * pll_mul; + crate::assert!(sysclk <= 72_000_000); + + let pll_src = if self.hse.is_some() { + cfgr::PLLSRC_A::HseDivPrediv + } else { + cfgr::PLLSRC_A::HsiDiv2 + }; + + // Convert into register bit field types + let pll_mul_bits = into_pll_mul(pll_mul as u8); + let pll_div_bits = pll_div.map(|pll_div| into_pre_div(pll_div as u8)); + + ( + sysclk, + PllConfig { + src: pll_src, + mul: pll_mul_bits, + div: pll_div_bits, + }, + ) + } + + /// Calculate the values for the pll multiplier (`PLLMUL`) and the pll divisor (`PLLDIV`). + /// + /// These values are chosen depending on the chosen system clock (`SYSCLK`) and the frequency of the oscillator + /// clk (`HSI` / `HSE`). + /// + /// For these devices, `PLL_SRC` can be set to choose between the internal oscillator (HSI) and + /// the external oscillator (`HSE`). + /// After this the system clock frequency (`SYSCLK`) can be changed via a division and a + /// multiplication block. + /// It can be divided from with values `1..16` and multiplied from `2..16`. + /// + /// To determine the optimal values, the greatest common divisor is calculated and the + /// limitations of the possible values are taken into considiration. + #[cfg(feature = "gpio-f303e")] + fn calc_pll(&self, sysclk: u32) -> (u32, PllConfig) { + let pllsrcclk = self.hse.unwrap_or(HSI.integer()); + + let (pll_mul, pll_div) = { + // Get the optimal value for the pll divisor (PLL_DIV) and multiplcator (PLL_MUL) + // with the greatest common divisor calculation. + let common_divisor = gcd(sysclk, pllsrcclk); + let mut multiplier = sysclk / common_divisor; + let mut divisor = pllsrcclk / common_divisor; + + // Check if the multiplier can be represented by PLL_MUL + if multiplier == 1 { + // PLL_MUL minimal value is 2 + multiplier *= 2; + divisor *= 2; + } + + // PLL_MUL maximal value is 16 + crate::assert!(multiplier <= 16); + + // PRE_DIV maximal value is 16 + crate::assert!(divisor <= 16); + + (multiplier, divisor) + }; + + let sysclk = (pllsrcclk / pll_div) * pll_mul; + crate::assert!(sysclk <= 72_000_000); + + // Select hardware clock source of the PLL + // TODO Check whether HSI_DIV2 could be useful + let pll_src = if self.hse.is_some() { + cfgr::PLLSRC_A::HseDivPrediv + } else { + cfgr::PLLSRC_A::HseDivPrediv + }; + + // Convert into register bit field types + let pll_mul_bits = into_pll_mul(pll_mul as u8); + let pll_div_bits = into_pre_div(pll_div as u8); + + ( + sysclk, + PllConfig { + src: pll_src, + mul: pll_mul_bits, + div: Some(pll_div_bits), + }, + ) + } + + /// Get the system clock, the system clock source and the pll_options, if needed. + /// + /// The system clock source is determined by the chosen system clock and the provided hardware + /// clock. + /// This function does only chose the PLL if needed, otherwise it will use the oscillator clock as system clock. + /// + /// Calls [`CFGR::calc_pll`] internally. + fn get_sysclk(&self) -> (u32, cfgr::SW_A, Option) { + // If a sysclk is given, check if the PLL has to be used, + // else select the system clock source, which is either HSI or HSE. + match (self.sysclk, self.hse) { + // No need to use the PLL + // PLL is needed for USB, but we can make this assumption, to not use PLL here, + // because the two valid USB clocks, 72 Mhz and 48 Mhz, can't be generated + // directly from neither the internal rc (8 Mhz) nor the external + // Oscillator (max 32 Mhz), without using the PLL. + (Some(sysclk), Some(hse)) if sysclk == hse && self.pll_bypass => { + (hse, cfgr::SW_A::Hse, None) + } + // No need to use the PLL + (Some(sysclk), None) if sysclk == HSI.to_Hz() && self.pll_bypass => { + (HSI.to_Hz(), cfgr::SW_A::Hsi, None) + } + (Some(sysclk), _) => { + let (sysclk, pll_config) = self.calc_pll(sysclk); + (sysclk, cfgr::SW_A::Pll, Some(pll_config)) + } + // Use HSE as system clock + (None, Some(hse)) => (hse, cfgr::SW_A::Hse, None), + // Use HSI as system clock + (None, None) => (HSI.to_Hz(), cfgr::SW_A::Hsi, None), + } + } + + /// Freezes the clock configuration, making it effective + /// + /// This function internally calculates the specific. + /// divisors for the different clock peripheries. + /// + /// # Panics + /// + /// If any of the set frequencies via [`sysclk`](CFGR::sysclk), [`hclk`](CFGR::hclk), [`pclk1`](CFGR::pclk1) or [`pclk2`](CFGR::pclk2) + /// are invalid or can not be reached because of e.g. to low frequencies + /// of the former, as [`sysclk`](CFGR::sysclk) depends on the configuration of [`hclk`](CFGR::hclk) + /// this function will panic. + pub fn freeze(self, acr: &mut ACR) -> Clocks { + let (sysclk, sysclk_source, pll_config) = self.get_sysclk(); + + let (hpre_bits, hpre) = + self.hclk + .map_or((cfgr::HPRE_A::Div1, 1), |hclk| match sysclk / hclk { + 0 => crate::unreachable!(), + 1 => (cfgr::HPRE_A::Div1, 1), + 2 => (cfgr::HPRE_A::Div2, 2), + 3..=5 => (cfgr::HPRE_A::Div4, 4), + 6..=11 => (cfgr::HPRE_A::Div8, 8), + 12..=39 => (cfgr::HPRE_A::Div16, 16), + 40..=95 => (cfgr::HPRE_A::Div64, 64), + 96..=191 => (cfgr::HPRE_A::Div128, 128), + 192..=383 => (cfgr::HPRE_A::Div256, 256), + _ => (cfgr::HPRE_A::Div512, 512), + }); + + let hclk: u32 = sysclk / hpre; + + crate::assert!(hclk <= 72_000_000); + + let (mut ppre1_bits, mut ppre1) = + self.pclk1 + .map_or((cfgr::PPRE1_A::Div1, 1), |pclk1| match hclk / pclk1 { + 0 => crate::unreachable!(), + 1 => (cfgr::PPRE1_A::Div1, 1), + 2 => (cfgr::PPRE1_A::Div2, 2), + 3..=5 => (cfgr::PPRE1_A::Div4, 4), + 6..=11 => (cfgr::PPRE1_A::Div8, 8), + _ => (cfgr::PPRE1_A::Div16, 16), + }); + + let mut pclk1 = hclk / u32::from(ppre1); + + // This ensures, that no panic happens, when + // pclk1 is not manually set. + // As hclk highest value is 72.MHz() + // dividing by 2 should always be sufficient + if self.pclk1.is_none() && pclk1 > 36_000_000 { + ppre1_bits = cfgr::PPRE1_A::Div2; + ppre1 = 2; + pclk1 = hclk / u32::from(ppre1); + } + + crate::assert!(pclk1 <= 36_000_000); + + let (ppre2_bits, ppre2) = + self.pclk2 + .map_or((cfgr::PPRE2_A::Div1, 1), |pclk2| match hclk / pclk2 { + 0 => crate::unreachable!(), + 1 => (cfgr::PPRE2_A::Div1, 1), + 2 => (cfgr::PPRE2_A::Div2, 2), + 3..=5 => (cfgr::PPRE2_A::Div4, 4), + 6..=11 => (cfgr::PPRE2_A::Div8, 8), + _ => (cfgr::PPRE2_A::Div16, 16), + }); + + let pclk2 = hclk / u32::from(ppre2); + + crate::assert!(pclk2 <= 72_000_000); + + // Adjust flash wait states according to the + // HCLK frequency (cpu core clock) + acr.acr().modify(|_, w| { + if hclk <= 24_000_000 { + w.latency().ws0() + } else if hclk <= 48_000_000 { + w.latency().ws1() + } else { + w.latency().ws2() + } + }); + + let (usbpre, usbclk_valid) = usb_clocking::is_valid(sysclk, self.hse, pclk1, &pll_config); + + let rcc = unsafe { &*RCC::ptr() }; + + // enable HSE and wait for it to be ready + if self.hse.is_some() { + rcc.cr.modify(|_, w| { + w.hsebyp().bit(self.hse_bypass); + w.csson().bit(self.css); + w.hseon().on() + }); + + while rcc.cr.read().hserdy().is_not_ready() {} + } + + // enable PLL and wait for it to be ready + if let Some(pll_config) = pll_config { + rcc.cfgr.modify(|_, w| { + w.pllmul() + .variant(pll_config.mul) + .pllsrc() + .variant(pll_config.src) + }); + + if let Some(pll_div) = pll_config.div { + rcc.cfgr2.modify(|_, w| w.prediv().variant(pll_div)); + }; + + rcc.cr.modify(|_, w| w.pllon().on()); + + while rcc.cr.read().pllrdy().is_not_ready() {} + }; + + // set prescalers and clock source + rcc.cfgr.modify(|_, w| { + usb_clocking::set_usbpre(w, usbpre); + + w.ppre2() + .variant(ppre2_bits) + .ppre1() + .variant(ppre1_bits) + .hpre() + .variant(hpre_bits) + .sw() + .variant(sysclk_source) + }); + + Clocks { + hclk: hclk.Hz(), + pclk1: pclk1.Hz(), + pclk2: pclk2.Hz(), + ppre1, + ppre2, + sysclk: sysclk.Hz(), + usbclk_valid, + pll_bypass: self.pll_bypass, + } + } +} + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no longer be changed. +/// This struct can be obtained via the [freeze](CFGR::freeze) method of the [CFGR](CFGR) struct. +#[derive(Debug, Clone, Copy)] +pub struct Clocks { + hclk: Hertz, + pclk1: Hertz, + pclk2: Hertz, + ppre1: u8, + ppre2: u8, + sysclk: Hertz, + usbclk_valid: bool, + pll_bypass: bool, +} + +// TODO(Sh3Rm4n) Add defmt support for embedded-time! +#[cfg(feature = "defmt")] +impl defmt::Format for Clocks { + fn format(&self, f: defmt::Formatter) { + // Format as hexadecimal. + defmt::write!( + f, + "Clocks {{ hclk: {} Hz, pclk1: {} Hz, pclk2: {} Hz, ppre1: {:b}, ppre2: {:b}, sysclk: {} Hz, usbclk_valid: {}, pll_bypass: {} }}", + self.hclk.integer(), + self.pclk1.integer(), + self.pclk2.integer(), + self.ppre1, + self.ppre2, + self.sysclk.integer(), + self.usbclk_valid, + self.pll_bypass, + ); + } +} + +// TODO(Sh3Rm4n): Think of some way to generlize APB1 and APB2 as types to then implement a method, +// with which the ppre or pclk can be obtained by passing in the type of APB. +// With that in place, some places of macro magic are not needed anymore. +impl Clocks { + /// Returns the frequency of the AHB + pub fn hclk(&self) -> Hertz { + self.hclk + } + + /// Returns the frequency of the APB1 + pub fn pclk1(&self) -> Hertz { + self.pclk1 + } + + /// Returns the frequency of the APB2 + pub fn pclk2(&self) -> Hertz { + self.pclk2 + } + + /// Returns the prescaler of the APB1 + pub fn ppre1(&self) -> u8 { + self.ppre1 + } + + /// Returns the prescaler of the APB2 + pub fn ppre2(&self) -> u8 { + self.ppre2 + } + + /// Returns the system (core) frequency + pub fn sysclk(&self) -> Hertz { + self.sysclk + } + + /// Returns the PLL clock if configured, else it returns `None`. + /// + /// The PLL clock is a source of the system clock, but it is not necessarily configured to be one. + pub fn pllclk(&self) -> Option { + if self.pll_bypass { + None + } else { + // The PLLCLK is the same as the sysclk, beccause + // the sysclk is using it as a source. + Some(self.sysclk()) + } + } + + /// Returns whether the USBCLK clock frequency is valid for the USB peripheral + /// + /// If the microcontroller does support USB, 48 Mhz or 72 Mhz have to be used + /// and the [`CFGR::use_hse`] must be set. + /// + /// The APB1 / [`CFGR::pclk1`] clock must have a minimum frequency of 10 MHz to avoid data + /// overrun/underrun problems. [RM0316 32.5.2][RM0316] + /// + /// [RM0316]: https://www.st.com/resource/en/reference_manual/dm00043574.pdf + pub fn usbclk_valid(&self) -> bool { + self.usbclk_valid + } +} diff --git a/src/rcc/f7/enable.rs b/src/rcc/f7/enable.rs new file mode 100644 index 00000000..dc9e4c5d --- /dev/null +++ b/src/rcc/f7/enable.rs @@ -0,0 +1,211 @@ +use super::*; + +macro_rules! bus_enable { + ($PER:ident => $en:ident) => { + impl Enable for crate::pac::$PER { + #[inline(always)] + fn enable(bus: &mut Self::Bus) { + bus.enr().modify(|_, w| w.$en().set_bit()); + // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + cortex_m::asm::dsb(); + } + #[inline(always)] + fn disable(bus: &mut Self::Bus) { + bus.enr().modify(|_, w| w.$en().clear_bit()); + } + #[inline(always)] + fn is_enabled() -> bool { + Self::Bus::new().enr().read().$en().bit_is_set() + } + #[inline(always)] + unsafe fn enable_unchecked() { + Self::enable(&mut Self::Bus::new()); + } + #[inline(always)] + unsafe fn disable_unchecked() { + Self::disable(&mut Self::Bus::new()); + } + } + }; +} + +macro_rules! bus_lpenable { + ($PER:ident => $lpen:ident) => { + impl LPEnable for crate::pac::$PER { + #[inline(always)] + fn low_power_enable(bus: &mut Self::Bus) { + bus.lpenr().modify(|_, w| w.$lpen().set_bit()); + // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + cortex_m::asm::dsb(); + } + #[inline(always)] + fn low_power_disable(bus: &mut Self::Bus) { + bus.lpenr().modify(|_, w| w.$lpen().clear_bit()); + } + #[inline(always)] + fn is_low_power_enabled() -> bool { + Self::Bus::new().lpenr().read().$lpen().bit_is_set() + } + #[inline(always)] + unsafe fn low_power_enable_unchecked() { + Self::enable(&mut Self::Bus::new()); + } + #[inline(always)] + unsafe fn low_power_disable_unchecked() { + Self::disable(&mut Self::Bus::new()); + } + } + }; +} +macro_rules! bus_reset { + ($PER:ident => $rst:ident) => { + impl Reset for crate::pac::$PER { + #[inline(always)] + fn reset(bus: &mut Self::Bus) { + bus.rstr().modify(|_, w| w.$rst().set_bit()); + bus.rstr().modify(|_, w| w.$rst().clear_bit()); + } + #[inline(always)] + unsafe fn reset_unchecked() { + Self::reset(&mut Self::Bus::new()); + } + } + }; +} + +macro_rules! bus { + ($($PER:ident => ($busX:ty, $($en:ident)?, $($lpen:ident)?, $($rst:ident)?),)+) => { + $( + impl crate::Sealed for crate::pac::$PER {} + impl RccBus for crate::pac::$PER { + type Bus = $busX; + } + $(bus_enable!($PER => $en);)? + $(bus_lpenable!($PER => $lpen);)? + $(bus_reset!($PER => $rst);)? + )+ + }; +} + +// Peripherals respective buses +// TODO: check which processor has which peripheral and add them +bus! { + GPIOA => (AHB1, gpioaen, gpioalpen, gpioarst), // 0 + GPIOB => (AHB1, gpioben, gpioblpen, gpiobrst), // 1 + GPIOC => (AHB1, gpiocen, gpioclpen, gpiocrst), // 2 + GPIOD => (AHB1, gpioden, gpiodlpen, gpiodrst), // 3 + GPIOE => (AHB1, gpioeen, gpioelpen, gpioerst), // 4 + GPIOF => (AHB1, gpiofen, gpioflpen, gpiofrst), // 5 + GPIOG => (AHB1, gpiogen, gpioglpen, gpiogrst), // 6 + GPIOH => (AHB1, gpiohen, gpiohlpen, gpiohrst), // 7 + GPIOI => (AHB1, gpioien, gpioilpen, gpioirst), // 8 + CRC => (AHB1, crcen, crclpen, crcrst), // 12 + DMA1 => (AHB1, dma1en, dma1lpen, dma1rst), // 21 + DMA2 => (AHB1, dma2en, dma2lpen, dma2rst), // 22 + OTG_HS_GLOBAL => (AHB1, otghsen, otghslpen, otghsrst), // 29 + + RNG => (AHB2, rngen, rnglpen, rngrst), // 6 + OTG_FS_GLOBAL => (AHB2, otgfsen, otgfslpen, otgfsrst), // 7 + + FMC => (AHB3, fmcen, fmclpen, fmcrst), // 0 + QUADSPI => (AHB3, qspien, qspilpen, qspirst), // 1 + + TIM2 => (APB1, tim2en, tim2lpen, tim2rst), // 0 + TIM3 => (APB1, tim3en, tim3lpen, tim3rst), // 1 + TIM4 => (APB1, tim4en, tim4lpen, tim4rst), // 2 + TIM5 => (APB1, tim5en, tim5lpen, tim5rst), // 3 + TIM6 => (APB1, tim6en, tim6lpen, tim6rst), // 4 + TIM7 => (APB1, tim7en, tim7lpen, tim7rst), // 5 + TIM12 => (APB1, tim12en, tim12lpen, tim12rst), // 6 + TIM13 => (APB1, tim13en, tim13lpen, tim13rst), // 7 + TIM14 => (APB1, tim14en, tim14lpen, tim14rst), // 8 + LPTIM1 => (APB1, lptim1en, lptim1lpen, lptim1rst), // 9 + WWDG => (APB1, wwdgen, wwdglpen, wwdgrst), // 11 + SPI2 => (APB1, spi2en, spi2lpen, spi2rst), // 14 + SPI3 => (APB1, spi3en, spi3lpen, spi3rst), // 15 + USART2 => (APB1, usart2en, usart2lpen, usart2rst), // 17 + USART3 => (APB1, usart3en, usart3lpen, usart3rst), // 18 + UART4 => (APB1, uart4en, uart4lpen, uart4rst), // 19 + UART5 => (APB1, uart5en, uart5lpen, uart5rst), // 20 + I2C1 => (APB1, i2c1en, i2c1lpen, i2c1rst), // 21 + I2C2 => (APB1, i2c2en, i2c2lpen, i2c2rst), // 22 + I2C3 => (APB1, i2c3en, i2c3lpen, i2c3rst), // 23 + CAN1 => (APB1, can1en, can1lpen, can1rst), // 25 + PWR => (APB1, pwren, pwrlpen, pwrrst), // 28 + DAC => (APB1, dacen, daclpen, dacrst), // 29 + UART7 => (APB1, uart7en, uart7lpen, uart7rst), // 30 + UART8 => (APB1, uart8en, uart8lpen, uart8rst), // 31 + + TIM1 => (APB2, tim1en, tim1lpen, tim1rst), // 0 + TIM8 => (APB2, tim8en, tim8lpen, tim8rst), // 1 + USART1 => (APB2, usart1en, usart1lpen, usart1rst), // 4 + USART6 => (APB2, usart6en, usart6lpen, usart6rst), // 5 + ADC1 => (APB2, adc1en, adc1lpen, adcrst), // 8 + ADC2 => (APB2, adc2en, adc2lpen, adcrst), // 9 + ADC3 => (APB2, adc3en, adc3lpen, adcrst), // 10 + SDMMC1 => (APB2, sdmmc1en, sdmmc1lpen, sdmmc1rst), // 11 + SPI1 => (APB2, spi1en, spi1lpen, spi1rst), // 12 + SPI4 => (APB2, spi4en, spi4lpen, spi4rst), // 13 + SYSCFG => (APB2, syscfgen, syscfglpen, syscfgrst), // 14 + TIM9 => (APB2, tim9en, tim9lpen, tim9rst), // 16 + TIM10 => (APB2, tim10en, tim10lpen, tim10rst), // 17 + TIM11 => (APB2, tim11en, tim11lpen, tim11rst), // 18 + SPI5 => (APB2, spi5en, spi5lpen, spi5rst), // 20 + SAI1 => (APB2, sai1en, sai1lpen, sai1rst), // 22 + SAI2 => (APB2, sai2en, sai2lpen, sai2rst), // 23 +} + +#[cfg(any(feature = "svd-f730", feature = "svd-f7x2", feature = "svd-f7x3",))] +bus! { + AES => (AHB2, aesen, aeslpen, aesrst), // 4 + + SDMMC2 => (APB2, sdmmc2en, sdmmc2lpen, sdmmc2rst), // 7 + USBPHYC => (APB2, usbphycen,, usbphycrst), // 31 +} + +#[cfg(any( + feature = "svd-f745", + //feature = "svd-f750", + feature = "svd-f7x6", + feature = "svd-f765", + feature = "svd-f7x7", + feature = "svd-f7x9", +))] +bus! { + GPIOJ => (AHB1, gpiojen, gpiojlpen, gpiojrst), // 9 + GPIOK => (AHB1, gpioken, gpioklpen, gpiokrst), // 10 + DMA2D => (AHB1, dma2den, dma2dlpen, dma2drst), // 23 + ETHERNET_MAC => (AHB1, ethmacen, ethmaclpen, ethmacrst), // 25 + + DCMI => (AHB2, dcmien, dcmilpen, dcmirst), // 0 + CRYP => (AHB2, crypen, cryplpen, cryprst), // 4 + HASH => (AHB2, hashen, hashlpen,), // 5 + + SPDIFRX => (APB1, spdifrxen, spdifrxlpen, spdifrxrst), // 16 + I2C4 => (APB1, i2c4en, i2c4lpen, i2c4rst), // 24 + CAN2 => (APB1, can2en, can2lpen, can2rst), // 26 + CEC => (APB1, cecen, ceclpen, cecrst), // 27 + + SPI6 => (APB2, spi6en, spi6lpen, spi6rst), // 21 + LTDC => (APB2, ltdcen, ltdclpen, ltdcrst), // 26 +} + +#[cfg(any(feature = "svd-f765", feature = "svd-f7x7", feature = "svd-f7x9"))] +bus! { + JPEG => (AHB2, jpegen, jpeglpen,), // 1 + + CAN3 => (APB1, can3en, can3lpen, can3rst), // 13 + + DSI => (APB2, dsien, dsilpen, dsirst), // 27 + MDIOS => (APB2, mdioen, mdiolpen, mdiorst), // 30 +} + +#[cfg(any(feature = "svd-f7x9", feature = "svd-f7x9"))] +bus! { + DFSDM => (APB2, dfsdm1en, dfsdm1lpen, dfsdm1rst), // 29 +} + +#[cfg(feature = "svd-f765")] +bus! { + DFSDM1 => (APB2, dfsdm1en, dfsdm1lpen, dfsdm1rst), // 29 +} diff --git a/src/rcc/f7/mod.rs b/src/rcc/f7/mod.rs new file mode 100644 index 00000000..7346f285 --- /dev/null +++ b/src/rcc/f7/mod.rs @@ -0,0 +1,1678 @@ +//! Reset and clock control. + +use core::cmp::min; + +mod enable; + +use super::{BusClock, BusTimerClock, RccBus}; + +#[cfg_attr(test, allow(unused_imports))] +use micromath::F32Ext; + +use crate::pac::{rcc, FLASH, PWR, RCC}; +use fugit::{HertzU32 as Hertz, RateExtU32}; + +/// Typical output frequency of the HSI oscillator. +const HSI_FREQUENCY: Hertz = Hertz::from_raw(16_000_000); + +/// Extension trait that constrains the `RCC` peripheral +pub trait RccExt { + /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions + fn constrain(self) -> Rcc; +} + +impl RccExt for RCC { + fn constrain(self) -> Rcc { + Rcc { + ahb1: AHB1::new(), + ahb2: AHB2::new(), + ahb3: AHB3::new(), + apb1: APB1::new(), + apb2: APB2::new(), + bdcr: BDCR::new(), + cfgr: CFGR { + hse: None, + hse_bypass: false, + hclk: None, + sysclk: None, + pclk1: None, + pclk2: None, + lse: None, + lsi: None, + use_pll: false, + pll48clk: None, + pllm: 2, + plln: 50, + pllp: PLLP::Div2, + pllq: 2, + use_pllsai: false, + pllsain: 192, + pllsaip: PLLSAIP::Div2, + pllsaiq: 2, + use_plli2s: false, + plli2sr: 2, + plli2sq: 2, + plli2sn: 192, + mco1: MCO1::Hsi, + mco1pre: MCOPRE::Div1_no_div, + mco2: MCO2::Sysclk, + mco2pre: MCOPRE::Div1_no_div, + }, + } + } +} + +/// Constrained RCC peripheral +pub struct Rcc { + /// Advanced High-Performance Bus 1 (AHB1) registers + pub ahb1: AHB1, + /// Advanced High-Performance Bus 2 (AHB2) registers + pub ahb2: AHB2, + /// Advanced High-Performance Bus 3 (AHB3) registers + pub ahb3: AHB3, + + /// Advanced Peripheral Bus 1 (APB1) registers + pub apb1: APB1, + /// Advanced Peripheral Bus 2 (APB2) registers + pub apb2: APB2, + /// RCC Backup Domain + pub bdcr: BDCR, + pub cfgr: CFGR, +} + +macro_rules! bus_struct { + ($($busX:ident => ($EN:ident, $en:ident, $LPEN:ident, $lpen:ident, $RST:ident, $rst:ident, $doc:literal),)+) => { + $( + #[doc = $doc] + pub struct $busX { + _0: (), + } + + impl $busX { + pub(crate) fn new() -> Self { + Self { _0: () } + } + + pub(crate) fn enr(&self) -> &rcc::$EN { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { (*RCC::ptr()).$en() } + } + + pub(crate) fn lpenr(&self) -> &rcc::$LPEN { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { (*RCC::ptr()).$lpen() } + } + + pub(crate) fn rstr(&self) -> &rcc::$RST { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { (*RCC::ptr()).$rst() } + } + } + )+ + }; +} + +bus_struct! { + APB1 => (APB1ENR, apb1enr, APB1LPENR, apb1lpenr, APB1RSTR, apb1rstr, "Advanced Peripheral Bus 1 (APB1) registers"), + APB2 => (APB2ENR, apb2enr, APB2LPENR, apb2lpenr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"), + AHB1 => (AHB1ENR, ahb1enr, AHB1LPENR, ahb1lpenr, AHB1RSTR, ahb1rstr, "Advanced High-performance Bus 1 (AHB1) registers"), + AHB2 => (AHB2ENR, ahb2enr, AHB2LPENR, ahb2lpenr, AHB2RSTR, ahb2rstr, "Advanced High-performance Bus 2 (AHB2) registers"), + AHB3 => (AHB3ENR, ahb3enr, AHB3LPENR, ahb3lpenr, AHB3RSTR, ahb3rstr, "Advanced High-performance Bus 3 (AHB3) registers"), +} + +/// Backup Domain Control register (RCC_BDCR) +pub struct BDCR { + _0: (), +} + +impl BDCR { + pub(crate) fn new() -> Self { + Self { _0: () } + } +} + +/*impl HSEClock { + /// Provide HSE frequency. + /// + /// # Panics + /// + /// Panics if the frequency is outside the valid range. The frequency must be between + /// 4 MHz and 26 MHz in oscillator mode and between 1 MHz and 50 MHz in bypass mode. + pub fn new(freq: Hertz, mode: HSEClockMode) -> Self { + let valid_range = match mode { + // Source: Datasheet DS12536 Rev 2, Table 38 + HSEClockMode::Oscillator => Hertz::MHz(4)..=Hertz::MHz(26), + // Source: Datasheet DS12536 Rev 2, Table 40 + HSEClockMode::Bypass => Hertz::MHz(1)..=Hertz::MHz(50), + }; + assert!(valid_range.contains(&freq)); + + HSEClock { freq, mode } + } +}*/ + +/// LSE clock mode. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum LSEClockMode { + /// Enable LSE oscillator to use external crystal or ceramic resonator. + Oscillator, + /// Bypass LSE oscillator to use external clock source. + /// Use this if an external oscillator is used which is not connected to `OSC32_IN` such as a MEMS resonator. + Bypass, +} + +/// LSE Clock. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct LSEClock { + /// Input frequency. + freq: Hertz, + /// Mode. + mode: LSEClockMode, +} + +impl LSEClock { + /// Provide LSE frequency. + pub fn new(mode: LSEClockMode) -> Self { + // Sets the LSE clock source to 32.768 kHz. + LSEClock { + freq: 32_768.Hz(), + mode, + } + } +} + +/// PLL P division factors. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PLLP { + Div2 = 0b00, + Div4 = 0b01, + Div6 = 0b10, + Div8 = 0b11, +} + +/// MCO prescaler +/// +/// Value on reset: No division +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MCOPRE { + /// No division + Div1_no_div, + /// Division by 2 + Div2, + /// Division by 3 + Div3, + /// Division by 4 + Div4, + /// Division by 5 + Div5, +} + +/// PLL48CLK clock source selection +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PLL48CLK { + /// 48 MHz clock from PLLQ is selected + Pllq, + /// 48 MHz clock from PLLSAI is selected + Pllsai, +} + +/// PLLSAIP division factors. +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PLLSAIP { + Div2 = 0b00, + Div4 = 0b01, + Div6 = 0b10, + Div8 = 0b11, +} + +/// Microcontroller clock output 1 +/// +/// Value on reset: HSI +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MCO1 { + /// HSI clock selected + Hsi, + /// LSE oscillator selected + Lse, + /// HSE oscillator clock selected + Hse, + /// PLL clock selected + Pll, +} + +/// Microcontroller clock output 2 +/// +/// Value on reset: SYSCLK +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MCO2 { + /// System clock (SYSCLK) selected + Sysclk, + /// PLLI2S clock selected + Plli2s, + /// HSE oscillator clock selected + Hse, + /// PLL clock selected + Pll, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +enum VOSscale { + PwrScale1, + PwrScale2, + PwrScale3, +} + +impl Default for VOSscale { + fn default() -> Self { + VOSscale::PwrScale3 + } +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)] +struct InternalRCCConfig { + hpre: u8, + ppre1: u8, + ppre2: u8, + flash_waitstates: u8, + overdrive: bool, + vos_scale: VOSscale, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq, Default)] +struct FreqRequest { + p: Option<(u32, u32)>, + q: Option<(u32, u32)>, +} + +/// Clock configuration register. +#[derive(Debug, PartialEq, Eq)] +pub struct CFGR { + hse: Option, + hse_bypass: bool, + hclk: Option, + sysclk: Option, + pclk1: Option, + pclk2: Option, + lse: Option, + lsi: Option, + use_pll: bool, + pll48clk: Option, + pllm: u8, + plln: u16, + pllp: PLLP, + pllq: u8, + use_pllsai: bool, + pllsain: u16, + pllsaip: PLLSAIP, + pllsaiq: u8, + use_plli2s: bool, + plli2sr: u8, + plli2sq: u8, + plli2sn: u16, + mco1: MCO1, + mco1pre: MCOPRE, + mco2: MCO2, + mco2pre: MCOPRE, +} + +impl CFGR { + /// Configures the HSE oscillator. + pub fn use_hse(mut self, hse: Hertz) -> Self { + self.hse = Some(hse.raw()); + self + } + + /// Sets HCLK frequency. + /// + /// The HCLK is used for the AHB bus, core, memory and DMA. + /// + /// # Panics + /// + /// Panics if the frequency is larger than 216 MHz. + pub fn hclk(mut self, freq: Hertz) -> Self { + assert!(freq.raw() <= 216_000_000); + + self.hclk = Some(freq.raw()); + self + } + + /// Sets the SYSCLK frequency. + /// + /// This sets the SYSCLK frequency and sets up the USB clock if defined. + /// The provided frequency must be between 12.5 Mhz and 216 Mhz. + /// 12.5 Mhz is the VCO minimum frequency and SYSCLK PLLP divider limitation. + /// If the ethernet peripheral is on, the user should set a frequency higher than 25 Mhz. + /// + /// # Panics + /// + /// Panics if the frequency is not between 12.5 MHz and 216 MHz. + pub fn sysclk(mut self, sysclk: Hertz) -> Self { + assert!((12_500_000..=216_000_000).contains(&sysclk.raw())); + + self.sysclk = Some(sysclk.raw()); + self + } + + /// Sets the PCLK1 clock (APB1 clock). + /// + /// If this method isn't called the maximum allowed frequency is used for PCLK1. + /// + /// # Panics + /// + /// Panics if the frequency is not between 12.5 MHz and 54 MHz. + pub fn pclk1(mut self, freq: Hertz) -> Self { + assert!((12_500_000..=54_000_000).contains(&freq.raw())); + + self.pclk1 = Some(freq.raw()); + self + } + + /// Sets PCLK2 clock (APB2 clock). + /// + /// If this method isn't called the maximum allowed frequency is used for PCLK2. + /// + /// # Panics + /// + /// Panics if the frequency is not between 12.5 MHz and 108 MHz. + pub fn pclk2(mut self, freq: Hertz) -> Self { + assert!((12_500_000..=108_000_000).contains(&freq.raw())); + + self.pclk2 = Some(freq.raw()); + self + } + + /// Sets the LSE clock source to 32.768 kHz. + pub fn lse(mut self, lse: LSEClock) -> Self { + self.lse = Some(lse); + self + } + + /// Sets the LSI clock source to 32 kHz. + /// + /// Be aware that the tolerance is up to ±47% (Min 17 kHz, Typ 32 kHz, Max 47 kHz). + pub fn lsi(mut self) -> Self { + self.lsi = Some(32.kHz()); + self + } + + /// Sets the SYSCLK clock source to the main PLL. + /// + /// Note: `sysclk` must be specified or `use_pll48clk` must be set to true, otherwise `use_pll` is reset to false. + pub fn use_pll(mut self) -> Self { + self.use_pll = true; + self + } + + /// Sets the 48 MHz clock source. + pub fn use_pll48clk(mut self, pll48clk: PLL48CLK) -> Self { + self.pll48clk = Some(pll48clk); + self + } + + /// Sets the common PLL division factor. + /// + /// # Panics + /// + /// Panics if the division factor isn't between 2 and 63. + pub fn pllm(mut self, pllm: u8) -> Self { + assert!((2..=63).contains(&pllm)); + self.pllm = pllm; + self + } + + /// Sets the PLL multiplication factor for the main PLL. + /// + /// # Panics + /// + /// Panics if the multiplication factor isn't between 50 and 432 (inclusive). + pub fn plln(mut self, plln: u16) -> Self { + assert!((50..=432).contains(&plln)); + self.plln = plln; + self + } + + /// Sets the PLL division factor for the main PLL. + pub fn pllp(mut self, pllp: PLLP) -> Self { + self.pllp = pllp; + self + } + + /// Sets the PLL division factor for the 48 MHz clock. + /// # Panics + /// + /// Panics if the division factor isn't between 2 and 15 (inclusive). + pub fn pllq(mut self, pllq: u8) -> Self { + assert!((2..=15).contains(&pllq)); + self.pllq = pllq; + self + } + + /// Enables the PLLSAI clock source. + pub fn use_pllsai(mut self) -> Self { + self.use_pllsai = true; + self + } + + /// Sets the PLLSAIN multiplication factor for PLLSAI. + /// + /// # Panics + /// + /// Panics if the multiplication factor isn't between 50 and 432. + pub fn pllsain(mut self, pllsain: u16) -> Self { + assert!((50..=432).contains(&pllsain)); + self.pllsain = pllsain; + self + } + + /// Sets the PLLSAIP division factor for PLLSAI. + pub fn pllsaip(mut self, pllsaip: PLLSAIP) -> Self { + self.pllsaip = pllsaip; + self + } + + /// Sets the PLLSAIQ division factor for PLLSAIS. + /// + /// # Panics + /// + /// Panics if the division factor isn't between 2 and 15. + pub fn pllsaiq(mut self, pllsaiq: u8) -> Self { + assert!((2..=15).contains(&pllsaiq)); + self.pllsaiq = pllsaiq; + self + } + + /// Enables the PLLI2S clock source. + pub fn use_plli2s(mut self) -> Self { + self.use_plli2s = true; + self + } + + /// Sets the PLLI2SN multiplication factor for PLLI2S. + /// + /// # Panics + /// + /// Panics if the multiplication factor isn't between 50 and 432. + pub fn plli2sn(mut self, plli2sn: u16) -> Self { + assert!((50..=432).contains(&plli2sn)); + self.plli2sn = plli2sn; + self + } + + /// Sets the PLLI2SQ division factor for PLLI2S. + /// + /// # Panics + /// + /// Panics if the division factor isn't between 2 and 15. + pub fn plli2sq(mut self, plli2sq: u8) -> Self { + assert!((2..=15).contains(&plli2sq)); + self.plli2sq = plli2sq; + self + } + + /// Sets the PLLI2SR division factor for PLLI2S. + /// + /// # Panics + /// + /// Panics if the division factor isn't between 2 and 7. + pub fn plli2sr(mut self, plli2sr: u8) -> Self { + assert!((2..=7).contains(&plli2sr)); + self.plli2sr = plli2sr; + self + } + + /// Sets the MCO1 source + pub fn mco1(mut self, mco1: MCO1) -> Self { + self.mco1 = mco1; + self + } + + /// Sets the MCO1 division factors + pub fn mco1pre(mut self, mco1pre: MCOPRE) -> Self { + self.mco1pre = mco1pre; + self + } + + /// Sets the MCO2 source + pub fn mco2(mut self, mco2: MCO2) -> Self { + self.mco2 = mco2; + self + } + + /// Sets the MCO2 division factors + pub fn mco2pre(mut self, mco2pre: MCOPRE) -> Self { + self.mco2pre = mco2pre; + self + } + // We want to avoid dividing u64 values, because the Cortex-M7 CPU doesn't + // have hardware instructions for that, and the software divide that LLVM + // gives us is a relatively large amount of code. + // + // To do this, we operate in a fixed-point domain, and do a multiply by 1/x + // instead of dividing by x. We can calculate those 1/x values in a u32, if + // the fixed-point decimal place is chosen to be close enough to the LSB. + // + // But we also need to be able to represent the largest numerator, so we + // need enough bits to the left of the virtual decimal point. + // + // All of the chunks of code that do this are structured like: + // + // base_clk * n / m / p + // + // and they all have the same base_clk and n ranges (n up to 432, base_clk + // up to 50MHz). So base*plln can be as high as 216_000_000_000, and to + // represent that we need 38 bits. + // + // (We could use just 37 bits in one of these cases, if we take into account + // that high values of base_clk preclude using high values of n. But the + // other case is checking the output, so we can't assume anything about the + // inputs there.) + // + // So use 26 bits on the right of the decimal place. + // + // Also note, we need to round the 1/x values, not truncate them. So we + // shift left by one more bit, add one, and shift right by one. + const FIXED_POINT_LSHIFT: u32 = 31; + const FIXED_POINT_RSHIFT: u32 = 30; + + // We also drop 4 bits from the base_clk so that it and the fractional part + // (above) can fit into 64 bits. The max base_clk*n value needs 38 bits; + // shifting this out means it can fit into 34, with 30 (above) for the + // fractions. + const BASE_CLK_SHIFT: u32 = 4; + + /// Output clock calculation + fn calculate_clocks(&self) -> (Clocks, InternalRCCConfig) { + let mut config = InternalRCCConfig::default(); + + let base_clk = u64::from(self.hse.unwrap_or(HSI_FREQUENCY.raw())) >> Self::BASE_CLK_SHIFT; + + let mut sysclk = base_clk << Self::BASE_CLK_SHIFT; + + let mut pll48clk_valid = false; + + if self.use_pll { + // These initial divisions have to operate on u32 values to avoid + // the software division. Fortunately our 26 bit choice for the + // decimal place, and the fact that these are 1/N, means we can + // fit them into 26 bits, so a u32 is fine. + let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1; + let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT) + / match self.pllp { + PLLP::Div2 => 2u32, + PLLP::Div4 => 4u32, + PLLP::Div6 => 6u32, + PLLP::Div8 => 8u32, + } + + 1) + >> 1; + sysclk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64) + >> Self::FIXED_POINT_RSHIFT) + * one_over_p as u64) + >> Self::FIXED_POINT_RSHIFT + << Self::BASE_CLK_SHIFT; + } + + // Check if pll48clk is valid + if let Some(pll48clk) = self.pll48clk { + match pll48clk { + PLL48CLK::Pllq => { + pll48clk_valid = { + let one_over_m = + ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1; + let one_over_q = + ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllq as u32) + 1) >> 1; + let pll48clk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64) + >> Self::FIXED_POINT_RSHIFT) + * one_over_q as u64) + >> Self::FIXED_POINT_RSHIFT + << Self::BASE_CLK_SHIFT; + (48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk) + } + } + PLL48CLK::Pllsai => { + pll48clk_valid = { + if self.use_pllsai { + // base_clk * pllsain has the same range as above + let one_over_m = + ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1; + let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT) + / match self.pllsaip { + PLLSAIP::Div2 => 2u32, + PLLSAIP::Div4 => 4u32, + PLLSAIP::Div6 => 6u32, + PLLSAIP::Div8 => 8u32, + } + + 1) + >> 1; + let pll48clk = + (((base_clk as u64 * self.pllsain as u64 * one_over_m as u64) + >> Self::FIXED_POINT_RSHIFT) + * one_over_p as u64) + >> Self::FIXED_POINT_RSHIFT + << Self::BASE_CLK_SHIFT; + (48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk) + } else { + false + } + } + } + } + } + + // SYSCLK, must be <= 216 Mhz. By default, HSI/HSE frequency is chosen + assert!(sysclk <= 216_000_000); + let sysclk = sysclk as u32; + + // HCLK. By default, SYSCLK frequency is chosen. Because of the method + // of clock multiplication and division, even if `sysclk` is set to be + // the same as `hclk`, it can be slightly inferior to `sysclk` after + // pllm, pllp... calculations + let mut hclk: u32 = min(sysclk, self.hclk.unwrap_or(sysclk)); + + // Configure HPRE. + let hpre_val: f32 = (sysclk as f32 / hclk as f32).ceil(); + + // The real value of hpre is computed to be as near as possible to the + // desired value, this leads to a quantization error + let (hpre_val, hpre): (f32, u8) = match hpre_val as u32 { + 0 => unreachable!(), + 1 => (1.0, 0b000), + 2 => (2.0, 0b1000), + 3..=5 => (4.0, 0b1001), + 6..=11 => (8.0, 0b1010), + 12..=39 => (16.0, 0b1011), + 40..=95 => (64.0, 0b1100), + 96..=191 => (128.0, 0b1101), + 192..=383 => (256.0, 0b1110), + _ => (512.0, 0b1111), + }; + config.hpre = hpre; + // update hclk with the real value + hclk = (sysclk as f32 / hpre_val).floor() as u32; + + // PCLK1 (APB1). Must be <= 54 Mhz. By default, min(hclk, 54Mhz) is + // chosen + // Add limits dependens on OD follows by DS Table 16. + let max_pclk1 = if sysclk <= 180_000_000 { + 45_000_000 + } else { + 54_000_000 + }; + let mut pclk1: u32 = min(max_pclk1, self.pclk1.unwrap_or(hclk)); + // PCLK2 (APB2). Must be <= 108 Mhz. By default, min(hclk, 108Mhz) is + // chosen + // Add limits dependens on OD follows by DS Table 16. + let max_pclk2 = if sysclk <= 180_000_000 { + 90_000_000 + } else { + 108_000_000 + }; + let mut pclk2: u32 = min(max_pclk2, self.pclk2.unwrap_or(hclk)); + + // Configure PPRE1 + let mut ppre1_val: u32 = (hclk as f32 / pclk1 as f32).ceil() as u32; + config.ppre1 = match ppre1_val { + 0 => unreachable!(), + 1 => { + ppre1_val = 1; + 0b000 + } + 2 => { + ppre1_val = 2; + 0b100 + } + 3..=6 => { + ppre1_val = 4; + 0b101 + } + 7..=12 => { + ppre1_val = 8; + 0b110 + } + _ => { + ppre1_val = 16; + 0b111 + } + }; + // update pclk1 with the real value + pclk1 = hclk / ppre1_val; + + // Configure PPRE2 + let mut ppre2_val: u32 = (hclk as f32 / pclk2 as f32).ceil() as u32; + config.ppre2 = match ppre2_val { + 0 => unreachable!(), + 1 => { + ppre2_val = 1; + 0b000 + } + 2 => { + ppre2_val = 2; + 0b100 + } + 3..=6 => { + ppre2_val = 4; + 0b101 + } + 7..=12 => { + ppre2_val = 8; + 0b110 + } + _ => { + ppre2_val = 16; + 0b111 + } + }; + // update pclk2 with the real value + pclk2 = hclk / ppre2_val; + + // Assumes TIMPRE bit of RCC_DCKCFGR1 is reset (0) + let timclk1 = if ppre1_val == 1 { pclk1 } else { 2 * pclk1 }; + let timclk2 = if ppre2_val == 1 { pclk2 } else { 2 * pclk2 }; + + // Adjust flash wait states + config.flash_waitstates = if sysclk <= 30_000_000 { + 0b0000 + } else if sysclk <= 60_000_000 { + 0b0001 + } else if sysclk <= 90_000_000 { + 0b0010 + } else if sysclk <= 120_000_000 { + 0b0011 + } else if sysclk <= 150_000_000 { + 0b0100 + } else if sysclk <= 180_000_000 { + 0b0101 + } else if sysclk <= 210_000_000 { + 0b0110 + } else { + 0b0111 + }; + // Adjust power state and overdrive mode + // Configure follows by RM 4.1.4 + // Values getted from DS Table 16. General operating conditions + config.vos_scale = if sysclk <= 144_000_000 { + VOSscale::PwrScale3 + } else if sysclk <= 168_000_000 { + VOSscale::PwrScale2 + } else { + VOSscale::PwrScale1 + }; + // For every frequency higher than 180 need to enable overdrive + // Follows by DS Table 16. + config.overdrive = sysclk > 180_000_000; + + let clocks = Clocks { + hclk: hclk.Hz(), + pclk1: pclk1.Hz(), + pclk2: pclk2.Hz(), + sysclk: sysclk.Hz(), + timclk1: timclk1.Hz(), + timclk2: timclk2.Hz(), + pll48clk_valid, + hse: self.hse.map(|hse| hse.Hz()), + lse: self.lse.map(|lse| lse.freq), + lsi: self.lsi, + }; + + (clocks, config) + } + + /// Calculate the PLL M, N, P and Q values from the provided clock and requested options. + fn calculate_mnpq( + f_pll_clock_input: u32, + freq_req: FreqRequest, + ) -> Option<(u32, u32, Option, Option)> { + let mut m = 2; + let mut n = 432; + let mut p = None; + let mut q = None; + + if freq_req.p.is_none() && freq_req.q.is_none() { + return None; + } + + loop { + if m > 63 { + return None; + } + let f_vco_input = f_pll_clock_input / m; + if f_vco_input < 1_000_000 { + return None; + } + if f_vco_input > 2_000_000 || n < 50 { + m += 1; + n = 432; + continue; + } + // See the comments around Self::FIXED_POINT_LSHIFT to see how this works. + let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1; + let f_vco_clock = (((f_pll_clock_input as u64 >> Self::BASE_CLK_SHIFT) + * n as u64 + * one_over_m as u64) + >> Self::FIXED_POINT_RSHIFT + << Self::BASE_CLK_SHIFT) as u32; + if f_vco_clock < 50_000_000 { + m += 1; + n = 432; + continue; + } + if f_vco_clock > 432_000_000 { + n -= 1; + continue; + } + + if let Some((p_freq_min, p_freq_max)) = freq_req.p { + let mut div = None; + for div_p in &[2, 4, 6, 8] { + let f_pll_clock_output = f_vco_clock / div_p; + if f_pll_clock_output >= p_freq_min && f_pll_clock_output <= p_freq_max { + div = Some(*div_p) + } + } + if div.is_some() { + p = div; + if freq_req.q.is_none() { + break; + } + } else { + n -= 1; + continue; + } + } + + if let Some((q_freq_min, q_freq_max)) = freq_req.q { + let mut div = None; + for div_q in 2..=15 { + let f_usb_clock_output = f_vco_clock / div_q; + if f_usb_clock_output >= q_freq_min && f_usb_clock_output <= q_freq_max { + div = Some(div_q) + } + } + if div.is_some() { + q = div; + break; + } else { + n -= 1; + continue; + } + } + } + + Some((m, n, p, q)) + } + + fn pll_configure(&mut self) { + let base_clk = self.hse.unwrap_or(HSI_FREQUENCY.raw()) >> Self::BASE_CLK_SHIFT; + + let sysclk = if let Some(clk) = self.sysclk { + clk + } else { + base_clk << Self::BASE_CLK_SHIFT + }; + + let p = if base_clk << Self::BASE_CLK_SHIFT == sysclk { + None + } else { + Some((sysclk - 1, sysclk + 1)) + }; + + let q = if let Some(PLL48CLK::Pllq) = self.pll48clk { + Some((48_000_000 - 120_000, 48_000_000 + 120_000)) + } else { + None + }; + + if p.is_none() && q.is_none() { + // We don't need PLL + self.use_pll = false; + return; + } + + // We check if (pllm, plln, pllp) allow to obtain the requested Sysclk, + // so that we don't have to calculate them + let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1; + let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT) + / match self.pllp { + PLLP::Div2 => 2u32, + PLLP::Div4 => 4u32, + PLLP::Div6 => 6u32, + PLLP::Div8 => 8u32, + } + + 1) + >> 1; + let p_ok = (sysclk as u64) + == (((base_clk as u64 * self.plln as u64 * one_over_m as u64) + >> Self::FIXED_POINT_RSHIFT) + * one_over_p as u64) + >> Self::FIXED_POINT_RSHIFT + << Self::BASE_CLK_SHIFT; + if p_ok && q.is_none() { + return; + } + + if let Some((m, n, p, q)) = + CFGR::calculate_mnpq(base_clk << Self::BASE_CLK_SHIFT, FreqRequest { p, q }) + { + self.pllm = m as u8; + self.plln = n as u16; + if let Some(p) = p { + self.use_pll = true; + self.pllp = match p { + 2 => PLLP::Div2, + 4 => PLLP::Div4, + 6 => PLLP::Div6, + 8 => PLLP::Div8, + _ => unreachable!(), + }; + } + if let Some(q) = q { + self.pllq = q as u8; + } + } else { + panic!("couldn't calculate {} from {}", sysclk, base_clk); + } + } + + /// Configures the default clock settings. + /// + /// Set SYSCLK as 216 Mhz and setup USB clock if defined. + pub fn set_defaults(self) -> Self { + self.sysclk(216.MHz()) + } + + /// Configure the "mandatory" clocks (`sysclk`, `hclk`, `pclk1` and `pclk2') + /// and return them via the `Clocks` struct. + /// + /// The user shouldn't call freeze more than once as the clocks parameters + /// cannot be changed after the clocks have started. + /// + /// The implementation makes the following choice: HSI is always chosen over + /// HSE except when HSE is provided. When HSE is provided, HSE is used + /// wherever it is possible. + pub fn freeze(mut self) -> Clocks { + let flash = unsafe { &(*FLASH::ptr()) }; + let rcc = unsafe { &(*RCC::ptr()) }; + let pwr = unsafe { &(*PWR::ptr()) }; + + self.pll_configure(); + + let (clocks, config) = self.calculate_clocks(); + + // Switch to fail-safe clock settings. + // This is useful when booting from a bootloader that alters clock tree configuration. + // Turn on HSI + rcc.cr().modify(|_, w| w.hsion().set_bit()); + while rcc.cr().read().hsirdy().bit_is_clear() {} + // Switch to HSI + rcc.cfgr().modify(|_, w| w.sw().hsi()); + + // Configure HSE if provided + if self.hse.is_some() { + // enable HSE and wait for it to be ready + rcc.cr().modify(|_, w| { + if self.hse_bypass { + w.hsebyp().bypassed(); + } + w.hseon().set_bit() + }); + while rcc.cr().read().hserdy().bit_is_clear() {} + } + + // Enable sequence follows by RM 4.1.4 Entering Overdrive mode. + if self.use_pll || self.pll48clk.is_some() { + // Disable PLL + // Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is + // recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as + // PLL clock source, and configuration of division factors M, N, P, and Q). + rcc.cr().modify(|_, w| w.pllon().off()); + + rcc.pllcfgr().modify(|_, w| unsafe { + w.pllm().bits(self.pllm); + w.plln().bits(self.plln); + w.pllp().bits(self.pllp as u8); + w.pllq().bits(self.pllq); + w.pllsrc().bit(self.hse.is_some()) + }); + + // Enable PWR domain and setup VOSscale and Overdrive options + rcc.apb1enr().modify(|_, w| w.pwren().set_bit()); + + pwr.cr1().modify(|_, w| match config.vos_scale { + VOSscale::PwrScale3 => w.vos().scale3(), + VOSscale::PwrScale2 => w.vos().scale2(), + VOSscale::PwrScale1 => w.vos().scale1(), + }); + + // Enable PLL + rcc.cr().modify(|_, w| w.pllon().on()); + + // Wait for PLL to stabilise + while rcc.cr().read().pllrdy().is_not_ready() {} + + //Over-drive + if config.overdrive { + // Entering Over-drive mode + //enable the Over-drive mode + pwr.cr1().modify(|_, w| w.oden().set_bit()); + + //wait for the ODRDY flag to be set + while !pwr.csr1().read().odrdy().bit_is_set() {} + + //switch the voltage regulator from Normal mode to Over-drive mode + pwr.cr1().modify(|_, w| w.odswen().set_bit()); + + //Wait for the ODSWRDY flag in the PWR_CSR1 to be set. + while !pwr.csr1().read().odswrdy().bit_is_set() {} + } + } + + // Configure LSE if provided + if self.lse.is_some() { + // Configure the LSE mode + match self.lse.as_ref().unwrap().mode { + LSEClockMode::Bypass => rcc.bdcr().modify(|_, w| w.lsebyp().bypassed()), + LSEClockMode::Oscillator => rcc.bdcr().modify(|_, w| w.lsebyp().not_bypassed()), + } + // Enable the LSE. + rcc.bdcr().modify(|_, w| w.lseon().on()); + while rcc.bdcr().read().lserdy().is_not_ready() {} + } + + if self.lsi.is_some() { + rcc.csr().modify(|_, w| w.lsion().on()); + while rcc.csr().read().lsirdy().is_not_ready() {} + } + + if self.use_pllsai { + let pllsain_freq = match self.hse { + Some(hse) => hse as u64 / self.pllm as u64 * self.pllsain as u64, + None => 16_000_000 / self.pllm as u64 * self.pllsain as u64, + }; + let pllsaip_freq = pllsain_freq + / match self.pllsaip { + PLLSAIP::Div2 => 2, + PLLSAIP::Div4 => 4, + PLLSAIP::Div6 => 6, + PLLSAIP::Div8 => 8, + }; + // let pllsaiq_freq = pllsain_freq / self.pllsaiq as u64; + + // The reference manual (RM0410 Rev 4, Page 212), says the following + // "Caution: The software has to set these bits correctly to ensure that the VCO output frequency is between 100 and 432 MHz.", + // but STM32CubeMX states 192 MHz as the minimum. SSo the stricter requirement was chosen. + assert!((192_000_000..=432_000_000).contains(&pllsain_freq)); + assert!(pllsaip_freq <= 48_000_000); + + rcc.pllsaicfgr().modify(|_, w| unsafe { + w.pllsain().bits(self.pllsain); + w.pllsaip().bits(self.pllsaip as u8); + w.pllsaiq().bits(self.pllsaiq) + }); + rcc.cr().modify(|_, w| w.pllsaion().on()); + } + + if let Some(pll48clk) = self.pll48clk { + match pll48clk { + PLL48CLK::Pllq => rcc.dckcfgr2().modify(|_, w| w.ck48msel().bit(false)), + PLL48CLK::Pllsai => rcc.dckcfgr2().modify(|_, w| w.ck48msel().bit(true)), + } + } + + if self.use_plli2s { + let plli2sn_freq = match self.hse { + Some(hse) => hse as u64 / self.pllm as u64 * self.plli2sn as u64, + None => 16_000_000 / self.pllm as u64 * self.plli2sn as u64, + }; + let plli2sr_freq = plli2sn_freq / self.plli2sr as u64; + let plli2sq_freq = plli2sn_freq / self.plli2sq as u64; + + assert!((192_000_000..=432_000_000).contains(&plli2sn_freq)); + assert!(plli2sr_freq <= 216_000_000); + assert!(plli2sq_freq <= 216_000_000); + + rcc.plli2scfgr().modify(|_, w| unsafe { + w.plli2sn().bits(self.plli2sn); + w.plli2sr().bits(self.plli2sr); + w.plli2sq().bits(self.plli2sq) + }); + rcc.cr().modify(|_, w| w.plli2son().on()); + } + + rcc.cfgr().modify(|_, w| { + w.mco1() + .variant(self.mco1.into()) + .mco1pre() + .variant(self.mco1pre.into()); + w.mco2() + .variant(self.mco2.into()) + .mco2pre() + .variant(self.mco2pre.into()) + }); + + flash + .acr() + .write(|w| w.latency().set(config.flash_waitstates)); + + // Configure HCLK, PCLK1, PCLK2 + rcc.cfgr().modify(|_, w| unsafe { + w.ppre1() + .bits(config.ppre1) + .ppre2() + .bits(config.ppre2) + .hpre() + .bits(config.hpre) + }); + + // Select SYSCLK source + if self.use_pll { + rcc.cfgr().modify(|_, w| w.sw().pll()); + while !rcc.cfgr().read().sws().is_pll() {} + } else if self.hse.is_some() { + rcc.cfgr().modify(|_, w| w.sw().hse()); + while !rcc.cfgr().read().sws().is_hse() {} + } else { + rcc.cfgr().modify(|_, w| w.sw().hsi()); + while !rcc.cfgr().read().sws().is_hsi() {} + } + + // As requested by user manual we need to wait 16 ticks before the right + // predivision is applied + cortex_m::asm::delay(16); + + clocks + } +} + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no longer be changed +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct Clocks { + hclk: Hertz, + pclk1: Hertz, + pclk2: Hertz, + sysclk: Hertz, + timclk1: Hertz, + timclk2: Hertz, + pll48clk_valid: bool, + hse: Option, + lse: Option, + lsi: Option, +} + +impl Clocks { + /// Returns the frequency of the AHB1 + pub fn hclk(&self) -> Hertz { + self.hclk + } + + /// Returns the frequency of the APB1 + pub fn pclk1(&self) -> Hertz { + self.pclk1 + } + + /// Returns the frequency of the APB2 + pub fn pclk2(&self) -> Hertz { + self.pclk2 + } + + /// Returns the system (core) frequency + pub fn sysclk(&self) -> Hertz { + self.sysclk + } + + /// Returns the frequency for timers on APB1 + pub fn timclk1(&self) -> Hertz { + self.timclk1 + } + + /// Returns the frequency for timers on APB1 + pub fn timclk2(&self) -> Hertz { + self.timclk2 + } + + /// Returns true if the PLL48 clock is within USB + /// specifications. It is required to use the USB functionality. + pub fn is_pll48clk_valid(&self) -> bool { + // USB specification allow +-0.25% + self.pll48clk_valid + } + + /// Returns the frequency of the `HSE` if `Some`, else `None`. + pub fn hse(&self) -> Option { + self.hse + } + + /// Returns the frequency of the `LSE` if `Some`, else `None`. + pub fn lse(&self) -> Option { + self.lse + } + + /// Returns the frequency of the `LSI` if `Some`, else `None`. + pub fn lsi(&self) -> Option { + self.lsi + } +} + +impl BusClock for AHB1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for AHB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for AHB3 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for APB1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk1 + } +} + +impl BusClock for APB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk2 + } +} + +impl BusTimerClock for APB1 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk1 + } +} + +impl BusTimerClock for APB2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk2 + } +} + +impl From for crate::pac::rcc::cfgr::MCO1 { + fn from(input: MCO1) -> Self { + match input { + MCO1::Hsi => Self::Hsi, + MCO1::Lse => Self::Lse, + MCO1::Hse => Self::Hse, + MCO1::Pll => Self::Pll, + } + } +} + +impl From for crate::pac::rcc::cfgr::MCO2 { + fn from(input: MCO2) -> Self { + match input { + MCO2::Sysclk => Self::Sysclk, + MCO2::Plli2s => Self::Plli2s, + MCO2::Hse => Self::Hse, + MCO2::Pll => Self::Pll, + } + } +} + +impl From for crate::pac::rcc::cfgr::MCO1PRE { + fn from(input: MCOPRE) -> Self { + match input { + MCOPRE::Div1_no_div => Self::Div1, + MCOPRE::Div2 => Self::Div2, + MCOPRE::Div3 => Self::Div3, + MCOPRE::Div4 => Self::Div4, + MCOPRE::Div5 => Self::Div5, + } + } +} + +/// Enable/disable peripheral +pub trait Enable: RccBus { + /// Enables peripheral + fn enable(bus: &mut Self::Bus); + + /// Disables peripheral + fn disable(bus: &mut Self::Bus); + + /// Check if peripheral enabled + fn is_enabled() -> bool; + + /// Check if peripheral disabled + fn is_disabled() -> bool { + !Self::is_enabled() + } + + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn enable_unchecked(); + + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn disable_unchecked(); +} + +/// Enable/disable peripheral in low power mode +pub trait LPEnable: RccBus { + /// Enables peripheral in low power mode + fn low_power_enable(bus: &mut Self::Bus); + + /// Disables peripheral in low power mode + fn low_power_disable(bus: &mut Self::Bus); + + /// Check if peripheral enabled in low power mode + fn is_low_power_enabled() -> bool; + + /// Check if peripheral disabled in low power mode + fn is_low_power_disabled() -> bool { + !Self::is_low_power_enabled() + } + + /// # Safety + /// + /// Enables peripheral in low power mode. Takes access to RCC internally + unsafe fn low_power_enable_unchecked(); + + /// # Safety + /// + /// Disables peripheral in low power mode. Takes access to RCC internally + unsafe fn low_power_disable_unchecked(); +} + +/// Reset peripheral +pub trait Reset: RccBus { + /// Resets peripheral + fn reset(bus: &mut Self::Bus); + + /// # Safety + /// + /// Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked(); +} + +#[cfg(test)] +mod tests { + use fugit::{HertzU32 as Hertz, RateExtU32}; + + use super::{FreqRequest, CFGR}; + + fn build_request(sysclk: u32, use_pll48clk: bool) -> FreqRequest { + let p = Some((sysclk - 1, sysclk + 1)); + let q = if use_pll48clk { + Some((48_000_000 - 120_000, 48_000_000 + 120_000)) + } else { + None + }; + FreqRequest { p, q } + } + + fn check(hse: u32, sysclk: u32, use_pll48clk: bool) { + let request = build_request(sysclk, use_pll48clk); + let (m, n, p, q) = + CFGR::calculate_mnpq(hse, request).expect("Can't calculate PLL parameters"); + + let pll_in = hse; + + if m < 2 || m > 63 { + panic!("Invalid PLL M value: {}", m); + } + + let vco_in = pll_in / m; + if vco_in < 1_000_000 || vco_in > 2_000_000 { + panic!("Invalid VCO input frequency: {}", vco_in); + } + + if n < 50 || n > 432 { + panic!("Invalid PLL N value: {}", n); + } + + let vco = ((pll_in as u64) * (n as u64) / (m as u64)) as u32; + if vco < 100_000_000 || vco > 432_000_000 { + panic!("Invalid VCO frequency: {}", vco); + } + + let p = p.expect("PLL P value should be defined!"); + if [2, 4, 6, 8].iter().find(|v| **v == p).is_none() { + panic!("Invalid PLL P value: {}", p); + } + + let p_freq = vco / p; + if p_freq > 216_000_000 { + panic!("Invalid PLL P frequency: {}", p_freq); + } + if p_freq < (sysclk - 1) || p_freq > (sysclk + 1) { + panic!( + "Invalid PLL P frequency: {} (requested sysclk {})", + p_freq, sysclk + ); + } + + if use_pll48clk && q.is_none() { + panic!("PLL Q value should be defined!"); + } + if let Some(q) = q { + if q < 2 || q > 15 { + panic!("Invalid PLL Q value: {}", q); + } + if use_pll48clk { + let q_freq = vco / q; + if q_freq < (48_000_000 - 120_000) || q_freq > (48_000_000 + 120_000) { + panic!("Invalid PLL Q frequency: {}", q_freq); + } + } + } + } + + #[test] + fn test_pll_calc1() { + check(25_000_000, 48_000_000, false); + } + + #[test] + fn test_pll_calc1_usb() { + check(25_000_000, 48_000_000, true); + } + + #[test] + fn test_pll_calc2() { + check(12_000_000, 48_000_000, false); + } + + #[test] + fn test_pll_calc2_usb() { + check(12_000_000, 48_000_000, true); + } + + #[test] + fn test_pll_calc3() { + check(12_000_000, 216_000_000, false); + } + + #[test] + fn test_pll_calc3_usb() { + check(12_000_000, 216_000_000, true); + } + + #[test] + fn test_rcc_calc1() { + use super::{HSEClock, HSEClockMode, MCO1, MCO2, MCOPRE, PLL48CLK, PLLP, PLLSAIP}; + + let cfgr = CFGR { + hse: None, + hse_bypass: false, + hclk: None, + sysclk: None, + pclk1: None, + pclk2: None, + lse: None, + lsi: None, + use_pll: false, + pll48clk: None, + pllm: 2, + plln: 50, + pllp: PLLP::Div2, + pllq: 2, + use_pllsai: false, + pllsain: 192, + pllsaip: PLLSAIP::Div2, + pllsaiq: 2, + use_plli2s: false, + plli2sr: 2, + plli2sq: 2, + plli2sn: 192, + mco1: MCO1::Hsi, + mco1pre: MCOPRE::Div1_no_div, + mco2: MCO2::Sysclk, + mco2pre: MCOPRE::Div1_no_div, + }; + + let mut cfgr = cfgr + .hse(HSEClock::new(25.MHz(), HSEClockMode::Bypass)) + .use_pll() + .use_pll48clk(PLL48CLK::Pllq) + .sysclk(216.MHz()); + cfgr.pll_configure(); + + assert_eq!(cfgr.hse.unwrap().freq, Hertz::MHz(25)); + + let (clocks, _config) = cfgr.calculate_clocks(); + assert_eq!(clocks.sysclk().raw(), 216_000_000); + assert!(clocks.is_pll48clk_valid()); + } + + #[test] + fn test_rcc_calc2() { + use super::{HSEClock, HSEClockMode, MCO1, MCO2, MCOPRE, PLL48CLK, PLLP, PLLSAIP}; + + let cfgr = CFGR { + hse: None, + hse_bypass: false, + hclk: None, + sysclk: None, + pclk1: None, + pclk2: None, + lse: None, + lsi: None, + use_pll: false, + pll48clk: None, + pllm: 2, + plln: 50, + pllp: PLLP::Div2, + pllq: 2, + use_pllsai: false, + pllsain: 192, + pllsaip: PLLSAIP::Div2, + pllsaiq: 2, + use_plli2s: false, + plli2sr: 2, + plli2sq: 2, + plli2sn: 192, + mco1: MCO1::Hsi, + mco1pre: MCOPRE::Div1_no_div, + mco2: MCO2::Sysclk, + mco2pre: MCOPRE::Div1_no_div, + }; + + let mut cfgr = cfgr + .hse(HSEClock::new(25.MHz(), HSEClockMode::Bypass)) + .use_pll48clk(PLL48CLK::Pllq) + .sysclk(216.MHz()); + cfgr.pll_configure(); + + assert_eq!(cfgr.hse.unwrap().freq, Hertz::MHz(25)); + + let (clocks, _config) = cfgr.calculate_clocks(); + assert_eq!(clocks.sysclk().raw(), 216_000_000); + assert!(clocks.is_pll48clk_valid()); + } + + #[test] + fn test_rcc_calc3() { + use super::{HSEClock, HSEClockMode, MCO1, MCO2, MCOPRE, PLL48CLK, PLLP, PLLSAIP}; + + let cfgr = CFGR { + hse: None, + hse_bypass: false, + hclk: None, + sysclk: None, + pclk1: None, + pclk2: None, + lse: None, + lsi: None, + use_pll: false, + pll48clk: None, + pllm: 2, + plln: 50, + pllp: PLLP::Div2, + pllq: 2, + use_pllsai: false, + pllsain: 192, + pllsaip: PLLSAIP::Div2, + pllsaiq: 2, + use_plli2s: false, + plli2sr: 2, + plli2sq: 2, + plli2sn: 192, + mco1: MCO1::Hsi, + mco1pre: MCOPRE::Div1_no_div, + mco2: MCO2::Sysclk, + mco2pre: MCOPRE::Div1_no_div, + }; + + let mut cfgr = cfgr + .hse(HSEClock::new(25.MHz(), HSEClockMode::Bypass)) + .use_pll48clk(PLL48CLK::Pllq) + .set_defaults(); + cfgr.pll_configure(); + + assert_eq!(cfgr.hse.unwrap().freq, Hertz::MHz(25)); + + let (clocks, _config) = cfgr.calculate_clocks(); + assert_eq!(clocks.sysclk().raw(), 216_000_000); + assert!(clocks.is_pll48clk_valid()); + } + + #[test] + fn test_rcc_default() { + use super::{MCO1, MCO2, MCOPRE, PLLP, PLLSAIP}; + + let mut cfgr = CFGR { + hse: None, + hse_bypass: false, + hclk: None, + sysclk: None, + pclk1: None, + pclk2: None, + lse: None, + lsi: None, + use_pll: false, + pll48clk: None, + pllm: 2, + plln: 50, + pllp: PLLP::Div2, + pllq: 2, + use_pllsai: false, + pllsain: 192, + pllsaip: PLLSAIP::Div2, + pllsaiq: 2, + use_plli2s: false, + plli2sr: 2, + plli2sq: 2, + plli2sn: 192, + mco1: MCO1::Hsi, + mco1pre: MCOPRE::Div1_no_div, + mco2: MCO2::Sysclk, + mco2pre: MCOPRE::Div1_no_div, + }; + + cfgr.pll_configure(); + assert!(!cfgr.use_pll); + let (clocks, _config) = cfgr.calculate_clocks(); + assert_eq!(clocks.sysclk().raw(), 16_000_000); + } +} diff --git a/src/rcc/g4/clockout.rs b/src/rcc/g4/clockout.rs new file mode 100644 index 00000000..8668d8f3 --- /dev/null +++ b/src/rcc/g4/clockout.rs @@ -0,0 +1,126 @@ +use crate::gpio::*; +use crate::pac::RCC; +use crate::rcc::*; + +pub type LscoPin = gpioa::PA2; + +pub struct Lsco { + pin: gpioa::PA2>, +} + +impl Lsco { + pub fn enable(&self) { + let rcc = unsafe { &(*RCC::ptr()) }; + rcc.bdcr.modify(|_, w| w.lscoen().set_bit()); + } + + pub fn disable(&self) { + let rcc = unsafe { &(*RCC::ptr()) }; + rcc.bdcr.modify(|_, w| w.lscoen().clear_bit()); + } + + pub fn release(self) -> LscoPin { + self.pin.into_floating_input() + } +} + +pub trait LSCOExt { + fn lsco(self, src: LSCOSrc, rcc: &mut Rcc) -> Lsco; +} + +impl LSCOExt for LscoPin { + fn lsco(self, src: LSCOSrc, rcc: &mut Rcc) -> Lsco { + let src_select_bit = match src { + LSCOSrc::LSE => { + rcc.enable_lse(false); + true + } + LSCOSrc::LSI => { + rcc.enable_lsi(); + false + } + }; + rcc.unlock_rtc(); + rcc.rb.bdcr.modify(|_, w| w.lscosel().bit(src_select_bit)); + Lsco { + pin: self.into_alternate(), + } + } +} + +pub struct Mco { + pin: PIN, + src_bits: u8, +} + +impl Mco { + pub fn enable(&self) { + let rcc = unsafe { &(*RCC::ptr()) }; + rcc.cfgr + .modify(|_, w| unsafe { w.mcosel().bits(self.src_bits) }); + } + + pub fn disable(&self) { + let rcc = unsafe { &(*RCC::ptr()) }; + rcc.cfgr.modify(|_, w| unsafe { w.mcosel().bits(0) }); + } + + pub fn release(self) -> PIN { + self.pin //TODO reverse pin to input + } +} + +pub trait MCOExt { + fn mco(self, src: MCOSrc, psc: Prescaler, rcc: &mut Rcc) -> Mco; +} + +macro_rules! mco { + ($($PIN:ident),+) => { + $( + impl MCOExt<$PIN>> for $PIN { + fn mco(self, src: MCOSrc, psc: Prescaler, rcc: &mut Rcc) -> Mco<$PIN>> { + let psc_bits = match psc { + Prescaler::NotDivided => 0b000, + Prescaler::Div2 => 0b001, + Prescaler::Div4 => 0b010, + Prescaler::Div8 => 0b011, + Prescaler::Div16 => 0b100, + Prescaler::Div32 => 0b101, + Prescaler::Div64 => 0b110, + _ => 0b111, + }; + rcc.rb.cfgr.modify(|r, w| unsafe { + w.bits((r.bits() & !(0b111 << 28)) | (psc_bits << 28)) + }); + + let src_bits = match src { + MCOSrc::SysClk => 0b001, + MCOSrc::HSI => { + rcc.enable_hsi(); + 0b011 + }, + MCOSrc::HSE => { + rcc.enable_hse(false); + 0b100 + }, + MCOSrc::PLL => 0b101, + MCOSrc::LSI => { + rcc.enable_lsi(); + 0b110 + }, + MCOSrc::LSE => { + rcc.enable_lse(false); + 0b111 + }, + }; + Mco { src_bits, pin: self.into_alternate() } + } + } + )+ + }; +} + +use crate::gpio::gpioa::PA8; +use crate::gpio::gpiog::PG10; + +mco!(PA8, PG10); diff --git a/src/rcc/g4/config.rs b/src/rcc/g4/config.rs new file mode 100644 index 00000000..1f54d923 --- /dev/null +++ b/src/rcc/g4/config.rs @@ -0,0 +1,386 @@ +use crate::time::Hertz; + +/// Prescaler +#[derive(Clone, Copy)] +pub enum Prescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div32, + Div64, + Div128, + Div256, + Div512, +} + +/// System clock mux source +pub enum SysClockSrc { + PLL, + HSI, + HSE(Hertz), +} + +/// Microcontroller clock output source +pub enum MCOSrc { + LSI, + PLL, + SysClk, + HSI, + HSE, + LSE, +} + +/// Low-speed clocks output source +pub enum LSCOSrc { + LSI, + LSE, +} + +/// PLL clock input source +#[derive(Clone, Copy)] +pub enum PLLSrc { + HSI, + HSE(Hertz), + HSE_BYPASS(Hertz), +} + +/// Divider for the PLL clock input (M) +/// This must be set based on the input clock to keep the PLL input frequency within the limits +/// specified in the datasheet. +#[derive(Clone, Copy)] +pub enum PllMDiv { + DIV_1 = 0, + DIV_2, + DIV_3, + DIV_4, + DIV_5, + DIV_6, + DIV_7, + DIV_8, + DIV_9, + DIV_10, + DIV_11, + DIV_12, + DIV_13, + DIV_14, + DIV_15, + DIV_16, +} + +impl PllMDiv { + pub fn divisor(&self) -> u32 { + (self.clone() as u32) + 1 + } + + pub fn register_setting(&self) -> u8 { + self.clone() as u8 + } +} + +/// Divider for the PLL Q Output +#[derive(Clone, Copy)] +pub enum PllQDiv { + DIV_2 = 0, + DIV_4, + DIV_6, + DIV_8, +} + +impl PllQDiv { + pub fn divisor(&self) -> u32 { + ((self.clone() as u32) + 1) * 2 + } + + pub fn register_setting(&self) -> u8 { + self.clone() as u8 + } +} + +/// Divider for the PLL R Output +#[derive(Clone, Copy)] +pub enum PllRDiv { + DIV_2 = 0, + DIV_4, + DIV_6, + DIV_8, +} + +impl PllRDiv { + pub fn divisor(&self) -> u32 { + ((self.clone() as u32) + 1) * 2 + } + + pub fn register_setting(&self) -> u8 { + self.clone() as u8 + } +} + +/// Divider for the PLL P Output +/// +/// Note: The P divider has a PLLP register that can be used to set the divider to either 7 or 17. +/// It is a complete mystery why anyone would want to do that instead of using the PLLPDIV register +/// so it's not supported. +#[derive(Clone, Copy)] +pub enum PllPDiv { + DIV_2 = 2, + DIV_3, + DIV_4, + DIV_5, + DIV_6, + DIV_7, + DIV_8, + DIV_9, + DIV_10, + DIV_11, + DIV_12, + DIV_13, + DIV_14, + DIV_15, + DIV_16, + DIV_17, + DIV_18, + DIV_19, + DIV_20, + DIV_21, + DIV_22, + DIV_23, + DIV_24, + DIV_25, + DIV_26, + DIV_27, + DIV_28, + DIV_29, + DIV_30, + DIV_31, +} + +impl PllPDiv { + pub fn divisor(&self) -> u32 { + self.clone() as u32 + } + + pub fn register_setting(&self) -> u8 { + self.clone() as u8 + } +} + +/// Main PLL multiplication factor for VCO +#[derive(Clone, Copy)] +pub enum PllNMul { + MUL_8 = 8, + MUL_9, + MUL_10, + MUL_11, + MUL_12, + MUL_13, + MUL_14, + MUL_15, + MUL_16, + MUL_17, + MUL_18, + MUL_19, + MUL_20, + MUL_21, + MUL_22, + MUL_23, + MUL_24, + MUL_25, + MUL_26, + MUL_27, + MUL_28, + MUL_29, + MUL_30, + MUL_31, + MUL_32, + MUL_33, + MUL_34, + MUL_35, + MUL_36, + MUL_37, + MUL_38, + MUL_39, + MUL_40, + MUL_41, + MUL_42, + MUL_43, + MUL_44, + MUL_45, + MUL_46, + MUL_47, + MUL_48, + MUL_49, + MUL_50, + MUL_51, + MUL_52, + MUL_53, + MUL_54, + MUL_55, + MUL_56, + MUL_57, + MUL_58, + MUL_59, + MUL_60, + MUL_61, + MUL_62, + MUL_63, + MUL_64, + MUL_65, + MUL_66, + MUL_67, + MUL_68, + MUL_69, + MUL_70, + MUL_71, + MUL_72, + MUL_73, + MUL_74, + MUL_75, + MUL_76, + MUL_77, + MUL_78, + MUL_79, + MUL_80, + MUL_81, + MUL_82, + MUL_83, + MUL_84, + MUL_85, + MUL_86, + MUL_87, + MUL_88, + MUL_89, + MUL_90, + MUL_91, + MUL_92, + MUL_93, + MUL_94, + MUL_95, + MUL_96, + MUL_97, + MUL_98, + MUL_99, + MUL_100, + MUL_101, + MUL_102, + MUL_103, + MUL_104, + MUL_105, + MUL_106, + MUL_107, + MUL_108, + MUL_109, + MUL_110, + MUL_111, + MUL_112, + MUL_113, + MUL_114, + MUL_115, + MUL_116, + MUL_117, + MUL_118, + MUL_119, + MUL_120, + MUL_121, + MUL_122, + MUL_123, + MUL_124, + MUL_125, + MUL_126, + MUL_127, +} + +impl PllNMul { + pub fn multiplier(&self) -> u32 { + self.clone() as u32 + } + + pub fn register_setting(&self) -> u8 { + self.clone() as u8 + } +} + +/// PLL config +#[derive(Clone, Copy)] +pub struct PllConfig { + pub mux: PLLSrc, + pub m: PllMDiv, + pub n: PllNMul, + pub r: Option, + pub q: Option, + pub p: Option, +} + +impl Default for PllConfig { + fn default() -> PllConfig { + PllConfig { + mux: PLLSrc::HSI, + m: PllMDiv::DIV_2, + n: PllNMul::MUL_8, + r: Some(PllRDiv::DIV_2), + q: None, + p: None, + } + } +} + +/// Clocks configutation +pub struct Config { + pub(crate) sys_mux: SysClockSrc, + pub(crate) pll_cfg: PllConfig, + pub(crate) ahb_psc: Prescaler, + pub(crate) apb1_psc: Prescaler, + pub(crate) apb2_psc: Prescaler, +} + +impl Config { + pub fn new(mux: SysClockSrc) -> Self { + Config::default().clock_src(mux) + } + + pub fn pll() -> Self { + Config::default().clock_src(SysClockSrc::PLL) + } + + pub fn hsi() -> Self { + Config::default().clock_src(SysClockSrc::HSI) + } + + pub fn clock_src(mut self, mux: SysClockSrc) -> Self { + self.sys_mux = mux; + self + } + + pub fn pll_cfg(mut self, cfg: PllConfig) -> Self { + self.pll_cfg = cfg; + self + } + + pub fn ahb_psc(mut self, psc: Prescaler) -> Self { + self.ahb_psc = psc; + self + } + + pub fn apb1_psc(mut self, psc: Prescaler) -> Self { + self.apb1_psc = psc; + self + } + + pub fn apb2_psc(mut self, psc: Prescaler) -> Self { + self.apb2_psc = psc; + self + } +} + +impl Default for Config { + fn default() -> Config { + Config { + sys_mux: SysClockSrc::HSI, + pll_cfg: PllConfig::default(), + ahb_psc: Prescaler::NotDivided, + apb1_psc: Prescaler::NotDivided, + apb2_psc: Prescaler::NotDivided, + } + } +} diff --git a/src/rcc/g4/enable.rs b/src/rcc/g4/enable.rs new file mode 100644 index 00000000..fb21c08c --- /dev/null +++ b/src/rcc/g4/enable.rs @@ -0,0 +1,209 @@ +use super::*; +use crate::bb; + +macro_rules! bus_enable { + ($PER:ident => ($busX:ty, $bit:literal)) => { + impl Enable for crate::pac::$PER { + #[inline(always)] + fn enable(rcc: &RccRB) { + unsafe { + bb::set(Self::Bus::enr(rcc), $bit); + } + // // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + // cortex_m::asm::dsb(); + } + #[inline(always)] + fn disable(rcc: &RccRB) { + unsafe { + bb::clear(Self::Bus::enr(rcc), $bit); + } + } + } + }; +} + +macro_rules! bus_reset { + ($PER:ident => ($busX:ty, $bit:literal)) => { + impl Reset for crate::pac::$PER { + #[inline(always)] + fn reset(rcc: &RccRB) { + unsafe { + bb::set(Self::Bus::rstr(rcc), $bit); + bb::clear(Self::Bus::rstr(rcc), $bit); + } + } + } + }; +} + +macro_rules! bus { + ($($PER:ident => ($busX:ty, $bit:literal),)+) => { + $( + impl crate::Sealed for crate::pac::$PER {} + impl RccBus for crate::pac::$PER { + type Bus = $busX; + } + impl crate::rcc::Instance for crate::pac::$PER {} + bus_enable!($PER => ($busX, $bit)); + bus_reset!($PER => ($busX, $bit)); + )+ + } +} + +bus! { + DMA1 => (AHB1, 0), + DMA2 => (AHB1, 1), + DMAMUX => (AHB1, 2), + CORDIC => (AHB1, 3), + FMAC => (AHB1, 4), + FLASH => (AHB1, 5), + CRC => (AHB1, 12), +} + +bus! { + GPIOA => (AHB2, 0), + GPIOB => (AHB2, 1), + GPIOC => (AHB2, 2), + GPIOD => (AHB2, 3), + GPIOE => (AHB2, 4), + GPIOF => (AHB2, 5), + GPIOG => (AHB2, 6), + ADC1 => (AHB2, 13), + ADC2 => (AHB2, 13), + DAC1 => (AHB2, 16), + DAC2 => (AHB2, 17), + DAC3 => (AHB2, 18), + DAC4 => (AHB2, 19), + RNG => (AHB2, 26), +} + +#[cfg(any( + feature = "stm32g471", + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484" +))] +bus! { + ADC3 => (AHB2, 14), +} + +#[cfg(any( + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484" +))] +bus! { + ADC4 => (AHB2, 14), + ADC5 => (AHB2, 14), +} + +#[cfg(any(feature = "stm32g431", feature = "stm32g441", feature = "stm32g484",))] +bus! { + AES => (AHB2, 24), +} + +#[cfg(any( + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484" +))] +bus! { + FMC => (AHB3, 0), + QUADSPI => (AHB3, 8), +} + +bus! { + TIM2 => (APB1_1, 0), + TIM3 => (APB1_1, 1), + TIM4 => (APB1_1, 2), + TIM6 => (APB1_1, 4), + TIM7 => (APB1_1, 5), + CRS => (APB1_1, 8), + SPI2 => (APB1_1, 14), + SPI3 => (APB1_1, 15), + USART2 => (APB1_1, 17), + USART3 => (APB1_1, 18), + UART4 => (APB1_1, 19), + I2C1 => (APB1_1, 21), + I2C2 => (APB1_1, 22), + USB => (APB1_1, 23), + FDCAN1 => (APB1_1, 25), + PWR => (APB1_1, 28), + I2C3 => (APB1_1, 30), + LPTIMER1 => (APB1_1, 31), + LPUART1 => (APB1_2, 0), + UCPD1 => (APB1_2, 8), +} + +#[cfg(any( + feature = "stm32g471", + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484", + feature = "stm32g491", + feature = "stm32g4A1" +))] +bus! { + FDCAN2 => (APB1_1, 25), +} + +#[cfg(any( + feature = "stm32g471", + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484" +))] +bus! { + TIM5 => (APB1_1, 3), + UART5 => (APB1_1, 20), + I2C4 => (APB1_2, 1), +} + +bus! { + SYSCFG => (APB2, 0), + TIM1 => (APB2, 11), + SPI1 => (APB2, 12), + TIM8 => (APB2, 13), + USART1 => (APB2, 14), + TIM15 => (APB2, 16), + TIM16 => (APB2, 17), + TIM17 => (APB2, 18), + SAI => (APB2, 21), +} + +#[cfg(any( + feature = "stm32g471", + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484" +))] +bus! { + SPI4 => (APB2, 15), +} + +#[cfg(any( + feature = "stm32g473", + feature = "stm32g474", + feature = "stm32g483", + feature = "stm32g484" +))] +bus! { + FDCAN3 => (APB1_1, 25), + TIM20 => (APB2, 20), +} + +#[cfg(any(feature = "stm32g474", feature = "stm32g484"))] +bus! { + HRTIM_TIMA => (APB2, 26), + HRTIM_TIMB => (APB2, 26), + HRTIM_TIMC => (APB2, 26), + HRTIM_TIMD => (APB2, 26), + HRTIM_TIME => (APB2, 26), + HRTIM_TIMF => (APB2, 26), +} diff --git a/src/rcc/g4/mod.rs b/src/rcc/g4/mod.rs new file mode 100644 index 00000000..451a47d5 --- /dev/null +++ b/src/rcc/g4/mod.rs @@ -0,0 +1,574 @@ +use crate::pac::{self, rcc, FLASH, PWR, RCC}; +use crate::time::Hertz; +use fugit::RateExtU32; + +mod clockout; +mod config; +mod enable; + +pub use clockout::*; +pub use config::*; + +pub trait Instance: crate::Sealed + Enable + Reset + BusClock {} + +/// HSI speed +pub const HSI_FREQ: u32 = 16_000_000; + +/// Clock frequencies +#[derive(Clone, Copy, Debug)] +pub struct Clocks { + /// System frequency + pub sysclk: Hertz, + /// Core frequency + pub core_clk: Hertz, + /// AHB frequency + pub hclk: Hertz, + /// APB 1 frequency + pub pclk1: Hertz, + /// APB 1 timers frequency (Timers 2-7) + pub timclk1: Hertz, + /// APB 2 frequency + pub pclk2: Hertz, + /// APB 2 timers frequency (Timers 1, 8, 20, 15, 16, 17 and HRTIM1) + pub timclk2: Hertz, + /// PLL frequency + pub pll_clk: PLLClocks, +} + +impl Clocks { + /// Returns the frequency of the AHB + pub fn hclk(&self) -> Hertz { + self.hclk + } + + /// Returns the frequency of the APB1 + pub fn pclk1(&self) -> Hertz { + self.pclk1 + } + + /// Returns the frequency of the APB2 + pub fn pclk2(&self) -> Hertz { + self.pclk2 + } + + /// Returns the system (core) frequency + pub fn sysclk(&self) -> Hertz { + self.sysclk + } + + /// Returns the frequency for timers on APB1 + pub fn timclk1(&self) -> Hertz { + self.timclk1 + } + + /// Returns the frequency for timers on APB2 + pub fn timclk2(&self) -> Hertz { + self.timclk2 + } +} + +/// PLL Clock frequencies +#[derive(Clone, Copy, Debug)] +pub struct PLLClocks { + /// R frequency + pub r: Option, + /// Q frequency + pub q: Option, + /// P frequency + pub p: Option, +} + +impl Default for Clocks { + fn default() -> Clocks { + let freq = HSI_FREQ.Hz(); + Clocks { + sysclk: freq, + hclk: freq, + core_clk: freq, + pclk1: freq, + timclk1: freq, + pclk2: freq, + timclk2: freq, + pll_clk: PLLClocks { + r: None, + q: None, + p: None, + }, + } + } +} + +/// Constrained RCC peripheral +pub struct Rcc { + /// Clock configuration + pub clocks: Clocks, + pub(crate) rb: RCC, +} + +impl Rcc { + /// Apply clock configuration + pub fn freeze(self, rcc_cfg: Config) -> Self { + let pll_clk = self.config_pll(rcc_cfg.pll_cfg); + + let (sysclk, sw_bits) = match rcc_cfg.sys_mux { + SysClockSrc::HSI => { + self.enable_hsi(); + (HSI_FREQ.Hz(), 0b01) + } + SysClockSrc::HSE(freq) => { + self.enable_hse(false); + (freq, 0b10) + } + SysClockSrc::PLL => { + // If PLL is selected as sysclock then the r output should have been configured + if pll_clk.r.is_none() { + panic!("PLL output selected as sysclock but PLL output R is not configured") + } + (pll_clk.r.unwrap(), 0b11) + } + }; + + let sys_freq = sysclk.raw(); + let (ahb_freq, ahb_psc_bits) = match rcc_cfg.ahb_psc { + Prescaler::Div2 => (sys_freq / 2, 0b1000), + Prescaler::Div4 => (sys_freq / 4, 0b1001), + Prescaler::Div8 => (sys_freq / 8, 0b1010), + Prescaler::Div16 => (sys_freq / 16, 0b1011), + Prescaler::Div64 => (sys_freq / 64, 0b1100), + Prescaler::Div128 => (sys_freq / 128, 0b1101), + Prescaler::Div256 => (sys_freq / 256, 0b1110), + Prescaler::Div512 => (sys_freq / 512, 0b1111), + _ => (sysclk.raw(), 0b0000), + }; + let (apb1_freq, apb1_psc_bits) = match rcc_cfg.apb1_psc { + Prescaler::Div2 => (sysclk.raw() / 2, 0b100), + Prescaler::Div4 => (sysclk.raw() / 4, 0b101), + Prescaler::Div8 => (sysclk.raw() / 8, 0b110), + Prescaler::Div16 => (sysclk.raw() / 16, 0b111), + _ => (sysclk.raw(), 0b000), + }; + let (apb2_freq, apb2_psc_bits) = match rcc_cfg.apb2_psc { + Prescaler::Div2 => (sysclk.raw() / 2, 0b100), + Prescaler::Div4 => (sysclk.raw() / 4, 0b101), + Prescaler::Div8 => (sysclk.raw() / 8, 0b110), + Prescaler::Div16 => (sysclk.raw() / 16, 0b111), + _ => (sysclk.raw(), 0b000), + }; + + unsafe { + // Adjust flash wait states + let flash = &(*FLASH::ptr()); + flash.acr.modify(|_, w| { + w.latency().bits(if sysclk.raw() <= 24_000_000 { + 0b000 + } else if sysclk.raw() <= 48_000_000 { + 0b001 + } else { + 0b010 + }) + }) + } + + self.rb.cfgr.modify(|_, w| unsafe { + w.hpre().bits(ahb_psc_bits); + w.ppre1().bits(apb1_psc_bits); + w.ppre2().bits(apb2_psc_bits); + w.sw().bits(sw_bits) + }); + + while self.rb.cfgr.read().sws().bits() != sw_bits {} + + // From RM: + // The timer clock frequencies are automatically defined by hardware. There are two cases: + // 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same + // frequency as that of the APB domain. + // 2. Otherwise, they are set to twice (×2) the frequency of the APB domain. + let timclk1 = match rcc_cfg.apb1_psc { + Prescaler::NotDivided => apb1_freq, + _ => apb1_freq * 2, + }; + + let timclk2 = match rcc_cfg.apb2_psc { + Prescaler::NotDivided => apb2_freq, + _ => apb2_freq * 2, + }; + + Rcc { + rb: self.rb, + clocks: Clocks { + pll_clk, + sysclk, + core_clk: ahb_freq.Hz(), + hclk: ahb_freq.Hz(), + pclk1: apb1_freq.Hz(), + timclk1: timclk1.Hz(), + pclk2: apb2_freq.Hz(), + timclk2: timclk2.Hz(), + }, + } + } + + pub fn unlock_rtc(&mut self) { + self.rb.apb1enr1.modify(|_, w| w.pwren().set_bit()); + let pwr = unsafe { &(*PWR::ptr()) }; + pwr.cr1.modify(|_, w| w.dbp().set_bit()); + } + + fn config_pll(&self, pll_cfg: PllConfig) -> PLLClocks { + // Disable PLL + self.rb.cr.modify(|_, w| w.pllon().clear_bit()); + while self.rb.cr.read().pllrdy().bit_is_set() {} + + // Enable the input clock feeding the PLL + let (pll_input_freq, pll_src_bits) = match pll_cfg.mux { + PLLSrc::HSI => { + self.enable_hsi(); + (HSI_FREQ, 0b10) + } + PLLSrc::HSE(freq) => { + self.enable_hse(false); + (freq.raw(), 0b11) + } + PLLSrc::HSE_BYPASS(freq) => { + self.enable_hse(true); + (freq.raw(), 0b11) + } + }; + + // Calculate the frequency of the internal PLL VCO. + let pll_freq = pll_input_freq / pll_cfg.m.divisor() * pll_cfg.n.multiplier(); + + // Calculate the output frequencies for the P, Q, and R outputs + let p = pll_cfg + .p + .map(|p| ((pll_freq / p.divisor()).Hz(), p.register_setting())); + + let q = pll_cfg + .q + .map(|q| ((pll_freq / q.divisor()).Hz(), q.register_setting())); + + let r = pll_cfg + .r + .map(|r| ((pll_freq / r.divisor()).Hz(), r.register_setting())); + + // Set the M input divider, the N multiplier for the PLL, and the PLL source. + self.rb.pllcfgr.modify(|_, w| unsafe { + // Set N, M, and source + let w = w.plln().bits(pll_cfg.n.register_setting()); + w.pllm().bits(pll_cfg.m.register_setting()); + w.pllsrc().bits(pll_src_bits); + + // Set and enable P if requested + let w = match p { + Some((_, register_setting)) => { + w.pllpdiv().bits(register_setting).pllpen().set_bit() + } + None => w, + }; + + // Set and enable Q if requested + let w = match q { + Some((_, register_setting)) => w.pllq().bits(register_setting).pllqen().set_bit(), + None => w, + }; + + // Set and enable R if requested + let w = match r { + Some((_, register_setting)) => w.pllr().bits(register_setting).pllren().set_bit(), + None => w, + }; + + w + }); + + // Enable PLL + self.rb.cr.modify(|_, w| w.pllon().set_bit()); + while self.rb.cr.read().pllrdy().bit_is_clear() {} + + PLLClocks { + r: r.map(|r| r.0), + q: q.map(|q| q.0), + p: p.map(|p| p.0), + } + } + + pub(crate) fn enable_hsi(&self) { + self.rb.cr.modify(|_, w| w.hsion().set_bit()); + while self.rb.cr.read().hsirdy().bit_is_clear() {} + } + + pub(crate) fn enable_hse(&self, bypass: bool) { + self.rb + .cr + .modify(|_, w| w.hseon().set_bit().hsebyp().bit(bypass)); + while self.rb.cr.read().hserdy().bit_is_clear() {} + } + + pub(crate) fn enable_lse(&self, bypass: bool) { + self.rb + .bdcr + .modify(|_, w| w.lseon().set_bit().lsebyp().bit(bypass)); + while self.rb.bdcr.read().lserdy().bit_is_clear() {} + } + + pub(crate) fn enable_lsi(&self) { + self.rb.csr.modify(|_, w| w.lsion().set_bit()); + while self.rb.csr.read().lsirdy().bit_is_clear() {} + } +} + +/// Extension trait that constrains the `RCC` peripheral +pub trait RccExt { + /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions + fn constrain(self) -> Rcc; + + /// Constrains the `RCC` peripheral and apply clock configuration + fn freeze(self, rcc_cfg: Config) -> Rcc; +} + +impl RccExt for RCC { + fn constrain(self) -> Rcc { + Rcc { + rb: self, + clocks: Clocks::default(), + } + } + + fn freeze(self, rcc_cfg: Config) -> Rcc { + self.constrain().freeze(rcc_cfg) + } +} + +use crate::pac::rcc::RegisterBlock as RccRB; + +pub struct AHB1 { + _0: (), +} +impl AHB1 { + #[inline(always)] + fn enr(rcc: &RccRB) -> &rcc::AHB1ENR { + &rcc.ahb1enr + } + #[inline(always)] + fn rstr(rcc: &RccRB) -> &rcc::AHB1RSTR { + &rcc.ahb1rstr + } + #[inline(always)] + fn smenr(rcc: &RccRB) -> &rcc::AHB1SMENR { + &rcc.ahb1smenr + } +} + +pub struct AHB2 { + _0: (), +} +impl AHB2 { + #[inline(always)] + fn enr(rcc: &RccRB) -> &rcc::AHB2ENR { + &rcc.ahb2enr + } + #[inline(always)] + fn rstr(rcc: &RccRB) -> &rcc::AHB2RSTR { + &rcc.ahb2rstr + } + #[inline(always)] + fn smenr(rcc: &RccRB) -> &rcc::AHB2SMENR { + &rcc.ahb2smenr + } +} + +pub struct AHB3 { + _0: (), +} +impl AHB3 { + #[inline(always)] + fn enr(rcc: &RccRB) -> &rcc::AHB3ENR { + &rcc.ahb3enr + } + #[inline(always)] + fn rstr(rcc: &RccRB) -> &rcc::AHB3RSTR { + &rcc.ahb3rstr + } + #[inline(always)] + fn smenr(rcc: &RccRB) -> &rcc::AHB3SMENR { + &rcc.ahb3smenr + } +} + +pub struct APB1_1 { + _0: (), +} +impl APB1_1 { + #[inline(always)] + fn enr(rcc: &RccRB) -> &rcc::APB1ENR1 { + &rcc.apb1enr1 + } + #[inline(always)] + fn rstr(rcc: &RccRB) -> &rcc::APB1RSTR1 { + &rcc.apb1rstr1 + } + #[inline(always)] + fn smenr(rcc: &RccRB) -> &rcc::APB1SMENR1 { + &rcc.apb1smenr1 + } +} + +pub struct APB1_2 { + _0: (), +} +impl APB1_2 { + #[inline(always)] + fn enr(rcc: &RccRB) -> &rcc::APB1ENR2 { + &rcc.apb1enr2 + } + #[inline(always)] + fn rstr(rcc: &RccRB) -> &rcc::APB1RSTR2 { + &rcc.apb1rstr2 + } + #[inline(always)] + fn smenr(rcc: &RccRB) -> &rcc::APB1SMENR2 { + &rcc.apb1smenr2 + } +} + +pub struct APB2 { + _0: (), +} +impl APB2 { + #[inline(always)] + fn enr(rcc: &RccRB) -> &rcc::APB2ENR { + &rcc.apb2enr + } + #[inline(always)] + fn rstr(rcc: &RccRB) -> &rcc::APB2RSTR { + &rcc.apb2rstr + } + #[inline(always)] + fn smenr(rcc: &RccRB) -> &rcc::APB2SMENR { + &rcc.apb2smenr + } +} + +/// Bus associated to peripheral +pub trait RccBus: crate::Sealed { + /// Bus type; + type Bus; +} + +/// Enable/disable peripheral +pub trait Enable: RccBus { + fn enable(rcc: &RccRB); + fn disable(rcc: &RccRB); + + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn enable_unchecked() { + let rcc = &*pac::RCC::ptr(); + Self::enable(rcc); + } + + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn disable_unchecked() { + let rcc = &*pac::RCC::ptr(); + Self::disable(rcc); + } +} + +/// Reset peripheral +pub trait Reset: RccBus { + fn reset(rcc: &RccRB); + + /// # Safety + /// + /// Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked() { + let rcc = pac::RCC::ptr(); + Self::reset(&*rcc); + } +} + +/// Frequency on bus that peripheral is connected in +pub trait BusClock { + /// Calculates frequency depending on `Clock` state + fn clock(clocks: &Clocks) -> Hertz; +} + +/// Frequency on bus that timer is connected in +pub trait BusTimerClock { + /// Calculates base frequency of timer depending on `Clock` state + fn timer_clock(clocks: &Clocks) -> Hertz; +} + +impl BusClock for T +where + T: RccBus, + T::Bus: BusClock, +{ + fn clock(clocks: &Clocks) -> Hertz { + T::Bus::clock(clocks) + } +} + +impl BusTimerClock for T +where + T: RccBus, + T::Bus: BusTimerClock, +{ + fn timer_clock(clocks: &Clocks) -> Hertz { + T::Bus::timer_clock(clocks) + } +} + +impl BusClock for AHB1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for AHB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for AHB3 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.hclk + } +} + +impl BusClock for APB1_1 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk1 + } +} +impl BusTimerClock for APB1_1 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk1 + } +} + +impl BusClock for APB1_2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk1 + } +} +impl BusTimerClock for APB1_2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk1 + } +} + +impl BusClock for APB2 { + fn clock(clocks: &Clocks) -> Hertz { + clocks.pclk2 + } +} +impl BusTimerClock for APB2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + clocks.timclk2 + } +} diff --git a/src/rcc/l4/enable.rs b/src/rcc/l4/enable.rs new file mode 100644 index 00000000..41f64a96 --- /dev/null +++ b/src/rcc/l4/enable.rs @@ -0,0 +1,375 @@ +use super::*; + +macro_rules! bus_enable { + ($PER:ident => $en:ident) => { + impl Enable for crate::pac::$PER { + #[inline(always)] + fn enable(bus: &mut Self::Bus) { + bus.enr().modify(|_, w| w.$en().set_bit()); + // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + cortex_m::asm::dsb(); // TODO: check if needed + } + #[inline(always)] + fn disable(bus: &mut Self::Bus) { + bus.enr().modify(|_, w| w.$en().clear_bit()); + } + #[inline(always)] + fn is_enabled() -> bool { + Self::Bus::new().enr().read().$en().bit_is_set() + } + #[inline(always)] + fn is_disabled() -> bool { + Self::Bus::new().enr().read().$en().bit_is_clear() + } + #[inline(always)] + unsafe fn enable_unchecked() { + Self::enable(&mut Self::Bus::new()); + } + #[inline(always)] + unsafe fn disable_unchecked() { + Self::disable(&mut Self::Bus::new()); + } + } + }; +} + +macro_rules! bus_smenable { + ($PER:ident => $smen:ident) => { + impl SMEnable for crate::pac::$PER { + #[inline(always)] + fn enable_in_sleep_mode(bus: &mut Self::Bus) { + bus.smenr().modify(|_, w| w.$smen().set_bit()); + // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + cortex_m::asm::dsb(); + } + #[inline(always)] + fn disable_in_sleep_mode(bus: &mut Self::Bus) { + bus.smenr().modify(|_, w| w.$smen().clear_bit()); + } + #[inline(always)] + fn is_enabled_in_sleep_mode() -> bool { + Self::Bus::new().smenr().read().$smen().bit_is_set() + } + #[inline(always)] + fn is_disabled_in_sleep_mode() -> bool { + Self::Bus::new().smenr().read().$smen().bit_is_clear() + } + #[inline(always)] + unsafe fn enable_in_sleep_mode_unchecked() { + Self::enable(&mut Self::Bus::new()); + } + #[inline(always)] + unsafe fn disable_in_sleep_mode_unchecked() { + Self::disable(&mut Self::Bus::new()); + } + } + }; +} +macro_rules! bus_reset { + ($PER:ident => $rst:ident) => { + impl Reset for crate::pac::$PER { + #[inline(always)] + fn reset(bus: &mut Self::Bus) { + bus.rstr().modify(|_, w| w.$rst().set_bit()); + bus.rstr().modify(|_, w| w.$rst().clear_bit()); + } + #[inline(always)] + unsafe fn reset_unchecked() { + Self::reset(&mut Self::Bus::new()); + } + } + }; +} + +macro_rules! bus { + ($($PER:ident => ($busX:ty, $($en:ident)?, $($smen:ident)?, $($rst:ident)?),)+) => { + $( + impl crate::Sealed for crate::pac::$PER {} + impl RccBus for crate::pac::$PER { + type Bus = $busX; + } + $(bus_enable!($PER => $en);)? + $(bus_smenable!($PER => $smen);)? + $(bus_reset!($PER => $rst);)? + )+ + }; +} + +bus! { + DMA1 => (AHB1, dma1en, dma1smen, dma1rst), // 0 + DMA2 => (AHB1, dma2en, dma2smen, dma2rst), // 1 + FLASH => (AHB1, flashen, flashsmen, flashrst), // 8 + CRC => (AHB1, crcen, crcsmen, crcrst), // 12 + TSC => (AHB1, tscen, tscsmen, tscrst), // 16 + + GPIOA => (AHB2, gpioaen, gpioasmen, gpioarst), // 0 + GPIOB => (AHB2, gpioben, gpiobsmen, gpiobrst), // 1 + GPIOC => (AHB2, gpiocen, gpiocsmen, gpiocrst), // 2 + GPIOD => (AHB2, gpioden, gpiodsmen, gpiodrst), // 3 + GPIOE => (AHB2, gpioeen, gpioesmen, gpioerst), // 4 + GPIOH => (AHB2, gpiohen, gpiohsmen, gpiohrst), // 7 + AES => (AHB2, aesen, aessmen, aesrst), // 16 + RNG => (AHB2, rngen, rngsmen, rngrst), // 18 + + TIM2 => (APB1R1, tim2en, tim2smen, tim2rst), // 0 + TIM6 => (APB1R1, tim6en, tim6smen, tim6rst), // 4 + TIM7 => (APB1R1, tim7en, tim7smen, tim7rst), // 5 + WWDG => (APB1R1, wwdgen, wwdgsmen,), // 11 + SPI2 => (APB1R1, spi2en, spi2smen, spi2rst), // 14 + SPI3 => (APB1R1, spi3en, sp3smen, spi3rst), // 15 // TODO: fix typo + USART2 => (APB1R1, usart2en, usart2smen, usart2rst), // 17 + USART3 => (APB1R1, usart3en, usart3smen, usart3rst), // 18 + I2C1 => (APB1R1, i2c1en, i2c1smen, i2c1rst), // 21 + I2C2 => (APB1R1, i2c2en, i2c2smen, i2c2rst), // 22 + I2C3 => (APB1R1, i2c3en, i2c3smen, i2c3rst), // 23 + CAN1 => (APB1R1, can1en, can1smen, can1rst), // 25 + PWR => (APB1R1, pwren, pwrsmen, pwrrst), // 28 + OPAMP => (APB1R1, opampen, opampsmen, opamprst), // 30 + LPTIM1 => (APB1R1, lptim1en, lptim1smen, lptim1rst), // 31 + + LPUART1 => (APB1R2, lpuart1en, lpuart1smen, lpuart1rst), // 0 + LPTIM2 => (APB1R2, lptim2en, lptim2smen, lptim2rst), // 5 + + SYSCFG => (APB2, syscfgen, syscfgsmen, syscfgrst), // 0 + TIM1 => (APB2, tim1en, tim1smen, tim1rst), // 11 + SPI1 => (APB2, spi1en, spi1smen, spi1rst), // 12 + USART1 => (APB2, usart1en, usart1smen, usart1rst), // 14 + TIM15 => (APB2, tim15en, tim15smen, tim15rst), // 16 + TIM16 => (APB2, tim16en, tim16smen, tim16rst), // 17 + SAI1 => (APB2, sai1en, sai1smen, sai1rst), // 21 +} + +// L4x1, L4x2, L4x3, L4x5 or L4x6 +#[cfg(not(any( + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +)))] +bus! { + ADC_COMMON => (AHB2, adcen, adcfssmen, adcrst), // 13 + + LCD => (APB1R1, lcden, lcdsmen, lcdrst), // 9 + + SWPMI1 => (APB1R2, swpmi1en, swpmi1smen, swpmi1rst), // 2 + + FIREWALL => (APB2, firewallen,,), // 7 +} + +// L4+ +#[cfg(any( + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +))] +bus! { + ADC1 => (AHB2, adcen, adcfssmen, adcrst), // 13 + + FIREWALL => (APB2, fwen,,), // 7 + LTCD => (APB2, ltdcen, ltdcsmen, ltdcrst), // 26 +} + +// L4x5 or L4x6 +#[cfg(any( + feature = "stm32l475", + feature = "stm32l476", + feature = "stm32l485", + feature = "stm32l486", + feature = "stm32l496", + feature = "stm32l4a6", + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +))] +bus! { + GPIOF => (AHB2, gpiofen, gpiofsmen, gpiofrst), // 5 + GPIOG => (AHB2, gpiogen, gpiogsmen, gpiogrst), // 6 + + FMC => (AHB3, fmcen, fmcsmen, fmcrst), // 0 + + TIM3 => (APB1R1, tim3en, tim3smen, tim3rst), // 1 + TIM4 => (APB1R1, tim4en, tim4smen, tim4rst), // 2 + TIM5 => (APB1R1, tim5en, tim5smen, tim5rst), // 3 + UART4 => (APB1R1, uart4en, uart4smen, uart4rst), // 19 + UART5 => (APB1R1, uart5en, uart5smen, uart5rst), // 20 + + TIM8 => (APB2, tim8en, tim8smen, tim8rst), // 13 + TIM17 => (APB2, tim17en, tim17smen, tim17rst), // 18 + SAI2 => (APB2, sai2en, sai2smen, sai2rst), // 22 +} + +// L4x1 or L4x2 +#[cfg(any( + feature = "stm32l431", + feature = "stm32l451", + feature = "stm32l471", + feature = "stm32l412", + feature = "stm32l422", + feature = "stm32l432", + feature = "stm32l442", + feature = "stm32l452", + feature = "stm32l462", +))] +bus! { + UART4 => (APB1R1, uart4en, uart4smen, usart4rst), // 19 // TODO: fix typo + + I2C4 => (APB1R2, i2c4en,, i2c4rst), // 1 // TODO: fix absent +} + +// L4x1, L4x2, L4x3, or L4x5 +#[cfg(any( + feature = "stm32l431", + feature = "stm32l451", + feature = "stm32l471", + feature = "stm32l412", + feature = "stm32l422", + feature = "stm32l432", + feature = "stm32l442", + feature = "stm32l452", + feature = "stm32l462", + feature = "stm32l433", + feature = "stm32l443", + feature = "stm32l475", +))] +bus! { + DAC => (APB1R1, dac1en, dac1smen, dac1rst), // 29 + + SDMMC => (APB2, sdmmcen, sdmmcsmen, sdmmcrst), // 10 +} + +// L4x1, L4x2, L4x5, or L4x6 +#[cfg(not(any( + feature = "stm32l433", + feature = "stm32l443", + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +)))] +bus! { + QUADSPI => (AHB3, qspien, qspismen, qspirst), // 8 +} + +// L4x1, L4x2, L4x3, or L4x6 (L4+ assumed) +#[cfg(not(any(feature = "stm32l475",)))] +bus! { + CRS => (APB1R1, crsen,,), // 24 // TODO: fix absent +} + +// L4x1, or L4x3 +#[cfg(any( + feature = "stm32l412", + feature = "stm32l422", + feature = "stm32l432", + feature = "stm32l442", + feature = "stm32l452", + feature = "stm32l462", + feature = "stm32l433", + feature = "stm32l443", +))] +bus! { + USB => (APB1R1, usbfsen, usbfssmen, usbfsrst), // 26 +} + +// L4x1 +#[cfg(any(feature = "stm32l431", feature = "stm32l451", feature = "stm32l471",))] +bus! { + TIM3 => (APB1R1, tim3en,,), // 1 // TODO: absent smen, rst + USB_FS => (APB1R1, usbf, usbfssmen, usbfsrst), // 26 // TODO: fix typo +} + +// L4x2 +#[cfg(any( + feature = "stm32l412", + feature = "stm32l422", + feature = "stm32l432", + feature = "stm32l442", + feature = "stm32l452", + feature = "stm32l462", +))] +bus! { + TIM3 => (APB1R1, tim3en,, tim3rst), // 1 // TODO: fix absent +} + +// L4x5 +#[cfg(any(feature = "stm32l475"))] +bus! { + DFSDM => (APB2, dfsdmen, dfsdmsmen, dfsdmrst), // 24 +} + +// L4x6 (L4+ assumed) +#[cfg(any( + feature = "stm32l476", + feature = "stm32l486", + feature = "stm32l496", + feature = "stm32l4a6", + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +))] +bus! { + DMA2D => (AHB1, dma2den, dma2dsmen, dma2drst), // 17 + + GPIOI => (AHB2, gpioien, gpioismen, gpioirst), // 8 + OTG_FS_GLOBAL => (AHB2, otgfsen, otgfssmen, otgfsrst), // 12 // TODO: absent in x5 + DCMI => (AHB2, dcmien, dcmismen, dcmirst), // 14 + + DAC => (APB1R1, dac1en, dac1smen, dac1rst), // 29 + + I2C4 => (APB1R2, i2c4en, i2c4smen, i2c4rst), // 1 +} + +#[cfg(any( + feature = "stm32l476", + feature = "stm32l486", + feature = "stm32l496", + feature = "stm32l4a6", +))] +bus! { + CAN2 => (APB1R1, can2en, can2smen, can2rst), // 26 + + HASH => (AHB2, hash1en, hash1smen, hash1rst), // 17 + + SDMMC1 => (APB2, sdmmcen, sdmmcsmen, sdmmcrst), // 10 + DFSDM1 => (APB2, dfsdmen, dfsdmsmen, dfsdmrst), // 24 +} + +#[cfg(any( + // feature = "stm32l4p5", + // feature = "stm32l4q5", + // feature = "stm32l4r5", + // feature = "stm32l4s5", + // feature = "stm32l4r7", + // feature = "stm32l4s7", + feature = "stm32l4r9", + feature = "stm32l4s9", +))] +bus! { + HASH => (AHB2, hashen, hashsmen, hashrst), // 17 + SDMMC1 => (AHB2, sdmmc1en, sdmmc1smen, sdmmc1rst), // 22 + + DFSDM1 => (APB2, dfsdm1en, dfsdm1smen, dfsdm1rst), // 24 +} diff --git a/src/rcc/l4/mod.rs b/src/rcc/l4/mod.rs new file mode 100644 index 00000000..3cca86f0 --- /dev/null +++ b/src/rcc/l4/mod.rs @@ -0,0 +1,1050 @@ +//! Reset and Clock Control + +use crate::pac::{rcc, RCC}; + +use crate::flash::ACR; +use crate::pwr::Pwr; +use crate::time::Hertz; +use fugit::RateExtU32; + +mod enable; + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MsiFreq { + #[doc = "range 0 around 100 kHz"] + RANGE100K = 0, + #[doc = "range 1 around 200 kHz"] + RANGE200K = 1, + #[doc = "range 2 around 400 kHz"] + RANGE400K = 2, + #[doc = "range 3 around 800 kHz"] + RANGE800K = 3, + #[doc = "range 4 around 1 MHz"] + RANGE1M = 4, + #[doc = "range 5 around 2 MHz"] + RANGE2M = 5, + #[doc = "range 6 around 4 MHz"] + RANGE4M = 6, + #[doc = "range 7 around 8 MHz"] + RANGE8M = 7, + #[doc = "range 8 around 16 MHz"] + RANGE16M = 8, + #[doc = "range 9 around 24 MHz"] + RANGE24M = 9, + #[doc = "range 10 around 32 MHz"] + RANGE32M = 10, + #[doc = "range 11 around 48 MHz"] + RANGE48M = 11, +} + +impl MsiFreq { + fn to_hertz(self) -> Hertz { + (match self { + Self::RANGE100K => 100_000, + Self::RANGE200K => 200_000, + Self::RANGE400K => 400_000, + Self::RANGE800K => 800_000, + Self::RANGE1M => 1_000_000, + Self::RANGE2M => 2_000_000, + Self::RANGE4M => 4_000_000, + Self::RANGE8M => 8_000_000, + Self::RANGE16M => 16_000_000, + Self::RANGE24M => 24_000_000, + Self::RANGE32M => 32_000_000, + Self::RANGE48M => 48_000_000, + }) + .Hz() + } +} + +/// Extension trait that constrains the `RCC` peripheral +pub trait RccExt { + /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions + fn constrain(self) -> Rcc; +} + +impl RccExt for RCC { + fn constrain(self) -> Rcc { + Rcc { + ahb1: AHB1::new(), + ahb2: AHB2::new(), + ahb3: AHB3::new(), + apb1r1: APB1R1::new(), + apb1r2: APB1R2::new(), + apb2: APB2::new(), + bdcr: BDCR { _0: () }, + csr: CSR { _0: () }, + crrcr: CRRCR { _0: () }, + ccipr: CCIPR { _0: () }, + cfgr: CFGR { + hse: None, + lse: None, + msi: None, + hsi48: false, + lsi: false, + hclk: None, + pclk1: None, + pclk2: None, + sysclk: None, + pll_source: None, + pll_config: None, + }, + } + } +} + +/// Constrained RCC peripheral +pub struct Rcc { + /// AMBA High-performance Bus (AHB1) registers + pub ahb1: AHB1, + /// AMBA High-performance Bus (AHB2) registers + pub ahb2: AHB2, + /// AMBA High-performance Bus (AHB3) registers + pub ahb3: AHB3, + /// Advanced Peripheral Bus 1 (APB1) registers + pub apb1r1: APB1R1, + /// Advanced Peripheral Bus 1 (APB2) registers + pub apb1r2: APB1R2, + /// Advanced Peripheral Bus 2 (APB2) registers + pub apb2: APB2, + /// Clock configuration register + pub cfgr: CFGR, + /// Backup domain control register + pub bdcr: BDCR, + /// Control/Status Register + pub csr: CSR, + /// Clock recovery RC register + pub crrcr: CRRCR, + /// Peripherals independent clock configuration register + pub ccipr: CCIPR, +} + +/// CSR Control/Status Register +pub struct CSR { + _0: (), +} + +impl CSR { + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn csr(&mut self) -> &rcc::CSR { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).csr } + } +} + +/// Clock recovery RC register +pub struct CRRCR { + _0: (), +} + +impl CRRCR { + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn crrcr(&mut self) -> &rcc::CRRCR { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).crrcr } + } + + /// Checks if the 48 MHz HSI is enabled + pub fn is_hsi48_on(&mut self) -> bool { + self.crrcr().read().hsi48on().bit() + } + + /// Checks if the 48 MHz HSI is ready + pub fn is_hsi48_ready(&mut self) -> bool { + self.crrcr().read().hsi48rdy().bit() + } +} + +/// Peripherals independent clock configuration register +pub struct CCIPR { + _0: (), +} + +impl CCIPR { + #[allow(dead_code)] + pub(crate) fn ccipr(&mut self) -> &rcc::CCIPR { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).ccipr } + } +} + +/// BDCR Backup domain control register registers +pub struct BDCR { + _0: (), +} + +impl BDCR { + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn enr(&mut self) -> &rcc::BDCR { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).bdcr } + } +} + +macro_rules! bus_struct { + ($($busX:ident => ($EN:ident, $en:ident, $SMEN:ident, $smen:ident, $RST:ident, $rst:ident, $clk:ident, $doc:literal),)+) => { + $( + #[doc = $doc] + pub struct $busX { + _0: (), + } + + impl $busX { + pub(crate) fn new() -> Self { + Self { _0: () } + } + + #[allow(unused)] + pub(crate) fn enr(&self) -> &rcc::$EN { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).$en } + } + + #[allow(unused)] + pub(crate) fn smenr(&self) -> &rcc::$SMEN { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).$smen } + } + + #[allow(unused)] + pub(crate) fn rstr(&self) -> &rcc::$RST { + // NOTE(unsafe) this proxy grants exclusive access to this register + unsafe { &(*RCC::ptr()).$rst } + } + } + + impl BusClock for $busX { + fn clock(clocks: &Clocks) -> Hertz { + clocks.$clk + } + } + )+ + }; +} + +bus_struct! { + AHB1 => (AHB1ENR, ahb1enr, AHB1SMENR, ahb1smenr, AHB1RSTR, ahb1rstr, hclk, "Advanced High-performance Bus 1 (AHB1) registers"), + AHB2 => (AHB2ENR, ahb2enr, AHB2SMENR, ahb2smenr, AHB2RSTR, ahb2rstr, hclk, "Advanced High-performance Bus 2 (AHB2) registers"), + AHB3 => (AHB3ENR, ahb3enr, AHB3SMENR, ahb3smenr, AHB3RSTR, ahb3rstr, hclk, "Advanced High-performance Bus 3 (AHB3) registers"), + APB1R1 => (APB1ENR1, apb1enr1, APB1SMENR1, apb1smenr1, APB1RSTR1, apb1rstr1, pclk1, "Advanced Peripheral Bus 1 (APB1) registers"), + APB1R2 => (APB1ENR2, apb1enr2, APB1SMENR2, apb1smenr2, APB1RSTR2, apb1rstr2, pclk1, "Advanced Peripheral Bus 1 (APB1) registers"), + APB2 => (APB2ENR, apb2enr, APB2SMENR, apb2smenr, APB2RSTR, apb2rstr, pclk2, "Advanced Peripheral Bus 2 (APB2) registers"), +} + +/// Bus associated to peripheral +pub trait RccBus: crate::Sealed { + /// Bus type; + type Bus; +} + +/// Frequency on bus that peripheral is connected in +pub trait BusClock { + /// Calculates frequency depending on `Clock` state + fn clock(clocks: &Clocks) -> Hertz; +} + +/// Frequency on bus that timer is connected in +pub trait BusTimerClock { + /// Calculates base frequency of timer depending on `Clock` state + fn timer_clock(clocks: &Clocks) -> Hertz; +} + +impl BusClock for T +where + T: RccBus, + T::Bus: BusClock, +{ + fn clock(clocks: &Clocks) -> Hertz { + T::Bus::clock(clocks) + } +} + +impl BusTimerClock for T +where + T: RccBus, + T::Bus: BusTimerClock, +{ + fn timer_clock(clocks: &Clocks) -> Hertz { + T::Bus::timer_clock(clocks) + } +} + +impl BusTimerClock for APB1R1 { + fn timer_clock(clocks: &Clocks) -> Hertz { + let pclk_mul = if clocks.ppre1 == 1 { 1 } else { 2 }; + Hertz::from_raw(clocks.pclk1.raw() * pclk_mul) + } +} + +impl BusTimerClock for APB1R2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + let pclk_mul = if clocks.ppre1 == 1 { 1 } else { 2 }; + Hertz::from_raw(clocks.pclk1.raw() * pclk_mul) + } +} + +impl BusTimerClock for APB2 { + fn timer_clock(clocks: &Clocks) -> Hertz { + let pclk_mul = if clocks.ppre2 == 1 { 1 } else { 2 }; + Hertz::from_raw(clocks.pclk2.raw() * pclk_mul) + } +} + +/// Enable/disable peripheral +pub trait Enable: RccBus { + /// Enables peripheral + fn enable(bus: &mut Self::Bus); + + /// Disables peripheral + fn disable(bus: &mut Self::Bus); + + /// Check if peripheral enabled + fn is_enabled() -> bool; + + /// Check if peripheral disabled + fn is_disabled() -> bool; + + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn enable_unchecked(); + + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn disable_unchecked(); +} + +/// Enable/disable peripheral in sleep mode +pub trait SMEnable: RccBus { + /// Enables peripheral + fn enable_in_sleep_mode(bus: &mut Self::Bus); + + /// Disables peripheral + fn disable_in_sleep_mode(bus: &mut Self::Bus); + + /// Check if peripheral enabled + fn is_enabled_in_sleep_mode() -> bool; + + /// Check if peripheral disabled + fn is_disabled_in_sleep_mode() -> bool; + + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn enable_in_sleep_mode_unchecked(); + + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn disable_in_sleep_mode_unchecked(); +} + +/// Reset peripheral +pub trait Reset: RccBus { + /// Resets peripheral + fn reset(bus: &mut Self::Bus); + + /// # Safety + /// + /// Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked(); +} + +#[derive(Debug, PartialEq)] +/// HSE Configuration +struct HseConfig { + /// Clock speed of HSE + speed: u32, + /// If the clock driving circuitry is bypassed i.e. using an oscillator, not a crystal or + /// resonator + bypass: CrystalBypass, + /// Clock Security System enable/disable + css: ClockSecuritySystem, +} + +#[derive(Debug, PartialEq)] +/// LSE Configuration +struct LseConfig { + /// If the clock driving circuitry is bypassed i.e. using an oscillator, not a crystal or + /// resonator + bypass: CrystalBypass, + /// Clock Security System enable/disable + css: ClockSecuritySystem, +} + +/// Crystal bypass selector +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CrystalBypass { + /// If the clock driving circuitry is bypassed i.e. using an oscillator + Enable, + /// If the clock driving circuitry is not bypassed i.e. using a crystal or resonator + Disable, +} + +/// Clock Security System (CSS) selector +/// +/// When this is enabled on HSE it will fire of the NMI interrupt on failure and for the LSE the +/// MCU will be woken if in Standby and then the LSECSS interrupt will fire. See datasheet on how +/// to recover for CSS failures. +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ClockSecuritySystem { + /// Enable the clock security system to detect clock failures + Enable, + /// Leave the clock security system disabled + Disable, +} + +const HSI: u32 = 16_000_000; // Hz + +/// Clock configuration +pub struct CFGR { + hse: Option, + lse: Option, + msi: Option, + hsi48: bool, + lsi: bool, + hclk: Option, + pclk1: Option, + pclk2: Option, + sysclk: Option, + pll_source: Option, + pll_config: Option, +} + +impl CFGR { + /// Add an HSE to the system + pub fn hse(mut self, freq: Hertz, bypass: CrystalBypass, css: ClockSecuritySystem) -> Self { + self.hse = Some(HseConfig { + speed: freq.raw(), + bypass, + css, + }); + + self + } + + /// Add an 32.768 kHz LSE to the system + pub fn lse(mut self, bypass: CrystalBypass, css: ClockSecuritySystem) -> Self { + self.lse = Some(LseConfig { bypass, css }); + + self + } + + /// Sets a frequency for the AHB bus + pub fn hclk(mut self, freq: Hertz) -> Self { + self.hclk = Some(freq.raw()); + self + } + + /// Enable the 48 MHz USB, RNG, SDMMC HSI clock source. Not available on all stm32l4x6 series + pub fn hsi48(mut self, on: bool) -> Self { + self.hsi48 = on; + self + } + + /// Enables the MSI with the specified speed + pub fn msi(mut self, range: MsiFreq) -> Self { + self.msi = Some(range); + self + } + + /// Sets LSI clock on (the default) or off + pub fn lsi(mut self, on: bool) -> Self { + self.lsi = on; + self + } + + /// Sets a frequency for the APB1 bus + pub fn pclk1(mut self, freq: Hertz) -> Self { + self.pclk1 = Some(freq.raw()); + self + } + + /// Sets a frequency for the APB2 bus + pub fn pclk2(mut self, freq: Hertz) -> Self { + self.pclk2 = Some(freq.raw()); + self + } + + /// Sets the system (core) frequency + pub fn sysclk(mut self, freq: Hertz) -> Self { + self.sysclk = Some(freq.raw()); + self + } + + /// Sets the system (core) frequency with some pll configuration + pub fn sysclk_with_pll(mut self, freq: Hertz, cfg: PllConfig) -> Self { + self.pll_config = Some(cfg); + self.sysclk = Some(freq.raw()); + self + } + + /// Sets the PLL source + pub fn pll_source(mut self, source: PllSource) -> Self { + self.pll_source = Some(source); + self + } + + /// Freezes the clock configuration, making it effective + pub fn freeze(&self, acr: &mut ACR, pwr: &mut Pwr) -> Clocks { + let rcc = unsafe { &*RCC::ptr() }; + + // Switch to MSI to prevent problems with PLL configuration. + if rcc.cr.read().msion().bit_is_clear() { + // Turn on MSI and configure it to 4MHz. + rcc.cr.modify(|_, w| { + w.msirgsel().set_bit(); // MSI Range is provided by MSIRANGE[3:0]. + w.msirange().range4m(); + w.msipllen().clear_bit(); + w.msion().set_bit() + }); + + // Wait until MSI is running + while rcc.cr.read().msirdy().bit_is_clear() {} + } + if rcc.cfgr.read().sws().bits() != 0 { + // Set MSI as a clock source, reset prescalers. + rcc.cfgr.reset(); + // Wait for clock switch status bits to change. + while rcc.cfgr.read().sws().bits() != 0 {} + } + + // + // 1. Setup clocks + // + + // Turn on the internal 32 kHz LSI oscillator + let lsi_used = match (self.lsi, &self.lse) { + (true, _) + | ( + _, + &Some(LseConfig { + bypass: _, + css: ClockSecuritySystem::Enable, + }), + ) => { + rcc.csr.modify(|_, w| w.lsion().set_bit()); + + // Wait until LSI is running + while rcc.csr.read().lsirdy().bit_is_clear() {} + + true + } + _ => false, + }; + + if let Some(lse_cfg) = &self.lse { + // 1. Unlock the backup domain + pwr.cr1.reg().modify(|_, w| w.dbp().set_bit()); + + // 2. Setup the LSE + rcc.bdcr.modify(|_, w| { + w.lseon().set_bit(); // Enable LSE + + if lse_cfg.bypass == CrystalBypass::Enable { + w.lsebyp().set_bit(); + } else { + unsafe { + w.lsedrv().bits(0b11); + } // Max drive strength, TODO: should probably be settable + } + + w + }); + + // Wait until LSE is running + while rcc.bdcr.read().lserdy().bit_is_clear() {} + + // Setup CSS + if lse_cfg.css == ClockSecuritySystem::Enable { + // Enable CSS and interrupt + rcc.bdcr.modify(|_, w| w.lsecsson().set_bit()); + rcc.cier.modify(|_, w| w.lsecssie().set_bit()); + } + } + + // If HSE is available, set it up + if let Some(hse_cfg) = &self.hse { + rcc.cr.write(|w| { + w.hseon().set_bit(); + + if hse_cfg.bypass == CrystalBypass::Enable { + w.hsebyp().set_bit(); + } + + w + }); + + while rcc.cr.read().hserdy().bit_is_clear() {} + + // Setup CSS + if hse_cfg.css == ClockSecuritySystem::Enable { + // Enable CSS + rcc.cr.modify(|_, w| w.csson().set_bit()); + } + } + + if let Some(msi) = self.msi { + unsafe { + rcc.cr.modify(|_, w| { + w.msirange() + .bits(msi as u8) + .msirgsel() + .set_bit() + .msion() + .set_bit(); + + // If LSE is enabled, enable calibration of MSI + if self.lse.is_some() { + w.msipllen().set_bit(); + } + + w + }) + }; + + // Wait until MSI is running + while rcc.cr.read().msirdy().bit_is_clear() {} + } + + // Turn on USB, RNG Clock using the HSI48 CLK source + if self.hsi48 { + // p. 180 in ref-manual + rcc.crrcr.modify(|_, w| w.hsi48on().set_bit()); + + // Wait until HSI48 is running + while rcc.crrcr.read().hsi48rdy().bit_is_clear() {} + } + + // Select MSI as clock source for usb48, rng ... + if let Some(MsiFreq::RANGE48M) = self.msi { + #[allow(unused_unsafe)] + unsafe { + rcc.ccipr.modify(|_, w| w.clk48sel().bits(0b11)) + }; + } + + // + // 2. Setup PLL + // + + // Select PLL source + let (clock_speed, pll_source) = if let Some(source) = self.pll_source { + match source { + PllSource::HSE => { + if let Some(hse) = &self.hse { + (hse.speed, source) + } else { + panic!("HSE selected as PLL source, but not enabled"); + } + } + PllSource::HSI16 => (HSI, source), + PllSource::MSI => { + if let Some(msi) = self.msi { + (msi.to_hertz().raw(), source) + } else { + panic!("MSI selected as PLL source, but not enabled"); + } + } + } + } else { + // No specific PLL source selected, do educated guess + + // 1. HSE + if let Some(hse) = &self.hse { + (hse.speed, PllSource::HSE) + } + // 2. MSI + else if let Some(msi) = self.msi { + (msi.to_hertz().raw(), PllSource::MSI) + } + // 3. HSI as fallback + else { + (HSI, PllSource::HSI16) + } + }; + + // Check if HSI should be started + if pll_source == PllSource::HSI16 || (self.msi.is_none() && self.hse.is_none()) { + rcc.cr.write(|w| w.hsion().set_bit()); + while rcc.cr.read().hsirdy().bit_is_clear() {} + } + + let pllconf = if self.pll_config.is_none() { + if let Some(sysclk) = self.sysclk { + // Calculate PLL multiplier and create a best effort pll config, just multiply n + let plln = (2 * sysclk) / clock_speed; + + Some(PllConfig::new(1, plln as u8, PllDivider::Div2)) + } else { + None + } + } else { + self.pll_config + }; + + let sysclk = match (self.sysclk, self.msi) { + (Some(sysclk), _) => sysclk, + (None, Some(msi)) => msi.to_hertz().raw(), + (None, None) => MsiFreq::RANGE4M.to_hertz().raw(), + }; + + assert!(sysclk <= 80_000_000); + + let (hpre_bits, hpre_div) = self + .hclk + .map(|hclk| match sysclk / hclk { + // From p 194 in RM0394 + 0 => unreachable!(), + 1 => (0b0000, 1), + 2 => (0b1000, 2), + 3..=5 => (0b1001, 4), + 6..=11 => (0b1010, 8), + 12..=39 => (0b1011, 16), + 40..=95 => (0b1100, 64), + 96..=191 => (0b1101, 128), + 192..=383 => (0b1110, 256), + _ => (0b1111, 512), + }) + .unwrap_or((0b0000, 1)); + + let hclk = sysclk / hpre_div; + + assert!(hclk <= sysclk); + + let (ppre1_bits, ppre1) = self + .pclk1 + .map(|pclk1| match hclk / pclk1 { + // From p 194 in RM0394 + 0 => unreachable!(), + 1 => (0b000, 1), + 2 => (0b100, 2), + 3..=5 => (0b101, 4), + 6..=11 => (0b110, 8), + _ => (0b111, 16), + }) + .unwrap_or((0b000, 1)); + + let pclk1: u32 = hclk / u32::from(ppre1); + + assert!(pclk1 <= sysclk); + + let (ppre2_bits, ppre2) = self + .pclk2 + .map(|pclk2| match hclk / pclk2 { + // From p 194 in RM0394 + 0 => unreachable!(), + 1 => (0b000, 1), + 2 => (0b100, 2), + 3..=5 => (0b101, 4), + 6..=11 => (0b110, 8), + _ => (0b111, 16), + }) + .unwrap_or((0b000, 1)); + + let pclk2: u32 = hclk / u32::from(ppre2); + + // RM0394 Rev 4, page 188 + // 6.2.14 Timer clock + // + // The timer clock frequencies are automatically defined by hardware. There are two cases: + // 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same + // frequency as that of the APB domain. + // 2. Otherwise, they are set to twice (×2) the frequency of the APB domain. + let timclk1 = if ppre1 == 1 { pclk1 } else { 2 * pclk1 }; + let timclk2 = if ppre2 == 1 { pclk2 } else { 2 * pclk2 }; + + assert!(pclk2 <= sysclk); + + // adjust flash wait states + unsafe { + acr.acr().write(|w| { + w.latency().bits(if hclk <= 16_000_000 { + 0b000 + } else if hclk <= 32_000_000 { + 0b001 + } else if hclk <= 48_000_000 { + 0b010 + } else if hclk <= 64_000_000 { + 0b011 + } else { + 0b100 + }) + }) + } + + let sysclk_src_bits; + let mut msi = self.msi; + if let Some(pllconf) = pllconf { + // Sanity-checks per RM0394, 6.4.4 PLL configuration register (RCC_PLLCFGR) + let r = pllconf.r.to_division_factor(); + let clock_speed = clock_speed / (pllconf.m as u32 + 1); + let vco = clock_speed * pllconf.n as u32; + let output_clock = vco / r; + + assert!(r <= 8); // Allowed max output divider + assert!(pllconf.n >= 8); // Allowed min multiplier + assert!(pllconf.n <= 86); // Allowed max multiplier + assert!(clock_speed >= 4_000_000); // VCO input clock min + assert!(clock_speed <= 16_000_000); // VCO input clock max + assert!(vco >= 64_000_000); // VCO output min + assert!(vco <= 334_000_000); // VCO output max + assert!(output_clock <= 80_000_000); // Max output clock + + // use PLL as source + sysclk_src_bits = 0b11; + rcc.cr.modify(|_, w| w.pllon().clear_bit()); + while rcc.cr.read().pllrdy().bit_is_set() {} + + let pllsrc_bits = pll_source.to_pllsrc(); + + rcc.pllcfgr.modify(|_, w| unsafe { + w.pllsrc() + .bits(pllsrc_bits) + .pllm() + .bits(pllconf.m) + .pllr() + .bits(pllconf.r.to_bits()) + .plln() + .bits(pllconf.n) + }); + + rcc.cr.modify(|_, w| w.pllon().set_bit()); + + while rcc.cr.read().pllrdy().bit_is_clear() {} + + rcc.pllcfgr.modify(|_, w| w.pllren().set_bit()); + + // SW: PLL selected as system clock + rcc.cfgr.modify(|_, w| unsafe { + w.ppre2() + .bits(ppre2_bits) + .ppre1() + .bits(ppre1_bits) + .hpre() + .bits(hpre_bits) + .sw() + .bits(sysclk_src_bits) + }); + } else { + // use MSI as fallback source for sysclk + sysclk_src_bits = 0b00; + if msi.is_none() { + msi = Some(MsiFreq::RANGE4M); + } + + // SW: MSI selected as system clock + rcc.cfgr.write(|w| unsafe { + w.ppre2() + .bits(ppre2_bits) + .ppre1() + .bits(ppre1_bits) + .hpre() + .bits(hpre_bits) + .sw() + .bits(sysclk_src_bits) + }); + } + + while rcc.cfgr.read().sws().bits() != sysclk_src_bits {} + + // + // 3. Shutdown unused clocks that have auto-started + // + + // MSI always starts on reset + if msi.is_none() { + rcc.cr + .modify(|_, w| w.msion().clear_bit().msipllen().clear_bit()) + } + + // + // 4. Clock setup done! + // + + Clocks { + hclk: hclk.Hz(), + lsi: lsi_used, + lse: self.lse.is_some(), + msi, + hsi48: self.hsi48, + pclk1: pclk1.Hz(), + pclk2: pclk2.Hz(), + ppre1, + ppre2, + sysclk: sysclk.Hz(), + timclk1: timclk1.Hz(), + timclk2: timclk2.Hz(), + pll_source: pllconf.map(|_| pll_source), + } + } +} + +#[derive(Clone, Copy, Debug)] +/// PLL output divider options +pub enum PllDivider { + /// Divider PLL output by 2 + Div2 = 0b00, + /// Divider PLL output by 4 + Div4 = 0b01, + /// Divider PLL output by 6 + Div6 = 0b10, + /// Divider PLL output by 8 + Div8 = 0b11, +} + +impl PllDivider { + #[inline(always)] + fn to_bits(self) -> u8 { + self as u8 + } + + #[inline(always)] + fn to_division_factor(self) -> u32 { + match self { + Self::Div2 => 2, + Self::Div4 => 4, + Self::Div6 => 6, + Self::Div8 => 8, + } + } +} + +#[derive(Clone, Copy, Debug)] +/// PLL Configuration +pub struct PllConfig { + // Main PLL division factor + m: u8, + // Main PLL multiplication factor + n: u8, + // Main PLL division factor for PLLCLK (system clock) + r: PllDivider, +} + +impl PllConfig { + /// Create a new PLL config from manual settings + /// + /// PLL output = ((SourceClk / input_divider) * multiplier) / output_divider + pub fn new(input_divider: u8, multiplier: u8, output_divider: PllDivider) -> Self { + assert!(input_divider > 0); + + PllConfig { + m: input_divider - 1, + n: multiplier, + r: output_divider, + } + } +} + +#[derive(Clone, Copy, Debug, PartialEq)] +/// PLL Source +pub enum PllSource { + /// Multi-speed internal clock + MSI, + /// High-speed internal clock + HSI16, + /// High-speed external clock + HSE, +} + +impl PllSource { + fn to_pllsrc(self) -> u8 { + match self { + Self::MSI => 0b01, + Self::HSI16 => 0b10, + Self::HSE => 0b11, + } + } +} + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no longer be changed +#[derive(Clone, Copy, Debug)] +pub struct Clocks { + hclk: Hertz, + hsi48: bool, + msi: Option, + lsi: bool, + lse: bool, + pclk1: Hertz, + pclk2: Hertz, + ppre1: u8, + ppre2: u8, + sysclk: Hertz, + timclk1: Hertz, + timclk2: Hertz, + pll_source: Option, +} + +impl Clocks { + /// Returns the frequency of the AHB + pub fn hclk(&self) -> Hertz { + self.hclk + } + + /// Returns status of HSI48 + pub fn hsi48(&self) -> bool { + self.hsi48 + } + + // Returns the status of the MSI + pub fn msi(&self) -> Option { + self.msi + } + + /// Returns status of the LSI + pub fn lsi(&self) -> bool { + self.lsi + } + + // Return the status of the LSE + pub fn lse(&self) -> bool { + self.lse + } + + /// Returns the frequency of the APB1 + pub fn pclk1(&self) -> Hertz { + self.pclk1 + } + + /// Returns the frequency of the APB2 + pub fn pclk2(&self) -> Hertz { + self.pclk2 + } + + /// Get which source is being used for PLL + pub fn pll_source(&self) -> Option { + self.pll_source + } + + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn ppre1(&self) -> u8 { + self.ppre1 + } + // TODO remove `allow` + #[allow(dead_code)] + pub(crate) fn ppre2(&self) -> u8 { + self.ppre2 + } + + /// Returns the system (core) frequency + pub fn sysclk(&self) -> Hertz { + self.sysclk + } + + /// Returns the frequency for timers on APB1 + pub fn timclk1(&self) -> Hertz { + self.timclk1 + } + + /// Returns the frequency for timers on APB2 + pub fn timclk2(&self) -> Hertz { + self.timclk2 + } +} diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index f843f521..6c549ca4 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -39,9 +39,93 @@ //! though I2S or SAI are available. On the STM32F410, the I2S clock is generated by the main PLL, //! and on the STM32F413/423 SAI clocks are generated by the I2S PLL. On these MCUs, the actual //! frequencies may substantially deviate from the requested frequencies. +/* +#[cfg(feature = "c0")] +mod c0; +#[cfg(feature = "c0")] +pub use c0::*; +*/ +#[cfg(feature = "f0")] +mod f0; +#[cfg(feature = "f0")] +pub use f0::*; +/* +#[cfg(feature = "f2")] +mod f2; +#[cfg(feature = "f2")] +pub use f2::*; +*/ +#[cfg(feature = "f3")] +mod f3; +#[cfg(feature = "f3")] +pub use f3::*; + +#[cfg(feature = "f4")] mod f4; +#[cfg(feature = "f4")] pub use f4::*; +#[cfg(feature = "f7")] +mod f7; +#[cfg(feature = "f7")] +pub use f7::*; +/* +#[cfg(feature = "g0")] +mod g0; +#[cfg(feature = "g0")] +pub use g0::*; +*/ +#[cfg(feature = "g4")] +mod g4; +#[cfg(feature = "g4")] +pub use g4::*; +/* +#[cfg(feature = "h7")] +mod h7; +#[cfg(feature = "h7")] +pub use h7::*; + +#[cfg(feature = "l0")] +mod l0; +#[cfg(feature = "l0")] +pub use l0::*; + +#[cfg(feature = "l1")] +mod l1; +#[cfg(feature = "l1")] +pub use l1::*; +*/ +#[cfg(feature = "l4")] +mod l4; +#[cfg(feature = "l4")] +pub use l4::*; +/* +#[cfg(feature = "l4p")] +mod l4p; +#[cfg(feature = "l4p")] +pub use l4p::*; + +#[cfg(feature = "l5")] +mod l5; +#[cfg(feature = "l5")] +pub use l5::*; + +#[cfg(feature = "u5")] +mod u5; +#[cfg(feature = "u5")] +pub use u5::*; + +#[cfg(feature = "wl")] +mod wl; +#[cfg(feature = "wl")] +pub use wl::*; + +#[cfg(feature = "wb")] +mod wb; +#[cfg(feature = "wb")] +pub use wb::*; +*/ + use fugit::HertzU32 as Hertz; /// Bus associated to peripheral diff --git a/src/sai.rs b/src/sai.rs index b093f557..150b4d3e 100644 --- a/src/sai.rs +++ b/src/sai.rs @@ -22,7 +22,6 @@ use core::ops::Deref; use crate::gpio::alt::SaiChannel; -use crate::pac::RCC; #[cfg(feature = "sai2")] use crate::pac::SAI2; #[cfg(any( @@ -32,7 +31,12 @@ use crate::pac::SAI2; feature = "stm32f439" ))] use crate::pac::{sai, SAI as SAI1}; -#[cfg(any(feature = "stm32f427", feature = "stm32f437", feature = "stm32f446"))] +#[cfg(any( + feature = "f7", + feature = "stm32f427", + feature = "stm32f437", + feature = "stm32f446" +))] use crate::pac::{sai1 as sai, SAI1}; use crate::rcc; use crate::time::Hertz; @@ -539,9 +543,10 @@ where where Self: Sized, { - let rcc = unsafe { &*RCC::ptr() }; - SAI::enable(rcc); - SAI::reset(rcc); + unsafe { + SAI::enable_unchecked(); + SAI::reset_unchecked(); + } ( SubBlock { channel: SAIA::new(self), @@ -565,9 +570,10 @@ where where Self: Sized, { - let rcc = unsafe { &*RCC::ptr() }; - SAI::enable(rcc); - SAI::reset(rcc); + unsafe { + SAI::enable_unchecked(); + SAI::reset_unchecked(); + } ( SubBlock { channel: SAIA::new(self), @@ -591,9 +597,10 @@ where where Self: Sized, { - let rcc = unsafe { &*RCC::ptr() }; - SAI::enable(rcc); - SAI::reset(rcc); + unsafe { + SAI::enable_unchecked(); + SAI::reset_unchecked(); + } ( SubBlock { channel: SAIA::new(self), diff --git a/src/serial.rs b/src/serial.rs index d4192bb2..f33ce242 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -30,6 +30,7 @@ use crate::pac; use crate::gpio::NoPin; use crate::rcc::Clocks; +#[cfg(feature = "dma")] pub mod dma; /// Serial error kind @@ -294,12 +295,25 @@ macro_rules! halUsart { } pub(crate) use halUsart; +#[cfg(feature = "usart1")] halUsart! { pac::USART1, Serial1, Rx1, Tx1 } +#[cfg(feature = "usart2")] halUsart! { pac::USART2, Serial2, Rx2, Tx2 } -halUsart! { pac::USART6, Serial6, Rx6, Tx6 } - #[cfg(feature = "usart3")] +#[cfg(not(feature = "l4"))] halUsart! { pac::USART3, Serial3, Rx3, Tx3 } +#[cfg(feature = "usart4")] +halUsart! { pac::USART4, Serial4, Rx4, Tx4 } +#[cfg(feature = "usart5")] +halUsart! { pac::USART5, Serial5, Rx5, Tx5 } +#[cfg(feature = "usart6")] +halUsart! { pac::USART6, Serial6, Rx6, Tx6 } +#[cfg(feature = "usart7")] +halUsart! { pac::USART7, Serial7, Rx7, Tx7 } +#[cfg(feature = "usart8")] +halUsart! { pac::USART8, Serial8, Rx8, Tx8 } +#[cfg(feature = "usart10")] +halUsart! { pac::USART10, Serial10, Rx10, Tx10 } impl Rx { pub(crate) fn with_u16_data(self) -> Rx { diff --git a/src/serial/config.rs b/src/serial/config.rs index 49804142..a7084d5c 100644 --- a/src/serial/config.rs +++ b/src/serial/config.rs @@ -4,6 +4,8 @@ use crate::time::U32Ext; #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum WordLength { + #[cfg(feature = "uart_v3")] + DataBits7, DataBits8, DataBits9, } diff --git a/src/serial/dma.rs b/src/serial/dma.rs index 4d36c38b..26770882 100644 --- a/src/serial/dma.rs +++ b/src/serial/dma.rs @@ -594,7 +594,7 @@ where { #[inline(always)] fn address(&self) -> u32 { - ::peri_address() + ::rx_peri_address() } type MemSize = u8; @@ -606,7 +606,7 @@ where { #[inline(always)] fn address(&self) -> u32 { - ::peri_address() + ::tx_peri_address() } type MemSize = u8; diff --git a/src/serial/uart_impls.rs b/src/serial/uart_impls.rs index 7a5c7bb9..a8ddc4eb 100644 --- a/src/serial/uart_impls.rs +++ b/src/serial/uart_impls.rs @@ -6,6 +6,7 @@ use nb::block; use super::{ config, CFlag, Error, Event, Flag, Rx, RxISR, RxListen, Serial, SerialExt, Tx, TxISR, TxListen, }; +#[cfg(feature = "dma")] use crate::dma::{ traits::{DMASet, PeriAddress}, MemoryToPeripheral, PeripheralToMemory, @@ -18,6 +19,7 @@ pub(crate) use crate::pac::uart4::RegisterBlock as RegisterBlockUart; pub(crate) use crate::pac::usart1::RegisterBlock as RegisterBlockUsart; #[cfg(feature = "uart4")] +#[cfg(not(feature = "f7"))] impl crate::Sealed for RegisterBlockUart {} impl crate::Sealed for RegisterBlockUsart {} @@ -36,8 +38,13 @@ pub trait Instance: fn set_stopbits(&self, bits: config::StopBits); #[doc(hidden)] #[inline(always)] - fn peri_address() -> u32 { - unsafe { &*Self::ptr() }.peri_address() + fn tx_peri_address() -> u32 { + unsafe { &*Self::ptr() }.tx_peri_address() + } + #[doc(hidden)] + #[inline(always)] + fn rx_peri_address() -> u32 { + unsafe { &*Self::ptr() }.rx_peri_address() } } @@ -143,8 +150,11 @@ pub trait RegisterBlockImpl: crate::Sealed { self.listen_event(Some(Event::TxEmpty.into()), None) } - // PeriAddress - fn peri_address(&self) -> u32; + // PeriAddress for transfer data + fn tx_peri_address(&self) -> u32; + + // PeriAddress for receive data + fn rx_peri_address(&self) -> u32; fn enable_dma(&self, dc: config::DmaConfig); @@ -155,9 +165,13 @@ macro_rules! uartCommon { () => { fn read_u16(&self) -> nb::Result { // NOTE(unsafe) atomic read with no side effects + #[cfg(feature = "uart_v2")] let sr = self.sr().read(); + #[cfg(feature = "uart_v3")] + let sr = self.isr().read(); // Any error requires the dr to be read to clear + #[cfg(feature = "uart_v2")] if sr.pe().bit_is_set() || sr.fe().bit_is_set() || sr.nf().bit_is_set() @@ -166,17 +180,30 @@ macro_rules! uartCommon { self.dr().read(); } + #[cfg(feature = "uart_v3")] + let icr = self.icr(); Err(if sr.pe().bit_is_set() { + #[cfg(feature = "uart_v3")] + icr.write(|w| w.pecf().clear()); Error::Parity.into() } else if sr.fe().bit_is_set() { + #[cfg(feature = "uart_v3")] + icr.write(|w| w.fecf().clear()); Error::FrameFormat.into() } else if sr.nf().bit_is_set() { + #[cfg(feature = "uart_v3")] + icr.write(|w| w.ncf().clear()); Error::Noise.into() } else if sr.ore().bit_is_set() { + #[cfg(feature = "uart_v3")] + icr.write(|w| w.orecf().clear()); Error::Overrun.into() } else if sr.rxne().bit_is_set() { // NOTE(unsafe) atomic read from stateless register + #[cfg(feature = "uart_v2")] return Ok(self.dr().read().dr().bits()); + #[cfg(feature = "uart_v3")] + return Ok(self.rdr().read().rdr().bits()); } else { nb::Error::WouldBlock }) @@ -184,11 +211,17 @@ macro_rules! uartCommon { fn write_u16(&self, word: u16) -> nb::Result<(), Error> { // NOTE(unsafe) atomic read with no side effects + #[cfg(feature = "uart_v2")] let sr = self.sr().read(); + #[cfg(feature = "uart_v3")] + let sr = self.isr().read(); if sr.txe().bit_is_set() { // NOTE(unsafe) atomic write to stateless register + #[cfg(feature = "uart_v2")] self.dr().write(|w| w.dr().set(word)); + #[cfg(feature = "uart_v3")] + self.tdr().write(|w| w.tdr().set(word)); Ok(()) } else { Err(nb::Error::WouldBlock) @@ -197,7 +230,10 @@ macro_rules! uartCommon { fn flush(&self) -> nb::Result<(), Error> { // NOTE(unsafe) atomic read with no side effects + #[cfg(feature = "uart_v2")] let sr = self.sr().read(); + #[cfg(feature = "uart_v3")] + let sr = self.isr().read(); if sr.tc().bit_is_set() { Ok(()) @@ -207,23 +243,41 @@ macro_rules! uartCommon { } fn flags(&self) -> BitFlags { - BitFlags::from_bits_truncate(self.sr().read().bits()) + #[cfg(feature = "uart_v2")] + let sr = self.sr().read(); + #[cfg(feature = "uart_v3")] + let sr = self.isr().read(); + BitFlags::from_bits_truncate(sr.bits()) } fn clear_flags(&self, flags: BitFlags) { + #[cfg(feature = "uart_v2")] self.sr() .write(|w| unsafe { w.bits(0xffff & !flags.bits()) }); + #[cfg(feature = "uart_v3")] + self.icr().write(|w| unsafe { w.bits(flags.bits()) }); } fn clear_idle_interrupt(&self) { - let _ = self.sr().read(); - let _ = self.dr().read(); + #[cfg(feature = "uart_v2")] + { + let _ = self.sr().read(); + let _ = self.dr().read(); + } + #[cfg(feature = "uart_v3")] + self.icr().write(|w| w.idlecf().set_bit()); } fn check_and_clear_error_flags(&self) -> Result<(), Error> { + #[cfg(feature = "uart_v2")] let sr = self.sr().read(); + #[cfg(feature = "uart_v2")] let _ = self.dr().read(); + // TODO: clear flags + #[cfg(feature = "uart_v3")] + let sr = self.isr().read(); + if sr.ore().bit_is_set() { Err(Error::Overrun) } else if sr.nf().bit_is_set() { @@ -260,9 +314,23 @@ macro_rules! uartCommon { }); } - fn peri_address(&self) -> u32 { + #[cfg(feature = "uart_v2")] + fn rx_peri_address(&self) -> u32 { self.dr().as_ptr() as u32 } + #[cfg(feature = "uart_v2")] + fn tx_peri_address(&self) -> u32 { + self.dr().as_ptr() as u32 + } + + #[cfg(feature = "uart_v3")] + fn rx_peri_address(&self) -> u32 { + self.rdr().as_ptr() as u32 + } + #[cfg(feature = "uart_v3")] + fn tx_peri_address(&self) -> u32 { + self.tdr().as_ptr() as u32 + } fn enable_dma(&self, dc: config::DmaConfig) { use config::DmaConfig; @@ -384,12 +452,22 @@ where { // Enable transmission and receiving // and configure frame + // M[1:0] are used to set data bits + // M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits + // M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits + // M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits uart.cr1().write(|w| { w.ue().set_bit(); w.over8().bit(over8); w.te().set_bit(); w.re().set_bit(); + #[cfg(feature = "uart_v2")] w.m().bit(config.wordlength == WordLength::DataBits9); + #[cfg(feature = "uart_v3")] + { + w.m0().bit(config.wordlength == WordLength::DataBits9); + w.m1().bit(config.wordlength == WordLength::DataBits7); + } w.pce().bit(config.parity != Parity::ParityNone); w.ps().bit(config.parity == Parity::ParityOdd) }); @@ -408,6 +486,7 @@ where { } #[cfg(feature = "uart4")] +#[cfg(not(feature = "f7"))] impl RegisterBlockImpl for RegisterBlockUart { fn new, WORD>( uart: UART, @@ -439,12 +518,22 @@ where { // Enable transmission and receiving // and configure frame + // M[1:0] are used to set data bits + // M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits + // M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits + // M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits uart.cr1().write(|w| { w.ue().set_bit(); w.over8().bit(over8); w.te().set_bit(); w.re().set_bit(); + #[cfg(feature = "uart_v2")] w.m().bit(config.wordlength == WordLength::DataBits9); + #[cfg(feature = "uart_v3")] + { + w.m0().bit(config.wordlength == WordLength::DataBits9); + w.m1().bit(config.wordlength == WordLength::DataBits7); + } w.pce().bit(config.parity != Parity::ParityNone); w.ps().bit(config.parity == Parity::ParityOdd) }); @@ -633,15 +722,17 @@ impl Serial { } } +#[cfg(feature = "dma")] unsafe impl PeriAddress for Rx { #[inline(always)] fn address(&self) -> u32 { - self.usart.peri_address() + self.usart.rx_peri_address() } type MemSize = u8; } +#[cfg(feature = "dma")] unsafe impl DMASet for Rx where @@ -649,15 +740,17 @@ where { } +#[cfg(feature = "dma")] unsafe impl PeriAddress for Tx { #[inline(always)] fn address(&self) -> u32 { - self.usart.peri_address() + self.usart.tx_peri_address() } type MemSize = u8; } +#[cfg(feature = "dma")] unsafe impl DMASet for Tx where diff --git a/src/signature.rs b/src/signature.rs index cc27a74a..c40857f3 100644 --- a/src/signature.rs +++ b/src/signature.rs @@ -5,7 +5,10 @@ use core::str::from_utf8_unchecked; /// This is the test voltage, in millivolts of the calibration done at the factory +#[cfg(any(feature = "f4", feature = "f7", feature = "g4"))] pub const VDDA_CALIB: u32 = 3300; +#[cfg(feature = "l4")] +pub const VDDA_CALIB_MV: u32 = 3000; macro_rules! define_ptr_type { ($name: ident, $ptr: expr) => { @@ -30,7 +33,12 @@ pub struct Uid { y: u16, waf_lot: [u8; 8], } +#[cfg(feature = "f4")] define_ptr_type!(Uid, 0x1FFF_7A10); +#[cfg(feature = "f7")] +define_ptr_type!(Uid, 0x1FF0_F420); +#[cfg(any(feature = "g4", feature = "l4"))] +define_ptr_type!(Uid, 0x1FFF_7590); impl Uid { /// X coordinate on wafer @@ -52,13 +60,23 @@ impl Uid { pub fn lot_num(&self) -> &str { unsafe { from_utf8_unchecked(&self.waf_lot[1..]) } } + + /// As a byte array + pub fn as_bytes() -> &'static [u8; 12] { + unsafe { &*(Self::ptr() as *const _) } + } } /// Size of integrated flash #[derive(Debug)] #[repr(C)] pub struct FlashSize(u16); +#[cfg(feature = "f4")] define_ptr_type!(FlashSize, 0x1FFF_7A22); +#[cfg(feature = "f7")] +define_ptr_type!(FlashSize, 0x1FF0_F442); +#[cfg(any(feature = "g4", feature = "l4"))] +define_ptr_type!(FlashSize, 0x1FFF_75E0); impl FlashSize { /// Read flash size in kilobytes @@ -76,7 +94,12 @@ impl FlashSize { #[derive(Debug)] #[repr(C)] pub struct VrefCal(u16); +#[cfg(feature = "f4")] define_ptr_type!(VrefCal, 0x1FFF_7A2A); +#[cfg(feature = "f7")] +define_ptr_type!(VrefCal, 0x1FF0_F44A); +#[cfg(any(feature = "g4", feature = "l4"))] +define_ptr_type!(VrefCal, 0x1FFF_75AA); impl VrefCal { /// Read calibration value @@ -86,11 +109,18 @@ impl VrefCal { } /// A temperature reading taken at 30°C stored at the factory +#[cfg(any(feature = "f4", feature = "f7"))] #[derive(Debug)] #[repr(C)] pub struct VtempCal30(u16); +#[cfg(feature = "f4")] define_ptr_type!(VtempCal30, 0x1FFF_7A2C); +#[cfg(feature = "f7")] +define_ptr_type!(VtempCal30, 0x1FF0_F44C); +#[cfg(feature = "g4")] +define_ptr_type!(VtempCal30, 0x1FFF_75A8); +#[cfg(any(feature = "f4", feature = "f7"))] impl VtempCal30 { /// Read calibration value pub fn read(&self) -> u16 { @@ -99,14 +129,77 @@ impl VtempCal30 { } /// A temperature reading taken at 110°C stored at the factory +#[cfg(any(feature = "f4", feature = "f7"))] #[derive(Debug)] #[repr(C)] pub struct VtempCal110(u16); +#[cfg(feature = "f4")] define_ptr_type!(VtempCal110, 0x1FFF_7A2E); +#[cfg(feature = "f7")] +define_ptr_type!(VtempCal110, 0x1FF0_F44E); +#[cfg(feature = "g4")] +define_ptr_type!(VtempCal110, 0x1FFF_75CA); +#[cfg(any(feature = "f4", feature = "f7"))] impl VtempCal110 { /// Read calibration value pub fn read(&self) -> u16 { self.0 } } + +/// A temperature reading taken at 30°C stored at the factory +/// aka TS_CAL1 in reference manual +#[cfg(feature = "l4")] +#[derive(Debug)] +#[repr(C)] +pub struct VtempCalLow(u16); +#[cfg(feature = "l4")] +define_ptr_type!(VtempCalLow, 0x1FFF_75A8); + +#[cfg(feature = "l4")] +impl VtempCalLow { + /// aka TS_CAL1_TEMP in reference manual + pub const TEMP_DEGREES: u16 = 30; + /// Read calibration value + pub fn read(&self) -> u16 { + self.0 + } +} + +/// A temperature reading taken at 130°C stored at the factory +/// aka TS_CAL2 in reference manual +#[cfg(feature = "l4")] +#[derive(Debug)] +#[repr(C)] +pub struct VtempCalHigh(u16); +#[cfg(feature = "l4")] +define_ptr_type!(VtempCalHigh, 0x1FFF_75CA); + +#[cfg(feature = "l4")] +impl VtempCalHigh { + /// aka TS_CAL2_TEMP in reference manual + /// Feature gate Required: this is 110 for L47x/L48x, 130 for other L4s according to + /// https://github.com/STMicroelectronics/STM32CubeL4/blob/5e1553e07706491bd11f4edd304e093b6e4b83a4/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h#L352-L356 + + // L47/L48 + #[cfg(any( + feature = "stm32l471", + feature = "stm32l475", + feature = "stm32l476", + feature = "stm32l486" + ))] + pub const TEMP_DEGREES: u16 = 110; + // else + #[cfg(not(any( + feature = "stm32l471", + feature = "stm32l475", + feature = "stm32l476", + feature = "stm32l486" + )))] + pub const TEMP_DEGREES: u16 = 130; + /// Read calibration value + pub fn read(&self) -> u16 { + self.0 + } +} diff --git a/src/signature_f3.rs b/src/signature_f3.rs new file mode 100644 index 00000000..a52bca4c --- /dev/null +++ b/src/signature_f3.rs @@ -0,0 +1,121 @@ +//! Device electronic signature +//! +//! (stored in flash memory) +use core::fmt; +use core::str; + +use core::convert::TryInto; + +macro_rules! define_ptr_type { + ($name: ident, $ptr: expr) => { + impl $name { + fn ptr() -> *const Self { + $ptr as *const _ + } + + /// Returns a wrapped reference to the value in flash memory + pub fn get() -> &'static Self { + unsafe { &*Self::ptr() } + } + } + }; +} + +/// Uniqure Device ID register +#[repr(C, packed)] +pub struct Uid { + x: u16, + y: u16, + waf: u8, + lot: [u8; 7], +} +define_ptr_type!(Uid, 0x1FFF_F7AC); + +#[cfg(feature = "defmt")] +impl defmt::Format for Uid { + fn format(&self, f: defmt::Formatter) { + defmt::write!( + f, + "Peripheral {{ x: {:x}, y: {:x}, waf: {}, lum: {}}}", + { self.x }, + { self.y }, + { self.waf }, + { self.lot_number() }, + ); + } +} + +impl fmt::Debug for Uid { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_struct("Uid") + .field("x", &self.x()) + .field("y", &self.y()) + .field("waf", &self.waf) + .field("lot", &self.lot_number()) + .finish() + } +} + +fn bcd_to_num(bcd_num: u16) -> u16 { + bcd_num + .to_ne_bytes() + .iter() + .enumerate() + .map(|(i, byte)| (i * 2, (*byte & 0xF0) >> 4, *byte & 0x0F)) + .map(|(i, high_nibble, low_nibble)| { + let i: u32 = i.try_into().unwrap_or_default(); // This should never overflow + u16::from(high_nibble) * 10u16.pow(i + 1) + u16::from(low_nibble) * 10u16.pow(i) + }) + .sum() +} + +impl Uid { + /// X coordinate on wafer in BCD format + pub fn x_bcd(&self) -> u16 { + self.x + } + + /// X coordinate on wafer + pub fn x(&self) -> u16 { + bcd_to_num(self.x) + } + + /// Y coordinate on wafer in BCD format + pub fn y_bcd(&self) -> u16 { + self.y + } + + /// Y coordinate on wafer + pub fn y(&self) -> u16 { + bcd_to_num(self.y) + } + + /// Wafer number + pub fn wafer_number(&self) -> u8 { + self.waf + } + + /// Lot number + pub fn lot_number(&self) -> &str { + // Lets ignore the last byte, because it is a '\0' character. + unsafe { str::from_utf8_unchecked(&self.lot[..6]) } + } +} + +/// Size of integrated flash +#[derive(Debug)] +#[repr(C)] +pub struct FlashSize(u16); +define_ptr_type!(FlashSize, 0x1FFF_F7CC); + +impl FlashSize { + /// Read flash size in kilobytes + pub fn kilo_bytes(&self) -> u16 { + self.0 + } + + /// Read flash size in bytes + pub fn bytes(&self) -> usize { + usize::from(self.kilo_bytes()) * 1024 + } +} diff --git a/src/spi.rs b/src/spi.rs index a689e9b9..4ba5807e 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -1,8 +1,10 @@ use core::marker::PhantomData; use core::ops::{Deref, DerefMut}; -use crate::dma::traits::{DMASet, PeriAddress}; -use crate::dma::{MemoryToPeripheral, PeripheralToMemory}; +use crate::dma::{ + traits::{DMASet, PeriAddress}, + MemoryToPeripheral, PeripheralToMemory, +}; use crate::gpio::{self, NoPin}; use crate::pac; @@ -67,7 +69,7 @@ pub type NoMosi = NoPin; #[enumflags2::bitflags] #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Eq, PartialEq, Copy, Clone)] -#[repr(u32)] +#[repr(u16)] pub enum Event { /// An error occurred. /// @@ -90,7 +92,7 @@ pub enum Event { #[enumflags2::bitflags] #[cfg_attr(feature = "defmt", derive(defmt::Format))] #[derive(Debug, Eq, PartialEq, Copy, Clone)] -#[repr(u32)] +#[repr(u16)] pub enum Flag { /// Receive buffer not empty RxNotEmpty = 1 << 0, @@ -125,18 +127,41 @@ pub const TransferModeNormal: bool = false; #[allow(non_upper_case_globals)] pub const TransferModeBidi: bool = true; +#[cfg(feature = "spi_v1")] pub trait FrameSize: Copy + Default { const DFF: bool; } +#[cfg(feature = "spi_v1")] impl FrameSize for u8 { const DFF: bool = false; } +#[cfg(feature = "spi_v1")] impl FrameSize for u16 { const DFF: bool = true; } +#[cfg(feature = "spi_v2")] +use crate::pac::spi1::cr2; +#[cfg(feature = "spi_v2")] +pub trait FrameSize: Copy + Default { + const FRXTH: cr2::FRXTH; + const DS: cr2::DS; +} + +#[cfg(feature = "spi_v2")] +impl FrameSize for u8 { + const FRXTH: cr2::FRXTH = cr2::FRXTH::Quarter; + const DS: cr2::DS = cr2::DS::EightBit; +} + +#[cfg(feature = "spi_v2")] +impl FrameSize for u16 { + const FRXTH: cr2::FRXTH = cr2::FRXTH::Half; + const DS: cr2::DS = cr2::DS::SixteenBit; +} + /// The bit format to send the data in #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum BitFormat { @@ -203,6 +228,16 @@ pub trait Instance: + rcc::BusClock + gpio::alt::SpiCommon { + #[doc(hidden)] + #[inline(always)] + fn rx_peri_address() -> u32 { + unsafe { &*Self::ptr() }.dr().as_ptr() as u32 + } + #[doc(hidden)] + #[inline(always)] + fn tx_peri_address() -> u32 { + unsafe { &*Self::ptr() }.dr().as_ptr() as u32 + } } // Implemented by all SPI instances @@ -222,19 +257,23 @@ macro_rules! spi { }; } +#[cfg(feature = "spi1")] spi! { pac::SPI1: Spi1, SpiSlave1 } +#[cfg(feature = "spi2")] +#[cfg(not(any( + //feature = "svd-f750", + feature = "svd-f7x6" +)))] spi! { pac::SPI2: Spi2, SpiSlave2 } - #[cfg(feature = "spi3")] +#[cfg(not(any(feature = "svd-f745", feature = "svd-f765")))] spi! { pac::SPI3: Spi3, SpiSlave3 } - #[cfg(feature = "spi4")] spi! { pac::SPI4: Spi4, SpiSlave4 } - #[cfg(feature = "spi5")] spi! { pac::SPI5: Spi5, SpiSlave5 } - #[cfg(feature = "spi6")] +#[cfg(not(any(feature = "svd-f745", feature = "svd-f765")))] spi! { pac::SPI6: Spi6, SpiSlave6 } pub trait SpiExt: Sized + Instance { @@ -360,11 +399,16 @@ impl SpiExt for SPI { impl Spi { pub fn init(self) -> Self { + #[cfg(feature = "spi_v2")] + self.spi + .cr2() + .modify(|_, w| w.frxth().variant(W::FRXTH).ds().variant(W::DS)); self.spi.cr1().modify(|_, w| { // bidimode: 2-line or 1-line unidirectional w.bidimode().bit(BIDI); w.bidioe().bit(BIDI); // data frame size + #[cfg(feature = "spi_v1")] w.dff().bit(W::DFF); // spe: enable the SPI bus w.spe().set_bit() @@ -376,11 +420,16 @@ impl Spi { impl SpiSlave { pub fn init(self) -> Self { + #[cfg(feature = "spi_v2")] + self.spi + .cr2() + .modify(|_, w| w.frxth().variant(W::FRXTH).ds().variant(W::DS)); self.spi.cr1().modify(|_, w| { // bidimode: 2-line or 1-line unidirectional w.bidimode().bit(BIDI); w.bidioe().bit(BIDI); // data frame size + #[cfg(feature = "spi_v1")] w.dff().bit(W::DFF); // spe: enable the SPI bus w.spe().set_bit() @@ -613,7 +662,7 @@ impl SpiSlave { } } -impl Spi { +impl Spi { /// Pre initializing the SPI bus. fn pre_init(self, mode: Mode, freq: Hertz, clock: Hertz) -> Self { // disable SS output @@ -631,6 +680,11 @@ impl Spi { _ => 0b111, }; + #[cfg(feature = "spi_v2")] + self.spi + .cr2() + .modify(|_, w| w.frxth().variant(W::FRXTH).ds().variant(W::DS)); + self.spi.cr1().write(|w| { w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition); w.cpol().bit(mode.polarity == Polarity::IdleHigh); @@ -645,16 +699,23 @@ impl Spi { w.ssi().set_bit(); w.rxonly().clear_bit(); // dff: 8 bit frames - w.dff().clear_bit() + #[cfg(feature = "spi_v1")] + w.dff().clear_bit(); + w }); self } } -impl SpiSlave { +impl SpiSlave { /// Pre initializing the SPI bus. fn pre_init(self, mode: Mode) -> Self { + #[cfg(feature = "spi_v2")] + self.spi + .cr2() + .modify(|_, w| w.frxth().variant(W::FRXTH).ds().variant(W::DS)); + self.spi.cr1().write(|w| { w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition); w.cpol().bit(mode.polarity == Polarity::IdleHigh); @@ -669,7 +730,9 @@ impl SpiSlave { w.ssi().set_bit(); w.rxonly().clear_bit(); // dff: 8 bit frames - w.dff().clear_bit() + #[cfg(feature = "spi_v1")] + w.dff().clear_bit(); + w }); self @@ -922,7 +985,7 @@ impl DmaBuilder { unsafe impl PeriAddress for Rx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*SPI::ptr()).dr().as_ptr() as u32 } + SPI::rx_peri_address() } type MemSize = u8; @@ -936,7 +999,7 @@ unsafe impl DMASet PeriAddress for Tx { #[inline(always)] fn address(&self) -> u32 { - unsafe { (*SPI::ptr()).dr().as_ptr() as u32 } + SPI::tx_peri_address() } type MemSize = u8; diff --git a/src/timer.rs b/src/timer.rs index 559ae782..ce2926be 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -9,9 +9,11 @@ use cortex_m::peripheral::syst::SystClkSource; use cortex_m::peripheral::SYST; use enumflags2::BitFlags; +#[cfg(feature = "bb")] use crate::bb; use crate::pac; +#[cfg(feature = "dma")] use crate::dma::traits::PeriAddress; use crate::rcc::{self, Clocks}; use fugit::HertzU32 as Hertz; @@ -523,7 +525,14 @@ macro_rules! hal { fn enable_channel(c: u8, b: bool) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { + #[cfg(feature = "bb")] unsafe { bb::write(tim.ccer(), c*4, b); } + #[cfg(not(feature = "bb"))] + tim.ccer().modify(|r,w| unsafe { if b { + w.bits(r.bits() | (1 << c*4)) + } else { + w.bits(r.bits() & !(1 << c*4)) + }}); } } @@ -531,7 +540,15 @@ macro_rules! hal { fn set_channel_polarity(c: u8, p: Polarity) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::CH_NUMBER { - unsafe { bb::write(tim.ccer(), c*4 + 1, p == Polarity::ActiveLow); } + let b = p == Polarity::ActiveLow; + #[cfg(feature = "bb")] + unsafe { bb::write(tim.ccer(), c*4 + 1, b); } + #[cfg(not(feature = "bb"))] + tim.ccer().modify(|r,w| unsafe { if b { + w.bits(r.bits() | (1 << (c*4 + 1))) + } else { + w.bits(r.bits() & !(1 << (c*4 + 1))) + }}); } } @@ -539,7 +556,15 @@ macro_rules! hal { fn set_nchannel_polarity(c: u8, p: Polarity) { let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::COMP_CH_NUMBER { - unsafe { bb::write(tim.ccer(), c*4 + 3, p == Polarity::ActiveLow); } + let b = p == Polarity::ActiveLow; + #[cfg(feature = "bb")] + unsafe { bb::write(tim.ccer(), c*4 + 3, b); } + #[cfg(not(feature = "bb"))] + tim.ccer().modify(|r,w| unsafe { if b { + w.bits(r.bits() | (1 << (c*4 + 3))) + } else { + w.bits(r.bits() & !(1 << (c*4 + 3))) + }}); } } } @@ -550,7 +575,14 @@ macro_rules! hal { let $aoe = (); let tim = unsafe { &*<$TIM>::ptr() }; if c < Self::COMP_CH_NUMBER { + #[cfg(feature = "bb")] unsafe { bb::write(tim.ccer(), c*4 + 2, b); } + #[cfg(not(feature = "bb"))] + tim.ccer().modify(|r,w| unsafe { if b { + w.bits(r.bits() | (1 << (c*4 + 2))) + } else { + w.bits(r.bits() & !(1 << (c*4 + 2))) + }}); } } fn set_dtg_value(value: u8) { @@ -565,11 +597,27 @@ macro_rules! hal { let tim = unsafe { &*<$TIM>::ptr() }; if !comp { if c < Self::CH_NUMBER { - unsafe { bb::write(tim.cr2(), c*2 + 8, s == IdleState::Set); } + let b = s == IdleState::Set; + #[cfg(feature = "bb")] + unsafe { bb::write(tim.cr2(), c*2 + 8, b); } + #[cfg(not(feature = "bb"))] + tim.cr2().modify(|r,w| unsafe { if b { + w.bits(r.bits() | (1 << (c*2 + 8))) + } else { + w.bits(r.bits() & !(1 << (c*2 + 8))) + }}); } } else { if c < Self::COMP_CH_NUMBER { - unsafe { bb::write(tim.cr2(), c*2 + 9, s == IdleState::Set); } + let b = s == IdleState::Set; + #[cfg(feature = "bb")] + unsafe { bb::write(tim.cr2(), c*2 + 9, b); } + #[cfg(not(feature = "bb"))] + tim.cr2().modify(|r,w| unsafe { if b { + w.bits(r.bits() | (1 << (c*2 + 9))) + } else { + w.bits(r.bits() & !(1 << (c*2 + 9))) + }}); } } } @@ -577,6 +625,7 @@ macro_rules! hal { )? with_pwm!($TIM: $cnum $(, $aoe)?); + #[cfg(feature = "dma")] unsafe impl PeriAddress for CCR<$TIM, C> { #[inline(always)] fn address(&self) -> u32 { @@ -599,6 +648,7 @@ use hal; macro_rules! with_dmar { ($TIM:ty, $memsize:ty) => { + #[cfg(feature = "dma")] unsafe impl PeriAddress for DMAR<$TIM> { #[inline(always)] fn address(&self) -> u32 { diff --git a/src/tsc.rs b/src/tsc.rs new file mode 100644 index 00000000..8c00163c --- /dev/null +++ b/src/tsc.rs @@ -0,0 +1,302 @@ +//! Touch sense controller +//! +//! From STM32 (https://www.st.com/content/ccc/resource/technical/document/application_note/9d/be/03/8c/5d/8c/49/50/DM00088471.pdf/files/DM00088471.pdf/jcr:content/translations/en.DM00088471.pdf): +//! +//! The Cs capacitance is a key parameter for sensitivity. For touchkey sensors, the Cs value is +//! usually comprised between 8.7nF to 22nF. For linear and rotary touch sensors, the value is +//! usually comprised between 47nF and 100nF. These values are given as reference for an +//! electrode fitting a human finger tip size across a few millimeters dielectric panel. + +use crate::gpio::gpiob::{PB4, PB5, PB6, PB7}; +use crate::gpio::{Alternate, OpenDrain}; +use crate::pac::TSC; +use crate::rcc::{Enable, Reset, AHB1}; + +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum Event { + /// Max count error + MaxCountError, + /// End of acquisition + EndOfAcquisition, +} + +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum Error { + /// Max count error + MaxCountError, + /// Wrong GPIO for reading - returns the ioccr register + InvalidPin(u32), +} + +pub trait SamplePin { + const GROUP: u32; + const OFFSET: u32; +} +impl SamplePin for PB4> { + const GROUP: u32 = 2; + const OFFSET: u32 = 0; +} +impl SamplePin for PB5> { + const GROUP: u32 = 2; + const OFFSET: u32 = 1; +} +impl SamplePin for PB6> { + const GROUP: u32 = 2; + const OFFSET: u32 = 2; +} +impl SamplePin for PB7> { + const GROUP: u32 = 2; + const OFFSET: u32 = 3; +} + +pub trait ChannelPin { + const GROUP: u32; + const OFFSET: u32; +} +impl ChannelPin for PB4> { + const GROUP: u32 = 2; + const OFFSET: u32 = 0; +} +impl ChannelPin for PB5> { + const GROUP: u32 = 2; + const OFFSET: u32 = 1; +} +impl ChannelPin for PB6> { + const GROUP: u32 = 2; + const OFFSET: u32 = 2; +} +impl ChannelPin for PB7> { + const GROUP: u32 = 2; + const OFFSET: u32 = 3; +} + +pub struct Tsc { + sample_pin: SPIN, + tsc: TSC, +} + +#[derive(Clone, Copy, Debug, PartialEq)] +pub struct Config { + pub clock_prescale: Option, + pub max_count_error: Option, + pub charge_transfer_high: Option, + pub charge_transfer_low: Option, + /// Spread spectrum deviation - a value between 0 and 128 + pub spread_spectrum_deviation: Option, +} + +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum ClockPrescaler { + Hclk = 0b000, + HclkDiv2 = 0b001, + HclkDiv4 = 0b010, + HclkDiv8 = 0b011, + HclkDiv16 = 0b100, + HclkDiv32 = 0b101, + HclkDiv64 = 0b110, + HclkDiv128 = 0b111, +} + +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum MaxCountError { + /// 000: 255 + U255 = 0b000, + /// 001: 511 + U511 = 0b001, + /// 010: 1023 + U1023 = 0b010, + /// 011: 2047 + U2047 = 0b011, + /// 100: 4095 + U4095 = 0b100, + /// 101: 8191 + U8191 = 0b101, + /// 110: 16383 + U16383 = 0b110, +} + +#[derive(Clone, Copy, Debug, PartialEq)] +/// How many tsc cycles are spent charging / discharging +pub enum ChargeDischargeTime { + C1 = 0b0000, + C2 = 0b0001, + C3 = 0b0010, + C4 = 0b0011, + C5 = 0b0100, + C6 = 0b0101, + C7 = 0b0110, + C8 = 0b0111, + C9 = 0b1000, + C10 = 0b1001, + C11 = 0b1010, + C12 = 0b1011, + C13 = 0b1100, + C14 = 0b1101, + C15 = 0b1110, + C16 = 0b1111, +} + +impl Tsc { + pub fn tsc(tsc: TSC, sample_pin: SPIN, ahb: &mut AHB1, cfg: Option) -> Self + where + SPIN: SamplePin, + { + /* Enable the peripheral clock */ + TSC::enable(ahb); + TSC::reset(ahb); + + let config = cfg.unwrap_or(Config { + clock_prescale: None, + max_count_error: None, + charge_transfer_high: None, + charge_transfer_low: None, + spread_spectrum_deviation: None, + }); + + tsc.cr.write(|w| unsafe { + w.ctph().bits( + config + .charge_transfer_high + .unwrap_or(ChargeDischargeTime::C2) as u8, + ); + w.ctpl().bits( + config + .charge_transfer_low + .unwrap_or(ChargeDischargeTime::C2) as u8, + ); + w.pgpsc() + .bits(config.clock_prescale.unwrap_or(ClockPrescaler::Hclk) as u8); + w.mcv() + .bits(config.max_count_error.unwrap_or(MaxCountError::U8191) as u8); + w.sse().bit(config.spread_spectrum_deviation.is_some()); + w.ssd() + .bits(config.spread_spectrum_deviation.unwrap_or(0u8)); + w.tsce().set_bit() + }); + + let bit_pos = SPIN::OFFSET + (4 * (SPIN::GROUP - 1)); + + // Schmitt trigger hysteresis on sample IOs + tsc.iohcr.write(|w| unsafe { w.bits(1 << bit_pos) }); + + // Set the sampling pin + tsc.ioscr.write(|w| unsafe { w.bits(1 << bit_pos) }); + + // set the acquisitiuon groups based of the channel pins, stm32l432xx only has group 2 + tsc.iogcsr.write(|w| w.g2e().set_bit()); + + // clear interrupt & flags + tsc.icr.write(|w| w.eoaic().set_bit().mceic().set_bit()); + + Tsc { tsc, sample_pin } + } + + /// Starts a charge acquisition + pub fn start(&self, _input: &mut PIN) + where + PIN: ChannelPin, + { + self.clear(Event::EndOfAcquisition); + self.clear(Event::MaxCountError); + + // discharge the caps ready for a new reading + self.tsc.cr.modify(|_, w| w.iodef().clear_bit()); + + let bit_pos = PIN::OFFSET + (4 * (PIN::GROUP - 1)); + + // Set the channel pin + self.tsc.ioccr.write(|w| unsafe { w.bits(1 << bit_pos) }); + + self.tsc.cr.modify(|_, w| w.start().set_bit()); + } + + /// Clear interrupt & flags + pub fn clear(&self, event: Event) { + match event { + Event::EndOfAcquisition => { + self.tsc.icr.write(|w| w.eoaic().set_bit()); + } + Event::MaxCountError => { + self.tsc.icr.write(|w| w.mceic().set_bit()); + } + } + } + + /// Blocks waiting for a acquisition to complete or for a Max Count Error + pub fn acquire(&self, input: &mut PIN) -> Result + where + PIN: ChannelPin, + { + // start the acq + self.start(input); + + let result = loop { + let isr = self.tsc.isr.read(); + if isr.eoaf().bit_is_set() { + self.tsc.icr.write(|w| w.eoaic().set_bit()); + break Ok(self.read_unchecked()); + } else if isr.mcef().bit_is_set() { + self.tsc.icr.write(|w| w.mceic().set_bit()); + break Err(Error::MaxCountError); + } + }; + self.tsc.ioccr.write(|w| unsafe { w.bits(0b0) }); // clear channel register + result + } + + /// Reads the tsc group 2 count register + pub fn read(&self, _input: &mut PIN) -> Result + where + PIN: ChannelPin, + { + let bit_pos = PIN::OFFSET + (4 * (PIN::GROUP - 1)); + // Read the current channel config + let channel = self.tsc.ioccr.read().bits(); + // if they are equal we have the right pin + if channel == (1 << bit_pos) { + Ok(self.read_unchecked()) + } else { + Err(Error::InvalidPin(channel)) + } + } + + /// Reads the tsc group 2 count register + /// WARNING, just returns the contents of the register! No validation of the correct pin + pub fn read_unchecked(&self) -> u16 { + self.tsc.iog2cr().read().cnt().bits() + } + + /// Is the tsc performing an aquisition + pub fn in_progress(&mut self) -> bool { + self.tsc.cr.read().start().bit_is_set() + } + + /// Enables an interrupt event + pub fn listen(&mut self, event: Event) { + match event { + Event::EndOfAcquisition => { + self.tsc.ier.modify(|_, w| w.eoaie().set_bit()); + } + Event::MaxCountError => { + self.tsc.ier.modify(|_, w| w.mceie().set_bit()); + } + } + } + + /// Disables an interrupt event + pub fn unlisten(&self, event: Event) { + match event { + Event::EndOfAcquisition => { + self.tsc.ier.modify(|_, w| w.eoaie().clear_bit()); + } + Event::MaxCountError => { + self.tsc.ier.modify(|_, w| w.mceie().clear_bit()); + } + } + } + + /// Releases the TSC peripheral and associated pins + pub fn free(self) -> (TSC, SPIN) { + (self.tsc, self.sample_pin) + } +} diff --git a/src/usb.rs b/src/usb.rs new file mode 100644 index 00000000..dd4a7f4c --- /dev/null +++ b/src/usb.rs @@ -0,0 +1,57 @@ +//! USB peripheral +//! +//! Requires the `stm32-usbd` feature. +//! +//! See +//! for usage examples. + +use crate::gpio::alt::usb as alt; +use crate::pac; +use crate::rcc::{Enable, Reset}; +use stm32_usbd::UsbPeripheral; + +pub use stm32_usbd::UsbBus; + +pub struct USB { + pub usb: pac::USB, + pub pin_dm: alt::Dm, + pub pin_dp: alt::Dp, +} + +impl USB { + pub fn new(usb: pac::USB, pins: (impl Into, impl Into)) -> Self { + Self { + usb, + pin_dm: pins.0.into(), + pin_dp: pins.1.into(), + } + } +} + +unsafe impl Sync for USB {} + +unsafe impl UsbPeripheral for USB { + const REGISTERS: *const () = pac::USB::ptr() as *const (); + const DP_PULL_UP_FEATURE: bool = true; + const EP_MEMORY: *const () = 0x4000_6c00 as _; + const EP_MEMORY_SIZE: usize = 1024; + const EP_MEMORY_ACCESS_2X16: bool = true; + + fn enable() { + cortex_m::interrupt::free(|_| unsafe { + // Enable USB peripheral + pac::USB::enable_unchecked(); + + // Reset USB peripheral + pac::USB::reset_unchecked(); + }); + } + + fn startup_delay() { + // There is a chip specific startup delay. For STM32F103xx it's 1µs and this should wait for + // at least that long. + cortex_m::asm::delay(72); + } +} + +pub type UsbBusType = UsbBus; diff --git a/src/watchdog.rs b/src/watchdog.rs index 0092f16f..551b1fe1 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -39,7 +39,11 @@ impl IndependentWatchdog { /// Debug independent watchdog stopped when core is halted pub fn stop_on_debug(&self, dbgmcu: &DBGMCU, stop: bool) { + #[cfg(any(feature = "f4", feature = "f7"))] dbgmcu.apb1_fz().modify(|_, w| w.dbg_iwdg_stop().bit(stop)); + + #[cfg(feature = "l4")] + dbgmcu.apb1fzr1().modify(|_, w| w.dbg_iwdg_stop().bit(stop)); } /// Sets the watchdog timer timout period. Max: 32768 ms diff --git a/tools/check.py b/tools/check.py index d5bf34bb..1fe381d5 100755 --- a/tools/check.py +++ b/tools/check.py @@ -30,7 +30,7 @@ def main(): features = ["{},usb_fs,can,i2s,fsmc_lcd,rtic1,defmt".format(x) for x in crate_info["features"].keys() - if x.startswith("stm32f4")] + if x.startswith("stm32f4") or x.startswith("stm32f7")] if 'size_check' in sys.argv: cargo_cmd = ['cargo', 'build', '--release']