Fix a number of clippy lints

Signed-off-by: Daniel Egger <[email protected]>

Author: therealprof

src/adc.rs

@@ -42,7 +42,7 @@ const VTEMPCAL30: *const u16 = 0x1FFF_F7B8 as *const u16;
 const VTEMPCAL110: *const u16 = 0x1FFF_F7C2 as *const u16;
 const VDD_CALIB: u16 = 3300;
 
-use core::ptr;
+use core::{ptr, default};
 
 use embedded_hal::{
     adc::{Channel, OneShot},
@@ -93,9 +93,9 @@ pub enum AdcSampleTime {
     T_239,
 }
 
-impl AdcSampleTime {
+impl default::Default for AdcSampleTime {
     /// Get the default sample time (currently 239.5 cycles)
-    pub fn default() -> Self {
+    fn default() -> Self {
         AdcSampleTime::T_239
     }
 }
@@ -138,9 +138,9 @@ pub enum AdcAlign {
     LeftAsRM,
 }
 
-impl AdcAlign {
+impl default::Default for AdcAlign {
     /// Get the default alignment (currently right aligned)
-    pub fn default() -> Self {
+    fn default() -> Self {
         AdcAlign::Right
     }
 }
@@ -168,9 +168,9 @@ pub enum AdcPrecision {
     B_6,
 }
 
-impl AdcPrecision {
+impl default::Default for AdcPrecision {
     /// Get the default precision (currently 12 bit precision)
-    pub fn default() -> Self {
+    fn default() -> Self {
         AdcPrecision::B_12
     }
 }
@@ -247,7 +247,7 @@ adc_pins!(
 impl VTemp {
     /// Init a new VTemp
     pub fn new() -> Self {
-        VTemp::default()
+        Self {}
     }
 
     /// Enable the internal temperature sense, this has a wake up time
@@ -316,7 +316,7 @@ impl VTemp {
 impl VRef {
     /// Init a new VRef
     pub fn new() -> Self {
-        VRef::default()
+        Self {}
     }
 
     /// Enable the internal voltage reference, remember to disable when not in use.
@@ -408,7 +408,7 @@ adc_pins!(
 impl VBat {
     /// Init a new VBat
     pub fn new() -> Self {
-        VBat::default()
+        Self {}
     }
 
     /// Enable the internal VBat sense, remember to disable when not in use
@@ -514,10 +514,10 @@ impl Adc {
     /// Returns the largest possible sample value for the current settings
     pub fn max_sample(&self) -> u16 {
         match self.align {
-            AdcAlign::Left => u16::max_value(),
+            AdcAlign::Left => u16::MAX,
             AdcAlign::LeftAsRM => match self.precision {
-                AdcPrecision::B_6 => u16::from(u8::max_value()),
-                _ => u16::max_value(),
+                AdcPrecision::B_6 => u16::from(u8::MAX),
+                _ => u16::MAX,
             },
             AdcAlign::Right => match self.precision {
                 AdcPrecision::B_12 => (1 << 12) - 1,

src/rcc.rs

@@ -61,12 +61,12 @@ pub enum HSEBypassMode {
 #[allow(clippy::upper_case_acronyms)]
 pub enum USBClockSource {
     #[cfg(feature = "stm32f070")]
-    /// USB peripheral's tranceiver is disabled
+    /// USB peripheral's transceiver is disabled
     Disabled,
     #[cfg(not(feature = "stm32f070"))]
-    /// HSI48 is used as USB peripheral tranceiver clock
+    /// HSI48 is used as USB peripheral transceiver clock
     HSI48,
-    /// PLL output is used as USB peripheral tranceiver clock
+    /// PLL output is used as USB peripheral transceiver clock
     PLL,
 }
 /// RCC for F0x0 devices
@@ -465,7 +465,7 @@ impl CFGR {
             let pllmul = (2 * pllprediv * self.sysclk.unwrap_or(src_clk_freq) + src_clk_freq)
                 / src_clk_freq
                 / 2;
-            let pllmul = core::cmp::min(core::cmp::max(pllmul, 2), 16);
+            let pllmul = pllmul.clamp(2, 16);
             r_sysclk = pllmul * src_clk_freq / pllprediv;
 
             pllmul_bits = Some(pllmul as u8 - 2)
@@ -562,17 +562,14 @@ impl CFGR {
                 feature = "stm32f091",
                 feature = "stm32f098",
             ))]
-            match self.crs {
-                Some(crs) => {
-                    self.rcc.apb1enr.modify(|_, w| w.crsen().set_bit());
-
-                    // Initialize clock recovery
-                    // Set autotrim enabled.
-                    crs.cr.modify(|_, w| w.autotrimen().set_bit());
-                    // Enable CR
-                    crs.cr.modify(|_, w| w.cen().set_bit());
-                }
-                _ => {}
+            if let Some(crs) = self.crs {
+                self.rcc.apb1enr.modify(|_, w| w.crsen().set_bit());
+
+                // Initialize clock recovery
+                // Set autotrim enabled.
+                crs.cr.modify(|_, w| w.autotrimen().set_bit());
+                // Enable CR
+                crs.cr.modify(|_, w| w.cen().set_bit());
             }
 
             // use HSI as source