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1 | 1 | use super::pac;
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2 | 2 | use super::pac::can::TX;
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| 3 | +use crate::gpio::gpioa::{PA11, PA12}; |
3 | 4 | use crate::gpio::gpiob::{PB8, PB9};
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4 | 5 | use crate::gpio::{Alternate, AF4};
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5 | 6 | use crate::rcc::Rcc;
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6 | 7 |
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7 |
| -pub struct CANBus { |
| 8 | +pub trait RxPin {} |
| 9 | +pub trait TxPin {} |
| 10 | + |
| 11 | +macro_rules! can_pins { |
| 12 | + ( |
| 13 | + rx => [$($rx:ty),+ $(,)*], |
| 14 | + tx => [$($tx:ty),+ $(,)*], |
| 15 | + ) => { |
| 16 | + $( |
| 17 | + impl RxPin for $rx {} |
| 18 | + )+ |
| 19 | + $( |
| 20 | + impl TxPin for $tx {} |
| 21 | + )+ |
| 22 | + }; |
| 23 | +} |
| 24 | + |
| 25 | +#[cfg(any(feature = "stm32f042", feature = "stm32f072", feature = "stm32f091"))] |
| 26 | +can_pins! { |
| 27 | + rx => [PA11<Alternate<AF4>>, PB8<Alternate<AF4>>], |
| 28 | + tx => [PA12<Alternate<AF4>>, PB9<Alternate<AF4>>], |
| 29 | +} |
| 30 | + |
| 31 | +pub struct CANBus<RX_PIN, TX_PIN> { |
8 | 32 | can: pac::CAN,
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9 |
| - _rx: PB8<Alternate<AF4>>, |
10 |
| - _tx: PB9<Alternate<AF4>>, |
| 33 | + _rx: RX_PIN, |
| 34 | + _tx: TX_PIN, |
11 | 35 | }
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12 | 36 |
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13 | 37 | pub enum Event {
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14 | 38 | RxMessagePending,
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15 | 39 | }
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16 | 40 |
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17 |
| -impl CANBus { |
18 |
| - // TODO add setting of pins the same way as done in other peripherals |
19 |
| - pub fn new( |
20 |
| - can: pac::CAN, |
21 |
| - rx: PB8<Alternate<AF4>>, |
22 |
| - tx: PB9<Alternate<AF4>>, |
23 |
| - rcc: &mut Rcc, |
24 |
| - ) -> Self { |
| 41 | +impl<RX_PIN, TX_PIN> CANBus<RX_PIN, TX_PIN> |
| 42 | +where |
| 43 | + RX_PIN: RxPin, |
| 44 | + TX_PIN: TxPin, |
| 45 | +{ |
| 46 | + pub fn new(can: pac::CAN, rx: RX_PIN, tx: TX_PIN, rcc: &mut Rcc) -> Self { |
25 | 47 | rcc.regs.apb1enr.modify(|_, w| w.canen().enabled());
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26 | 48 | rcc.regs.apb1rstr.modify(|_, w| w.canrst().reset());
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27 | 49 | rcc.regs.apb1rstr.modify(|_, w| w.canrst().clear_bit());
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