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Merge pull request #184 from Patryk27/cherry-pick-145224
Backport llvm#145224
2 parents 99f0e05 + 0c49875 commit d6d9a37

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llvm/lib/Target/AVR/AVRISelLowering.cpp

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@@ -1123,14 +1123,17 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const {
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EVT VT;
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SDValue Ptr;
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SDLoc DL(N);
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if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
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VT = LD->getMemoryVT();
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Ptr = LD->getBasePtr();
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if (LD->getExtensionType() != ISD::NON_EXTLOAD)
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return false;
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} else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
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VT = ST->getMemoryVT();
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Ptr = ST->getBasePtr();
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// We can not store to program memory.
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if (AVR::isProgramMemoryAccess(ST))
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return false;
@@ -1167,6 +1170,12 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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return false;
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Base = Op->getOperand(0);
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// Post-indexing updates the base, so it's not a valid transform
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// if that's not the same as the load's pointer.
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if (Ptr != Base)
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return false;
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Offset = DAG.getConstant(RHSC, DL, MVT::i8);
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AM = ISD::POST_INC;
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llvm/test/CodeGen/AVR/bug-143247.ll

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@@ -0,0 +1,36 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -O=2 -mtriple=avr-none --mcpu=avr128db28 -verify-machineinstrs | FileCheck %s
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declare dso_local void @nil(i16 noundef) addrspace(1)
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define void @complex_sbi() {
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; CHECK-LABEL: complex_sbi:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: push r16
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; CHECK-NEXT: push r17
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; CHECK-NEXT: ldi r24, 0
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; CHECK-NEXT: ldi r25, 0
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; CHECK-NEXT: .LBB0_1: ; %while.cond
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: sbi 1, 7
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; CHECK-NEXT: adiw r24, 1
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; CHECK-NEXT: movw r16, r24
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; CHECK-NEXT: andi r24, 15
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; CHECK-NEXT: andi r25, 0
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; CHECK-NEXT: adiw r24, 1
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; CHECK-NEXT: call nil
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; CHECK-NEXT: movw r24, r16
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; CHECK-NEXT: rjmp .LBB0_1
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entry:
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br label %while.cond
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while.cond:
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%s.0 = phi i16 [ 0, %entry ], [ %inc, %while.cond ]
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%inc = add nuw nsw i16 %s.0, 1
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%0 = load volatile i8, ptr inttoptr (i16 1 to ptr), align 1
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%or = or i8 %0, -128
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store volatile i8 %or, ptr inttoptr (i16 1 to ptr), align 1
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%and = and i16 %inc, 15
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%add = add nuw nsw i16 %and, 1
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tail call addrspace(1) void @nil(i16 noundef %add)
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br label %while.cond
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}

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