diff --git a/svd-encoder/CHANGELOG.md b/svd-encoder/CHANGELOG.md
index 313a6c4..1a15cd6 100644
--- a/svd-encoder/CHANGELOG.md
+++ b/svd-encoder/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Pin `indexmap` to `2.11.4` to support our MSRV
+
 ## [v0.14.7] - 2025-03-11
 
 - Bump MSRV to 1.70.0
diff --git a/svd-encoder/Cargo.toml b/svd-encoder/Cargo.toml
index 8e6661b..d1a90b1 100644
--- a/svd-encoder/Cargo.toml
+++ b/svd-encoder/Cargo.toml
@@ -15,6 +15,9 @@ readme = "README.md"
 convert_case = "0.6.0"
 svd-rs = { version = "0.14.12", path = "../svd-rs" }
 thiserror = "1.0.31"
+# This is a transitive dep introduced by XML tree,
+# but we need to pin to this version to support our current MSRV of 1.70.0
+indexmap = "=2.11.4"
 
 [dependencies.xmltree]
 version = "0.11.0"
diff --git a/svd-parser/CHANGELOG.md b/svd-parser/CHANGELOG.md
index a68c9f2..f1626fe 100644
--- a/svd-parser/CHANGELOG.md
+++ b/svd-parser/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Add `Target` enum to `Config` and make `vendorSystickConfig` only required for ARM.
+
 ## [v0.14.9] - 2025-03-11
 
 - Bump MSRV to 1.70.0
diff --git a/svd-parser/src/cpu.rs b/svd-parser/src/cpu.rs
index 8725627..e5430da 100644
--- a/svd-parser/src/cpu.rs
+++ b/svd-parser/src/cpu.rs
@@ -12,6 +12,14 @@ impl Parse for Cpu {
             return Err(SVDError::NotExpectedTag("cpu".to_string()).at(tree.id()));
         }
 
+        // Vendor systick is required by ARM targets, but not others
+        // So for others we just default to false if not provided
+        let has_vendor_systick = match tree.get_child_bool("vendorSystickConfig") {
+            Ok(v) => v,
+            Err(e) if config.target == Target::CortexM => return Err(e),
+            _ => false,
+        };
+
         Cpu::builder()
             .name(tree.get_child_text("name")?)
             .revision(tree.get_child_text("revision")?)
@@ -26,7 +34,7 @@ impl Parse for Cpu {
             .dtcm_present(optional::<BoolParse>("dtcmPresent", tree, &())?)
             .vtor_present(optional::<BoolParse>("vtorPresent", tree, &())?)
             .nvic_priority_bits(tree.get_child_u32("nvicPrioBits")?)
-            .has_vendor_systick(tree.get_child_bool("vendorSystickConfig")?)
+            .has_vendor_systick(has_vendor_systick)
             .device_num_interrupts(optional::<u32>("deviceNumInterrupts", tree, &())?)
             .sau_num_regions(optional::<u32>("sauNumRegions", tree, &())?)
             .build(config.validate_level)
diff --git a/svd-parser/src/lib.rs b/svd-parser/src/lib.rs
index b3d22c6..085c0c7 100644
--- a/svd-parser/src/lib.rs
+++ b/svd-parser/src/lib.rs
@@ -38,6 +38,8 @@ pub mod types;
 #[non_exhaustive]
 /// Advanced parser options
 pub struct Config {
+    /// CPU target architecture
+    pub target: Target,
     /// SVD error check level
     pub validate_level: ValidateLevel,
     #[cfg(feature = "expand")]
@@ -80,6 +82,26 @@ impl Config {
     }
 }
 
+#[allow(clippy::upper_case_acronyms)]
+#[allow(non_camel_case_types)]
+#[derive(Clone, Copy, PartialEq, Eq, Debug, Default)]
+/// CPU target architecture
+pub enum Target {
+    #[default]
+    /// ARM Cortex-M
+    CortexM,
+    /// Texas Instruments MSP430
+    Msp430,
+    /// RISC-V
+    RISCV,
+    /// Xtensa LX
+    XtensaLX,
+    /// MIPS
+    Mips,
+    /// None specified
+    None,
+}
+
 /// Parse trait allows SVD objects to be parsed from XML elements.
 pub trait Parse {
     /// Object returned by parse method