Merge pull request #13 from robamu/cortex-r-und-abt-stack-setup

Cortex-R: UND and ABT stack setup

Author: jonathanpallant

cortex-ar/CHANGELOG.md

@@ -0,0 +1,15 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [unreleased]
+
+## [v0.1.0]
+
+Initial release
+
+[unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.1.0...HEAD
+[v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-ar-v0.1.0

cortex-r-rt/CHANGELOG.md

@@ -0,0 +1,19 @@
+# Change Log
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+## [unreleased]
+
+## Added
+
+- Added ABT und UND mode stack setup.
+
+## [v0.1.0]
+
+Initial release
+
+[unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-r-rt-v0.1.0...HEAD
+[v0.1.0]: https://github.com/rust-embedded/cortex-ar/releases/tag/cortex-r-rt-v0.1.0

cortex-r-rt/link.x

@@ -78,13 +78,19 @@ and a FIQ stack, plus the remainder is our system stack.
 You must keep _stack_top and the stack sizes aligned to eight byte boundaries.
 */
 PROVIDE(_stack_top = ORIGIN(DATA) + LENGTH(DATA));
-PROVIDE(_fiq_stack_size = 0x100);
+PROVIDE(_fiq_stack_size = 0x400);
 PROVIDE(_irq_stack_size = 0x1000);
+PROVIDE(_abt_stack_size = 0x400);
+PROVIDE(_und_stack_size = 0x400);
 PROVIDE(_svc_stack_size = 0x1000);
 
 ASSERT(_stack_top % 8 == 0, "ERROR(cortex-r-rt): top of stack is not 8-byte aligned");
 ASSERT(_fiq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of FIQ stack is not 8-byte aligned");
 ASSERT(_irq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of IRQ stack is not 8-byte aligned");
+ASSERT(_fiq_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of FIQ stack is not 8-byte aligned");
+ASSERT(_abt_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of ABT stack is not 8-byte aligned");
+ASSERT(_und_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of UND stack is not 8-byte aligned");
+ASSERT(_svc_stack_size % 8 == 0, "ERROR(cortex-r-rt): size of SVC stack is not 8-byte aligned");
 
 PROVIDE(_asm_undefined_handler =_asm_default_handler);
 PROVIDE(_asm_prefetch_handler  =_asm_default_handler);

cortex-r-rt/src/lib.rs

@@ -342,21 +342,32 @@ core::arch::global_asm!(
 
     .type _el1_start, %function
     _el1_start:
-        // Set stack pointer (as the top) and mask interrupts for for FIQ mode (Mode 0x11)
+        // Set up stacks.
         ldr     r0, =_stack_top
-        msr     cpsr, {fiq_mode}
+        // Set stack pointer (right after) and mask interrupts for for UND mode (Mode 0x1B)
+        msr     cpsr, {und_mode}
         mov     sp, r0
-        ldr     r1, =_fiq_stack_size
+        ldr     r1, =_und_stack_size
+        sub     r0, r0, r1
+        // Set stack pointer (right after) and mask interrupts for for SVC mode (Mode 0x13)
+        msr     cpsr, {svc_mode}
+        mov     sp, r0
+        ldr     r1, =_svc_stack_size
+        sub     r0, r0, r1
+        // Set stack pointer (right after) and mask interrupts for for ABT mode (Mode 0x17)
+        msr     cpsr, {abt_mode}
+        mov     sp, r0
+        ldr     r1, =_abt_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for IRQ mode (Mode 0x12)
         msr     cpsr, {irq_mode}
         mov     sp, r0
         ldr     r1, =_irq_stack_size
         sub     r0, r0, r1
-        // Set stack pointer (right after) and mask interrupts for for SVC mode (Mode 0x13)
-        msr     cpsr, {svc_mode}
+        // Set stack pointer (right after) and mask interrupts for for FIQ mode (Mode 0x11)
+        msr     cpsr, {fiq_mode}
         mov     sp, r0
-        ldr     r1, =_svc_stack_size
+        ldr     r1, =_fiq_stack_size
         sub     r0, r0, r1
         // Set stack pointer (right after) and mask interrupts for for System mode (Mode 0x1F)
         msr     cpsr, {sys_mode}
@@ -395,23 +406,37 @@ core::arch::global_asm!(
         b       .
     .size _el1_start, . - _el1_start
     "#,
-    fiq_mode = const {
+    und_mode = const {
         Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Fiq)
+            .with_mode(ProcessorMode::Und)
             .with_i(true)
             .with_f(true)
             .raw_value()
     },
-    irq_mode = const {
+    svc_mode = const {
         Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Irq)
+            .with_mode(ProcessorMode::Svc)
             .with_i(true)
             .with_f(true)
             .raw_value()
     },
-    svc_mode = const {
+    abt_mode = const {
         Cpsr::new_with_raw_value(0)
-            .with_mode(ProcessorMode::Svc)
+            .with_mode(ProcessorMode::Abt)
+            .with_i(true)
+            .with_f(true)
+            .raw_value()
+    },
+    fiq_mode = const {
+        Cpsr::new_with_raw_value(0)
+            .with_mode(ProcessorMode::Fiq)
+            .with_i(true)
+            .with_f(true)
+            .raw_value()
+    },
+    irq_mode = const {
+        Cpsr::new_with_raw_value(0)
+            .with_mode(ProcessorMode::Irq)
             .with_i(true)
             .with_f(true)
             .raw_value()