From 38cf20c5cd7d7c81c4347375adf7c060cd24285b Mon Sep 17 00:00:00 2001
From: jethroqti <baucheng@qualcomm.com>
Date: Thu, 27 Nov 2025 00:39:38 -0800
Subject: [PATCH] Qualcomm AI Engine Direct - support SW6100

Summary
- Support SOC SW6100

Test plan
- Use unit test with -m SW6100
---
 backends/qualcomm/README.md                          | 1 +
 backends/qualcomm/serialization/qc_compiler_spec.fbs | 1 +
 backends/qualcomm/serialization/qc_schema.py         | 2 ++
 backends/qualcomm/utils/utils.py                     | 2 ++
 4 files changed, 6 insertions(+)

diff --git a/backends/qualcomm/README.md b/backends/qualcomm/README.md
index fa82c38b2fd..98d7960cca1 100644
--- a/backends/qualcomm/README.md
+++ b/backends/qualcomm/README.md
@@ -30,6 +30,7 @@ Please check `generate_qnn_executorch_compiler_spec()` in
 - SXR2330P
 - QCS9100
 - SAR2230P
+- SW6100
 
 ### Adding more supported Chipset
 Currently, users cannot add additional chipset models because the chipset ID is not accessible to community users. If you have specific chipset models you wish to add, please contact one of the authors in the `Code Reviews` section at the bottom of this page.
diff --git a/backends/qualcomm/serialization/qc_compiler_spec.fbs b/backends/qualcomm/serialization/qc_compiler_spec.fbs
index 85affe3464d..b10a6549c6a 100644
--- a/backends/qualcomm/serialization/qc_compiler_spec.fbs
+++ b/backends/qualcomm/serialization/qc_compiler_spec.fbs
@@ -48,6 +48,7 @@ enum QcomChipset: int {
   QCS9100 = 77,
   SAR2230P = 95,
   SA8255 = 52,
+  SW6100 = 96,
 }
 
 /// Indicate the information of the specified SoC.
diff --git a/backends/qualcomm/serialization/qc_schema.py b/backends/qualcomm/serialization/qc_schema.py
index c188c555c41..ab989545e28 100644
--- a/backends/qualcomm/serialization/qc_schema.py
+++ b/backends/qualcomm/serialization/qc_schema.py
@@ -54,6 +54,7 @@ class QcomChipset(IntEnum):
     QCS9100 = 77  # v73
     SAR2230P = 95  # v81
     SA8255 = 52  # v73
+    SW6100 = 96  # v81
 
 
 @dataclass
@@ -78,6 +79,7 @@ class SocInfo:
     QcomChipset.SXR2330P: SocInfo(QcomChipset.SXR2330P, HtpInfo(HtpArch.V79, 8)),
     QcomChipset.QCS9100: SocInfo(QcomChipset.QCS9100, HtpInfo(HtpArch.V73, 8)),
     QcomChipset.SAR2230P: SocInfo(QcomChipset.SAR2230P, HtpInfo(HtpArch.V81, 4)),
+    QcomChipset.SW6100: SocInfo(QcomChipset.SW6100, HtpInfo(HtpArch.V81, 4)),
 }
 
 
diff --git a/backends/qualcomm/utils/utils.py b/backends/qualcomm/utils/utils.py
index 20a1d3c0f72..2b3964d413b 100644
--- a/backends/qualcomm/utils/utils.py
+++ b/backends/qualcomm/utils/utils.py
@@ -1104,6 +1104,7 @@ def get_soc_to_arch_map():
         "SXR2330P": HtpArch.V79,
         "QCS9100": HtpArch.V73,
         "SAR2230P": HtpArch.V81,
+        "SW6100": HtpArch.V81,
     }
 
 
@@ -1124,6 +1125,7 @@ def get_soc_to_chipset_map():
         "SXR2330P": QcomChipset.SXR2330P,
         "QCS9100": QcomChipset.QCS9100,
         "SAR2230P": QcomChipset.SAR2230P,
+        "SW6100": QcomChipset.SW6100,
     }