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Can say a bit what you're trying to achieve? I guess the ability for user code to configure the CPU frequency at runtime, but why? Saving power? Is there really so much power to save compared to, say, running whatever task needs done at highest frequency and then going to sleep? |
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My experiments with configuring CPU Clock of Rasp Pico and Rasp Pico 2: Rasp Pico CPU clock config: Rasp Pico2 CPU clock config: |
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It seems that two separate issues are being discussed together here. The first is how to represent the actual hardware configuration. Boards with the same name may still use different MCUs, oscillator sources, crystal frequencies, or maximum operating frequencies. These are not arbitrary settings that users should freely combine; they are properties of the manufactured hardware. For that reason, rather than adding separate common CLI options such as The second issue is how to switch between performance and power-consumption levels at runtime on the same hardware. Rather than exposing a raw CPU-frequency setter, this could be represented by a small set of validated operating modes: type PowerMode uint8
const (
PowerHigh PowerMode = iota
PowerNormal
PowerLow
PowerVeryLow
)
func SetPowerMode(mode PowerMode) errorThe selected hardware variant would define the actual frequency, PLL configuration, bus dividers, flash wait states, and other details for each mode.
This does not need to be implemented for every target at once. Targets that do not support runtime switching can return an unsupported error, and support can be added incrementally. Why validated modes instead of a raw frequency setter?RP2040-E16 requires This is not simply another point on a performance-versus-power scale, and it is not something users can reasonably be expected to know when choosing a frequency. It is exactly the kind of silicon-specific constraint that a hardware variant should encode and that validated operating modes should preserve. With a raw frequency setter, a user trying to save power could silently violate this erratum by lowering the system clock. The failure might then appear only at process, voltage, or temperature extremes rather than during normal development. I am not suggesting that direct register access should be removed. It should remain available for configurations that TinyGo does not cover. However, the modes that TinyGo does provide should be known-good configurations. SummaryRather than modeling clock configuration itself as one common abstraction, I suggest separating the problem into two layers:
The number and exact meaning of the modes are open to discussion. The four modes above are only a starting point. |
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This discussion centers on modeling CPU frequency at the TinyGo API level.
Things to take into consideration:
Catalyst conversation: #5106 (comment)
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