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[GR-57104] Use r12 as zero value register where applicable.
PullRequest: graal/18684
2 parents 5f0306c + abef2e2 commit df398bc

33 files changed

+242
-106
lines changed

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/amd64/AMD64Assembler.java

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -512,7 +512,8 @@ public static class AMD64MROp extends AMD64RROp {
512512
// @formatter:off
513513
public static final AMD64MROp MOVB = new AMD64MROp("MOVB", 0x88, OpAssertion.ByteAssertion);
514514
public static final AMD64MROp MOV = new AMD64MROp("MOV", 0x89, OpAssertion.WordOrLargerAssertion);
515-
// @formatter:on
515+
public static final AMD64MROp TEST = new AMD64MROp("TEST", 0x85, OpAssertion.WordOrLargerAssertion);
516+
// @formatter:on
516517

517518
protected AMD64MROp(String opcode, int op, OpAssertion assertion) {
518519
this(opcode, 0, 0, op, assertion, null);

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/amd64/AMD64MacroAssembler.java

Lines changed: 76 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ public final void movdbl(AMD64Address dst, Register src) {
299299
*/
300300
public final void movlong(AMD64Address dst, long src) {
301301
if (NumUtil.isInt(src)) {
302-
AMD64MIOp.MOV.emit(this, OperandSize.QWORD, dst, (int) src);
302+
emitAMD64MIOp(AMD64MIOp.MOV, OperandSize.QWORD, dst, (int) src, false);
303303
} else {
304304
AMD64Address high = new AMD64Address(dst.getBase(), dst.getIndex(), dst.getScale(), dst.getDisplacement() + 4, dst.getDisplacementAnnotation(), dst.instructionStartPosition);
305305
movl(dst, (int) (src & 0xFFFFFFFF));
@@ -1439,4 +1439,79 @@ public final void ptestU(AVXKind.AVXSize size, Register dst, AMD64Address src, R
14391439
public boolean isAVX() {
14401440
return supports(CPUFeature.AVX);
14411441
}
1442+
1443+
public final void moveInt(Register dst, int imm) {
1444+
if (imm == 0) {
1445+
Register zeroValueRegister = getZeroValueRegister();
1446+
if (!Register.None.equals(zeroValueRegister)) {
1447+
movl(dst, zeroValueRegister);
1448+
return;
1449+
}
1450+
}
1451+
movl(dst, imm);
1452+
}
1453+
1454+
public final void moveInt(AMD64Address dst, int imm) {
1455+
if (imm == 0) {
1456+
Register zeroValueRegister = getZeroValueRegister();
1457+
if (!Register.None.equals(zeroValueRegister)) {
1458+
movl(dst, zeroValueRegister);
1459+
return;
1460+
}
1461+
}
1462+
movl(dst, imm);
1463+
}
1464+
1465+
public final void moveIntSignExtend(Register result, int imm) {
1466+
if (imm == 0) {
1467+
Register zeroValueRegister = getZeroValueRegister();
1468+
if (!Register.None.equals(zeroValueRegister)) {
1469+
movl(result, zeroValueRegister);
1470+
return;
1471+
}
1472+
}
1473+
movslq(result, imm);
1474+
}
1475+
1476+
private static AMD64MROp toMR(AMD64MIOp op) {
1477+
if (op == AMD64MIOp.MOVB) {
1478+
return AMD64MROp.MOVB;
1479+
} else if (op == AMD64MIOp.MOV) {
1480+
return AMD64MROp.MOV;
1481+
} else if (op == AMD64MIOp.TEST) {
1482+
return AMD64MROp.TEST;
1483+
}
1484+
return null;
1485+
}
1486+
1487+
public final void emitAMD64MIOp(AMD64MIOp opcode, OperandSize size, Register dst, int imm, boolean annotateImm) {
1488+
if (imm == 0) {
1489+
Register zeroValueRegister = getZeroValueRegister();
1490+
AMD64MROp mrOp = toMR(opcode);
1491+
if (!Register.None.equals(zeroValueRegister) && mrOp != null) {
1492+
mrOp.emit(this, size, dst, zeroValueRegister);
1493+
return;
1494+
}
1495+
}
1496+
opcode.emit(this, size, dst, imm, annotateImm);
1497+
}
1498+
1499+
public final void emitAMD64MIOp(AMD64MIOp opcode, OperandSize size, AMD64Address dst, int imm, boolean annotateImm) {
1500+
if (imm == 0) {
1501+
Register zeroValueRegister = getZeroValueRegister();
1502+
AMD64MROp mrOp = toMR(opcode);
1503+
if (!Register.None.equals(zeroValueRegister) && mrOp != null) {
1504+
mrOp.emit(this, size, dst, zeroValueRegister);
1505+
return;
1506+
}
1507+
}
1508+
opcode.emit(this, size, dst, imm, annotateImm);
1509+
}
1510+
1511+
/**
1512+
* Returns a register whose content is always zero.
1513+
*/
1514+
public Register getZeroValueRegister() {
1515+
return Register.None;
1516+
}
14421517
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/AMD64HotSpotLIRGenerator.java

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2012, 2023, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2012, 2024, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -96,13 +96,15 @@
9696
import jdk.vm.ci.code.RegisterConfig;
9797
import jdk.vm.ci.code.RegisterValue;
9898
import jdk.vm.ci.meta.AllocatableValue;
99+
import jdk.vm.ci.meta.Constant;
99100
import jdk.vm.ci.meta.DeoptimizationAction;
100101
import jdk.vm.ci.meta.DeoptimizationReason;
101102
import jdk.vm.ci.meta.JavaConstant;
102103
import jdk.vm.ci.meta.JavaKind;
103104
import jdk.vm.ci.meta.PlatformKind;
104105
import jdk.vm.ci.meta.SpeculationLog;
105106
import jdk.vm.ci.meta.Value;
107+
import jdk.vm.ci.meta.ValueKind;
106108

107109
/**
108110
* LIR generator specialized for AMD64 HotSpot.
@@ -655,4 +657,15 @@ public int getArrayLengthOffset() {
655657
public Register getHeapBaseRegister() {
656658
return getProviders().getRegisters().getHeapBaseRegister();
657659
}
660+
661+
@Override
662+
public AllocatableValue emitLoadConstant(ValueKind<?> kind, Constant constant) {
663+
if (((AMD64Kind) kind.getPlatformKind()).isInteger() && constant instanceof JavaConstant && constant.isDefaultForKind()) {
664+
Register zeroValueRegister = getProviders().getRegisters().getZeroValueRegister(config);
665+
if (!Register.None.equals(zeroValueRegister)) {
666+
return zeroValueRegister.asValue(kind);
667+
}
668+
}
669+
return super.emitLoadConstant(kind, constant);
670+
}
658671
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/AMD64HotSpotMacroAssembler.java

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2022, 2024, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -171,4 +171,9 @@ protected final int membarOffset() {
171171
}
172172
return offset;
173173
}
174+
175+
@Override
176+
public Register getZeroValueRegister() {
177+
return providers.getRegisters().getZeroValueRegister(config);
178+
}
174179
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXAtomicReadAndWriteOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ public AMD64HotSpotXAtomicReadAndWriteOp(Variable result, AMD64AddressValue load
5454
@Override
5555
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
5656
AMD64Move.move(QWORD, crb, masm, result, newValue);
57-
masm.xchgq(asRegister(result), loadAddress.toAddress());
57+
masm.xchgq(asRegister(result), loadAddress.toAddress(masm));
5858
emitBarrier(crb, masm);
5959
}
6060
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXBarrieredOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ protected AMD64HotSpotXBarrieredOp(LIRInstructionClass<? extends AMD64HotSpotXBa
6565
* Emit a barrier testing a specific register.
6666
*/
6767
protected void emitBarrier(CompilationResultBuilder crb, AMD64MacroAssembler masm, Register register, Label success) {
68-
AMD64HotSpotXBarrierSetLIRGenerator.emitBarrier(crb, masm, success, register, config, callTarget, loadAddress.toAddress(), this);
68+
AMD64HotSpotXBarrierSetLIRGenerator.emitBarrier(crb, masm, success, register, config, callTarget, loadAddress.toAddress(masm), this);
6969
}
7070

7171
/**

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXCompareAndSwapOp.java

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
7777
if (crb.target.isMP) {
7878
masm.lock();
7979
}
80-
masm.cmpxchgq(newReg, loadAddress.toAddress());
80+
masm.cmpxchgq(newReg, loadAddress.toAddress(masm));
8181
// if the cmpxchgq succeeds then we are done
8282
masm.jccb(AMD64Assembler.ConditionFlag.Zero, success);
8383
/*
@@ -91,7 +91,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
9191
if (crb.target.isMP) {
9292
masm.lock();
9393
}
94-
masm.cmpxchgq(newReg, loadAddress.toAddress());
94+
masm.cmpxchgq(newReg, loadAddress.toAddress(masm));
9595
masm.bind(barrierOk);
9696
masm.cmpq(asRegister(temp), asRegister(result));
9797
masm.bind(success);

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXReadBarrierOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
5555
crb.recordImplicitException(masm.position(), state);
5656
}
5757
final Register resultReg = asRegister(result);
58-
MOV.emit(masm, AMD64BaseAssembler.OperandSize.QWORD, resultReg, loadAddress.toAddress());
58+
MOV.emit(masm, AMD64BaseAssembler.OperandSize.QWORD, resultReg, loadAddress.toAddress(masm));
5959
emitBarrier(crb, masm);
6060
}
6161
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXVectorReadBarrierOp.java

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -74,9 +74,9 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
7474
crb.recordImplicitException(masm.position(), state);
7575
}
7676
Register resultReg = asRegister(result);
77-
op.emit(masm, size, resultReg, loadAddress.toAddress());
77+
op.emit(masm, size, resultReg, loadAddress.toAddress(masm));
7878

79-
AMD64Address address = loadAddress.toAddress();
79+
AMD64Address address = loadAddress.toAddress(masm);
8080

8181
final Label entryPoint = new Label();
8282
final Label continuation = new Label();
@@ -119,7 +119,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
119119
masm.movslq(cArg1, count);
120120
AMD64Call.directCall(crb, masm, callTarget, null, false, null);
121121
masm.movq(resultReg, cArg0);
122-
op.emit(masm, size, resultReg, loadAddress.toAddress());
122+
op.emit(masm, size, resultReg, loadAddress.toAddress(masm));
123123

124124
// Return to inline code
125125
masm.jmp(continuation);

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZAtomicReadAndWriteOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ public AMD64HotSpotZAtomicReadAndWriteOp(Variable result, AMD64AddressValue load
5656
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
5757
emitPreWriteBarrier(crb, masm, asRegister(result), null);
5858
zColor(crb, masm, asRegister(result), asRegister(newValue));
59-
masm.xchgq(asRegister(result), storeAddress.toAddress());
59+
masm.xchgq(asRegister(result), storeAddress.toAddress(masm));
6060
Register ref = asRegister(result);
6161
AMD64HotSpotZBarrierSetLIRGenerator.zUncolor(crb, masm, ref);
6262
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZCompareAndSwapOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
8585
if (crb.target.isMP) {
8686
masm.lock();
8787
}
88-
masm.cmpxchgq(asRegister(tmp), storeAddress.toAddress());
88+
masm.cmpxchgq(asRegister(tmp), storeAddress.toAddress(masm));
8989
if (!isLogic) {
9090
Register ref = asRegister(cmpValue);
9191
AMD64HotSpotZBarrierSetLIRGenerator.zUncolor(crb, masm, ref);

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZLoadBarrieredOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,6 @@ protected AMD64HotSpotZLoadBarrieredOp(LIRInstructionClass<? extends AMD64HotSpo
6666
* Emit a barrier testing the {@code result} register.
6767
*/
6868
protected void emitLoadBarrier(CompilationResultBuilder crb, AMD64MacroAssembler masm, boolean isNotStrong) {
69-
AMD64HotSpotZBarrierSetLIRGenerator.emitLoadBarrier(crb, masm, asRegister(result), callTarget, loadAddress.toAddress(), this, isNotStrong);
69+
AMD64HotSpotZBarrierSetLIRGenerator.emitLoadBarrier(crb, masm, asRegister(result), callTarget, loadAddress.toAddress(masm), this, isNotStrong);
7070
}
7171
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZReadBarrierOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
5959
crb.recordImplicitException(masm.position(), state);
6060
}
6161
final Register resultReg = asRegister(result);
62-
MOV.emit(masm, AMD64BaseAssembler.OperandSize.QWORD, resultReg, loadAddress.toAddress());
62+
MOV.emit(masm, AMD64BaseAssembler.OperandSize.QWORD, resultReg, loadAddress.toAddress(masm));
6363
emitLoadBarrier(crb, masm, isNotStrong);
6464
}
6565
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZStoreBarrieredOp.java

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ protected AMD64HotSpotZStoreBarrieredOp(LIRInstructionClass<? extends AMD64HotSp
7575
}
7676

7777
protected void emitPreWriteBarrier(CompilationResultBuilder crb, AMD64MacroAssembler masm, Register resultReg, LIRFrameState state) {
78-
AMD64HotSpotZBarrierSetLIRGenerator.emitPreWriteBarrier(crb, masm, this, config, storeAddress.toAddress(), resultReg, storeKind, asRegister(tmp), asRegister(tmp2), callTarget,
78+
AMD64HotSpotZBarrierSetLIRGenerator.emitPreWriteBarrier(crb, masm, this, config, storeAddress.toAddress(masm), resultReg, storeKind, asRegister(tmp), asRegister(tmp2), callTarget,
7979
state);
8080
}
8181
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZVectorReadBarrierOp.java

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -84,9 +84,9 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
8484
crb.recordImplicitException(masm.position(), state);
8585
}
8686
Register resultReg = asRegister(result);
87-
op.emit(masm, size, resultReg, loadAddress.toAddress());
87+
op.emit(masm, size, resultReg, loadAddress.toAddress(masm));
8888

89-
AMD64Address address = loadAddress.toAddress();
89+
AMD64Address address = loadAddress.toAddress(masm);
9090

9191
final Label entryPoint = new Label();
9292
final Label continuation = new Label();
@@ -129,7 +129,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
129129
masm.movslq(cArg1, count);
130130
AMD64Call.directCall(crb, masm, callTarget, null, false, null);
131131
masm.movq(resultReg, cArg0);
132-
op.emit(masm, size, resultReg, loadAddress.toAddress());
132+
op.emit(masm, size, resultReg, loadAddress.toAddress(masm));
133133

134134
// Return to inline code
135135
masm.jmp(continuation);

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/meta/HotSpotRegisters.java

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2011, 2024, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -24,6 +24,7 @@
2424
*/
2525
package jdk.graal.compiler.hotspot.meta;
2626

27+
import jdk.graal.compiler.hotspot.GraalHotSpotVMConfig;
2728
import jdk.vm.ci.code.Register;
2829

2930
public class HotSpotRegisters implements HotSpotRegistersProvider {
@@ -55,4 +56,16 @@ public Register getStackPointerRegister() {
5556
assert !stackPointerRegister.equals(Register.None) : "stack pointer register is not defined";
5657
return stackPointerRegister;
5758
}
59+
60+
@Override
61+
public Register getZeroValueRegister(GraalHotSpotVMConfig config) {
62+
if (config.useCompressedOops && !config.getOopEncoding().hasBase()) {
63+
/*
64+
* Heap base register is exempted from register allocation when using compressed oops.
65+
* Its value will be config.getOopEncoding().getBase().
66+
*/
67+
return getHeapBaseRegister();
68+
}
69+
return Register.None;
70+
}
5871
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/meta/HotSpotRegistersProvider.java

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2011, 2024, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -24,6 +24,7 @@
2424
*/
2525
package jdk.graal.compiler.hotspot.meta;
2626

27+
import jdk.graal.compiler.hotspot.GraalHotSpotVMConfig;
2728
import jdk.vm.ci.code.Register;
2829

2930
/**
@@ -45,4 +46,9 @@ public interface HotSpotRegistersProvider {
4546
* Gets the stack pointer register.
4647
*/
4748
Register getStackPointerRegister();
49+
50+
/**
51+
* Gets the register whose value is always 0.
52+
*/
53+
Register getZeroValueRegister(GraalHotSpotVMConfig config);
4854
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/lir/LIRValueUtil.java

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2011, 2024, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -34,7 +34,6 @@
3434
import jdk.graal.compiler.debug.GraalError;
3535
import jdk.graal.compiler.lir.framemap.SimpleVirtualStackSlot;
3636
import jdk.graal.compiler.lir.framemap.SimpleVirtualStackSlotAlias;
37-
3837
import jdk.vm.ci.code.Register;
3938
import jdk.vm.ci.code.RegisterValue;
4039
import jdk.vm.ci.code.StackSlot;

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