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__sys builtin support for AArch64 (#146456)
Adds support for __sys Clang builtin for AArch64 __sys is a long existing MSVC intrinsic used to manage caches, tlbs, etc by writing to system registers: * It takes a macro-generated constant and uses it to form the AArch64 SYS instruction which is MSR with op0=1. The macro drops op0 and expects the implementation to hardcode it to 1 in the encoding. * Volume use is in systems code (kernels, hypervisors, boot environments, firmware) * Has an unused return value due to MSVC cut/paste error Implementation: * Clang builtin, sharing code with Read/WriteStatusReg * Hardcodes the op0=1 * Explicitly returns 0 * Code-format change from clang-format * Unittests included * Not limited to MSVC-environment as its generally useful and neutral
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clang/include/clang/Basic/BuiltinsAArch64.def

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@@ -274,6 +274,7 @@ TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", INTRIN_H, ALL_MS_LANGUAGES,
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TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(_ReadStatusReg, "LLii", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(_WriteStatusReg, "viLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(__sys, "UiiLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(_AddressOfReturnAddress, "v*", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(__mulh, "SLLiSLLiSLLi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")

clang/lib/CodeGen/TargetBuiltins/ARM.cpp

Lines changed: 17 additions & 9 deletions
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@@ -5471,19 +5471,22 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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}
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if (BuiltinID == clang::AArch64::BI_ReadStatusReg ||
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BuiltinID == clang::AArch64::BI_WriteStatusReg) {
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BuiltinID == clang::AArch64::BI_WriteStatusReg ||
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BuiltinID == clang::AArch64::BI__sys) {
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LLVMContext &Context = CGM.getLLVMContext();
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unsigned SysReg =
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E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
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std::string SysRegStr;
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llvm::raw_string_ostream(SysRegStr) <<
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((1 << 1) | ((SysReg >> 14) & 1)) << ":" <<
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((SysReg >> 11) & 7) << ":" <<
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((SysReg >> 7) & 15) << ":" <<
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((SysReg >> 3) & 15) << ":" <<
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( SysReg & 7);
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unsigned SysRegOp0 = (BuiltinID == clang::AArch64::BI_ReadStatusReg ||
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BuiltinID == clang::AArch64::BI_WriteStatusReg)
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? ((1 << 1) | ((SysReg >> 14) & 1))
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: 1;
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llvm::raw_string_ostream(SysRegStr)
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<< SysRegOp0 << ":" << ((SysReg >> 11) & 7) << ":"
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<< ((SysReg >> 7) & 15) << ":" << ((SysReg >> 3) & 15) << ":"
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<< (SysReg & 7);
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llvm::Metadata *Ops[] = { llvm::MDString::get(Context, SysRegStr) };
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llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
@@ -5500,8 +5503,13 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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llvm::Function *F = CGM.getIntrinsic(Intrinsic::write_register, Types);
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llvm::Value *ArgValue = EmitScalarExpr(E->getArg(1));
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return Builder.CreateCall(F, { Metadata, ArgValue });
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llvm::Value *Result = Builder.CreateCall(F, {Metadata, ArgValue});
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if (BuiltinID == clang::AArch64::BI__sys) {
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// Return 0 for convenience, even though MSVC returns some other undefined
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// value.
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Result = ConstantInt::get(Builder.getInt32Ty(), 0);
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}
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return Result;
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}
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if (BuiltinID == clang::AArch64::BI_AddressOfReturnAddress) {

clang/lib/Headers/intrin.h

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@@ -392,6 +392,7 @@ __int64 _InterlockedAdd64_nf(__int64 volatile *, __int64);
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__int64 _InterlockedAdd64_rel(__int64 volatile *, __int64);
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__int64 _ReadStatusReg(int);
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void _WriteStatusReg(int, __int64);
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unsigned int __sys(int, __int64);
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unsigned short __cdecl _byteswap_ushort(unsigned short val);
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unsigned long __cdecl _byteswap_ulong (unsigned long val);

clang/lib/Sema/SemaARM.cpp

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@@ -1084,7 +1084,7 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI,
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// converted to a register of the form S1_2_C3_C4_5. Let the hardware throw
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// an exception for incorrect registers. This matches MSVC behavior.
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if (BuiltinID == AArch64::BI_ReadStatusReg ||
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BuiltinID == AArch64::BI_WriteStatusReg)
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BuiltinID == AArch64::BI_WriteStatusReg || BuiltinID == AArch64::BI__sys)
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return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 0x7fff);
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if (BuiltinID == AArch64::BI__getReg)
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@@ -0,0 +1,65 @@
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// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -S \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// From winnt.h
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// op0=1 encodings, use with __sys
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#define ARM64_SYSINSTR(op0, op1, crn, crm, op2) \
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( ((op1 & 7) << 11) | \
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((crn & 15) << 7) | \
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((crm & 15) << 3) | \
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((op2 & 7) << 0) )
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//
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// Sampling of instructions
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//
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#define ARM64_DC_CGDSW_EL1 ARM64_SYSINSTR(1,0, 7,10,6) // Clean of Data and Allocation Tags by Set/Way
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#define ARM64_IC_IALLU_EL1 ARM64_SYSINSTR(1,0, 7, 5,0) // Instruction Cache Invalidate All to PoU
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#define ARM64_AT_S1E2W ARM64_SYSINSTR(1,4, 7, 8,1) // Translate Stage1, EL2, write
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#define ARM64_TLBI_VMALLE1 ARM64_SYSINSTR(1,0, 8, 7,0) // Invalidate stage 1 TLB [CP15_TLBIALL]
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#define ARM64_CFP_RCTX ARM64_SYSINSTR(1,3, 7, 3,4) // Control Flow Prediction Restriction by Context
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// From intrin.h
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unsigned int __sys(int, __int64);
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void check__sys(__int64 v) {
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__int64 ret;
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__sys(ARM64_DC_CGDSW_EL1, v);
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// CHECK-ASM: msr S1_0_C7_C10_6, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
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__sys(ARM64_IC_IALLU_EL1, v);
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// CHECK-ASM: msr S1_0_C7_C5_0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
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__sys(ARM64_AT_S1E2W, v);
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// CHECK-ASM: msr S1_4_C7_C8_1, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
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__sys(ARM64_TLBI_VMALLE1, v);
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// CHECK-ASM: msr S1_0_C8_C7_0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
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__sys(ARM64_CFP_RCTX, v);
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// CHECK-ASM: msr S1_3_C7_C3_4, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
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}
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// CHECK-IR: ![[MD2]] = !{!"1:0:7:10:6"}
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// CHECK-IR: ![[MD3]] = !{!"1:0:7:5:0"}
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// CHECK-IR: ![[MD4]] = !{!"1:4:7:8:1"}
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// CHECK-IR: ![[MD5]] = !{!"1:0:8:7:0"}
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// CHECK-IR: ![[MD6]] = !{!"1:3:7:3:4"}

clang/test/Sema/builtins-microsoft-arm64.c

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Original file line numberDiff line numberDiff line change
@@ -24,3 +24,12 @@ void check_ReadWriteStatusReg(int v) {
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_ReadStatusReg(x); // expected-error {{argument to '_ReadStatusReg' must be a constant integer}}
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_WriteStatusReg(x, v); // expected-error {{argument to '_WriteStatusReg' must be a constant integer}}
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}
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void check__sys(int v) {
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int x;
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__sys(x, v); // expected-error {{argument to '__sys' must be a constant integer}}
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}
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unsigned int check__sys_retval() {
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return __sys(0, 1); // builtin has superfluous return value for MSVC compatibility
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}

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