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| 1 | +//===- MaskedloadToLoad.cpp - Lowers maskedload to load -------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | + |
| 9 | +#include "mlir/Dialect/AMDGPU/Transforms/Passes.h" |
| 10 | + |
| 11 | +#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h" |
| 12 | +#include "mlir/Dialect/Affine/IR/AffineOps.h" |
| 13 | +#include "mlir/Dialect/Arith/IR/Arith.h" |
| 14 | +#include "mlir/Dialect/MemRef/IR/MemRef.h" |
| 15 | +#include "mlir/Dialect/MemRef/Utils/MemRefUtils.h" |
| 16 | +#include "mlir/Dialect/SCF/IR/SCF.h" |
| 17 | +#include "mlir/Dialect/Vector/IR/VectorOps.h" |
| 18 | +#include "mlir/IR/BuiltinTypes.h" |
| 19 | +#include "mlir/IR/OpDefinition.h" |
| 20 | +#include "mlir/IR/PatternMatch.h" |
| 21 | +#include "mlir/IR/TypeUtilities.h" |
| 22 | +#include "mlir/Pass/Pass.h" |
| 23 | +#include "mlir/Support/LogicalResult.h" |
| 24 | +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" |
| 25 | +#include "llvm/Support/MathExtras.h" |
| 26 | + |
| 27 | +namespace mlir::amdgpu { |
| 28 | +#define GEN_PASS_DEF_AMDGPUMASKEDLOADTOLOADPASS |
| 29 | +#include "mlir/Dialect/AMDGPU/Transforms/Passes.h.inc" |
| 30 | +} // namespace mlir::amdgpu |
| 31 | + |
| 32 | +using namespace mlir; |
| 33 | +using namespace mlir::amdgpu; |
| 34 | + |
| 35 | +/// This pattern supports lowering of: `vector.maskedload` to `vector.load` |
| 36 | +/// and `arith.select` if the memref is in buffer address space. |
| 37 | +static LogicalResult baseInBufferAddrSpace(PatternRewriter &rewriter, |
| 38 | + vector::MaskedLoadOp maskedOp) { |
| 39 | + auto memRefType = dyn_cast<MemRefType>(maskedOp.getBase().getType()); |
| 40 | + if (!memRefType) |
| 41 | + return rewriter.notifyMatchFailure(maskedOp, "not a memref source"); |
| 42 | + |
| 43 | + Attribute addrSpace = memRefType.getMemorySpace(); |
| 44 | + if (!isa_and_nonnull<amdgpu::AddressSpaceAttr>(addrSpace)) |
| 45 | + return rewriter.notifyMatchFailure(maskedOp, "no address space"); |
| 46 | + |
| 47 | + if (dyn_cast<amdgpu::AddressSpaceAttr>(addrSpace).getValue() != |
| 48 | + amdgpu::AddressSpace::FatRawBuffer) |
| 49 | + return rewriter.notifyMatchFailure(maskedOp, "not in buffer address space"); |
| 50 | + |
| 51 | + return success(); |
| 52 | +} |
| 53 | + |
| 54 | +static Value createVectorLoadForMaskedLoad(OpBuilder &builder, Location loc, |
| 55 | + vector::MaskedLoadOp maskedOp) { |
| 56 | + VectorType vectorType = maskedOp.getVectorType(); |
| 57 | + Value load = builder.create<vector::LoadOp>( |
| 58 | + loc, vectorType, maskedOp.getBase(), maskedOp.getIndices()); |
| 59 | + Value res = builder.create<arith::SelectOp>( |
| 60 | + loc, vectorType, maskedOp.getMask(), load, maskedOp.getPassThru()); |
| 61 | + return res; |
| 62 | +} |
| 63 | + |
| 64 | +static constexpr char kMaskedloadNeedsMask[] = |
| 65 | + "amdgpu.buffer_maskedload_needs_mask"; |
| 66 | + |
| 67 | +namespace { |
| 68 | + |
| 69 | +struct MaskedLoadLowering final : OpRewritePattern<vector::MaskedLoadOp> { |
| 70 | + using OpRewritePattern::OpRewritePattern; |
| 71 | + |
| 72 | + LogicalResult matchAndRewrite(vector::MaskedLoadOp maskedOp, |
| 73 | + PatternRewriter &rewriter) const override { |
| 74 | + if (maskedOp->hasAttr(kMaskedloadNeedsMask)) |
| 75 | + return failure(); |
| 76 | + |
| 77 | + if (failed(baseInBufferAddrSpace(rewriter, maskedOp))) { |
| 78 | + return failure(); |
| 79 | + } |
| 80 | + |
| 81 | + Location loc = maskedOp.getLoc(); |
| 82 | + Value src = maskedOp.getBase(); |
| 83 | + |
| 84 | + VectorType vectorType = maskedOp.getVectorType(); |
| 85 | + int64_t vectorSize = vectorType.getNumElements(); |
| 86 | + int64_t elementBitWidth = vectorType.getElementTypeBitWidth(); |
| 87 | + SmallVector<OpFoldResult> indices = maskedOp.getIndices(); |
| 88 | + |
| 89 | + auto stridedMetadata = |
| 90 | + rewriter.create<memref::ExtractStridedMetadataOp>(loc, src); |
| 91 | + SmallVector<OpFoldResult> strides = |
| 92 | + stridedMetadata.getConstifiedMixedStrides(); |
| 93 | + SmallVector<OpFoldResult> sizes = stridedMetadata.getConstifiedMixedSizes(); |
| 94 | + OpFoldResult offset = stridedMetadata.getConstifiedMixedOffset(); |
| 95 | + memref::LinearizedMemRefInfo linearizedInfo; |
| 96 | + OpFoldResult linearizedIndices; |
| 97 | + std::tie(linearizedInfo, linearizedIndices) = |
| 98 | + memref::getLinearizedMemRefOffsetAndSize(rewriter, loc, elementBitWidth, |
| 99 | + elementBitWidth, offset, sizes, |
| 100 | + strides, indices); |
| 101 | + |
| 102 | + // delta = bufferSize - linearizedOffset |
| 103 | + Value vectorSizeOffset = |
| 104 | + rewriter.create<arith::ConstantIndexOp>(loc, vectorSize); |
| 105 | + Value linearIndex = |
| 106 | + getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices); |
| 107 | + Value totalSize = getValueOrCreateConstantIndexOp( |
| 108 | + rewriter, loc, linearizedInfo.linearizedSize); |
| 109 | + Value delta = rewriter.create<arith::SubIOp>(loc, totalSize, linearIndex); |
| 110 | + |
| 111 | + // 1) check if delta < vectorSize |
| 112 | + Value isOutofBounds = rewriter.create<arith::CmpIOp>( |
| 113 | + loc, arith::CmpIPredicate::ult, delta, vectorSizeOffset); |
| 114 | + |
| 115 | + // 2) check if (detla % elements_per_word != 0) |
| 116 | + Value elementsPerWord = rewriter.create<arith::ConstantIndexOp>( |
| 117 | + loc, llvm::divideCeil(32, elementBitWidth)); |
| 118 | + Value isNotWordAligned = rewriter.create<arith::CmpIOp>( |
| 119 | + loc, arith::CmpIPredicate::ne, |
| 120 | + rewriter.create<arith::RemUIOp>(loc, delta, elementsPerWord), |
| 121 | + rewriter.create<arith::ConstantIndexOp>(loc, 0)); |
| 122 | + |
| 123 | + // We take the fallback of maskedload default lowering only it is both |
| 124 | + // out-of-bounds and not word aligned. The fallback ensures correct results |
| 125 | + // when loading at the boundary of the buffer since buffer load returns |
| 126 | + // inconsistent zeros for the whole word when boundary is crossed. |
| 127 | + Value ifCondition = |
| 128 | + rewriter.create<arith::AndIOp>(loc, isOutofBounds, isNotWordAligned); |
| 129 | + |
| 130 | + auto thenBuilder = [&](OpBuilder &builder, Location loc) { |
| 131 | + Operation *read = builder.clone(*maskedOp.getOperation()); |
| 132 | + read->setAttr(kMaskedloadNeedsMask, builder.getUnitAttr()); |
| 133 | + Value readResult = read->getResult(0); |
| 134 | + builder.create<scf::YieldOp>(loc, readResult); |
| 135 | + }; |
| 136 | + |
| 137 | + auto elseBuilder = [&](OpBuilder &builder, Location loc) { |
| 138 | + Value res = createVectorLoadForMaskedLoad(builder, loc, maskedOp); |
| 139 | + rewriter.create<scf::YieldOp>(loc, res); |
| 140 | + }; |
| 141 | + |
| 142 | + auto ifOp = |
| 143 | + rewriter.create<scf::IfOp>(loc, ifCondition, thenBuilder, elseBuilder); |
| 144 | + |
| 145 | + rewriter.replaceOp(maskedOp, ifOp); |
| 146 | + |
| 147 | + return success(); |
| 148 | + } |
| 149 | +}; |
| 150 | + |
| 151 | +} // namespace |
| 152 | + |
| 153 | +void mlir::amdgpu::populateAmdgpuMaskedloadToLoadPatterns( |
| 154 | + RewritePatternSet &patterns, PatternBenefit benefit) { |
| 155 | + patterns.add<MaskedLoadLowering>(patterns.getContext(), benefit); |
| 156 | +} |
| 157 | + |
| 158 | +struct AmdgpuMaskedloadToLoadPass final |
| 159 | + : amdgpu::impl::AmdgpuMaskedloadToLoadPassBase<AmdgpuMaskedloadToLoadPass> { |
| 160 | + void runOnOperation() override { |
| 161 | + RewritePatternSet patterns(&getContext()); |
| 162 | + populateAmdgpuMaskedloadToLoadPatterns(patterns); |
| 163 | + if (failed(applyPatternsGreedily(getOperation(), std::move(patterns)))) { |
| 164 | + return signalPassFailure(); |
| 165 | + } |
| 166 | + } |
| 167 | +}; |
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