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[RISCV] Remove Predicates from classes in RISCVInstrInfoXTHead.td. NFC
All of instantiations of these classes also specify Predicates making the base class redundant or unnecessary. The Predicates on the instantiations aren't always the same as the base class so those are needed. Also move the DecoderNamespace to the instantiations for consistency with the Predicates.
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llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,7 @@ class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
7676
}
7777
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
7878

79-
let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa",
80-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
79+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
8180
class THShiftALU_rri<bits<3> funct3, string opcodestr>
8281
: RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
8382
(ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
@@ -87,13 +86,13 @@ class THShiftALU_rri<bits<3> funct3, string opcodestr>
8786
let Inst{26-25} = uimm2;
8887
}
8988

90-
let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb",
91-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
89+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
9290
class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
9391
: RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
9492
(ins GPR:$rs1, uimmlog2xlen:$shamt),
9593
opcodestr, "$rd, $rs1, $shamt">;
9694

95+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
9796
class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
9897
: RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
9998
(ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
@@ -104,38 +103,34 @@ class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
104103
let Inst{25-20} = lsb;
105104
}
106105

106+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
107107
class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
108108
: RVInstIUnary<{funct5, funct2, 0b00000}, 0b001, OPC_CUSTOM_0,
109109
(outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
110-
}
111110

112-
let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
113-
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
111+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
114112
class THShiftW_ri<bits<7> funct7, bits<3> funct3, string opcodestr>
115113
: RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
116114
(ins GPR:$rs1, uimm5:$shamt),
117115
opcodestr, "$rd, $rs1, $shamt">;
118116

119-
let Predicates = [HasVendorXTHeadCondMov], DecoderNamespace = "XTHeadCondMov",
120-
hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
117+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
121118
class THCondMov_rr<bits<7> funct7, string opcodestr>
122119
: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
123120
(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
124121
opcodestr, "$rd, $rs1, $rs2"> {
125122
let Constraints = "$rd_wb = $rd";
126123
}
127124

128-
let Predicates = [HasVendorXTHeadMac], DecoderNamespace = "XTHeadMac",
129-
hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
125+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
130126
class THMulAccumulate_rr<bits<7> funct7, string opcodestr>
131127
: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
132128
(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
133129
opcodestr, "$rd, $rs1, $rs2"> {
134130
let Constraints = "$rd_wb = $rd";
135131
}
136132

137-
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
138-
hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
133+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
139134
class THLoadPair<bits<5> funct5, string opcodestr>
140135
: RVInstRBase<0b100, OPC_CUSTOM_0,
141136
(outs GPR:$rd, GPR:$rs2),
@@ -148,8 +143,7 @@ class THLoadPair<bits<5> funct5, string opcodestr>
148143
let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
149144
}
150145

151-
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
152-
hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
146+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
153147
class THStorePair<bits<5> funct5, string opcodestr>
154148
: RVInstRBase<0b101, OPC_CUSTOM_0, (outs),
155149
(ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
@@ -249,11 +243,11 @@ multiclass THVdotVMAQA<string opcodestr, bits<6> funct6>
249243
// Instructions
250244
//===----------------------------------------------------------------------===//
251245

252-
let Predicates = [HasVendorXTHeadBa] in
246+
let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa" in
253247
def TH_ADDSL : THShiftALU_rri<0b001, "th.addsl">,
254248
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
255249

256-
let Predicates = [HasVendorXTHeadBb] in {
250+
let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb" in {
257251
def TH_SRRI : THShift_ri<0b00010, 0b001, "th.srri">;
258252
def TH_EXT : THBitfieldExtract_rii<0b010, "th.ext">;
259253
def TH_EXTU : THBitfieldExtract_rii<0b011, "th.extu">;
@@ -263,7 +257,8 @@ def TH_REV : THRev_r<0b10000, 0b01, "th.rev">;
263257
def TH_TSTNBZ : THRev_r<0b10000, 0b00, "th.tstnbz">;
264258
} // Predicates = [HasVendorXTHeadBb]
265259

266-
let Predicates = [HasVendorXTHeadBb, IsRV64], IsSignExtendingOpW = 1 in {
260+
let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
261+
IsSignExtendingOpW = 1 in {
267262
def TH_SRRIW : THShiftW_ri<0b0001010, 0b001, "th.srriw">;
268263
def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;
269264
} // Predicates = [HasVendorXTHeadBb, IsRV64]
@@ -273,11 +268,13 @@ let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "XTHeadBs",
273268
def TH_TST : THShift_ri<0b10001, 0b001, "th.tst">,
274269
Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
275270

276-
let Predicates = [HasVendorXTHeadCondMov] in {
271+
let Predicates = [HasVendorXTHeadCondMov],
272+
DecoderNamespace = "XTHeadCondMov" in {
277273
def TH_MVEQZ : THCondMov_rr<0b0100000, "th.mveqz">;
278274
def TH_MVNEZ : THCondMov_rr<0b0100001, "th.mvnez">;
279275
} // Predicates = [HasVendorXTHeadCondMov]
280276

277+
let DecoderNamespace = "XTHeadMac" in {
281278
let Predicates = [HasVendorXTHeadMac] in {
282279
def TH_MULA : THMulAccumulate_rr<0b0010000, "th.mula">;
283280
def TH_MULS : THMulAccumulate_rr<0b0010001, "th.muls">;
@@ -292,7 +289,9 @@ let Predicates = [HasVendorXTHeadMac, IsRV64], IsSignExtendingOpW = 1 in {
292289
def TH_MULAW : THMulAccumulate_rr<0b0010010, "th.mulaw">;
293290
def TH_MULSW : THMulAccumulate_rr<0b0010011, "th.mulsw">;
294291
} // Predicates = [HasVendorXTHeadMac, IsRV64]
292+
} // DecoderNamespace = "XTHeadMac"
295293

294+
let DecoderNamespace = "XTHeadMemPair" in {
296295
let Predicates = [HasVendorXTHeadMemPair] in {
297296
def TH_LWUD : THLoadPair<0b11110, "th.lwud">,
298297
Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
@@ -309,6 +308,7 @@ def TH_LDD : THLoadPair<0b11111, "th.ldd">,
309308
def TH_SDD : THStorePair<0b11111, "th.sdd">,
310309
Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
311310
}
311+
} // DecoderNamespace = "XTHeadMemPair"
312312

313313
let Predicates = [HasVendorXTHeadMemIdx], DecoderNamespace = "XTHeadMemIdx" in {
314314
// T-Head Load/Store + Update instructions.

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