@@ -76,8 +76,7 @@ class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
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}
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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- let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa",
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- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class THShiftALU_rri<bits<3> funct3, string opcodestr>
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: RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
@@ -87,13 +86,13 @@ class THShiftALU_rri<bits<3> funct3, string opcodestr>
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let Inst{26-25} = uimm2;
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}
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- let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb",
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- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
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: RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
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(ins GPR:$rs1, uimmlog2xlen:$shamt),
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opcodestr, "$rd, $rs1, $shamt">;
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
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: RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
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(ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
@@ -104,38 +103,34 @@ class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
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let Inst{25-20} = lsb;
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}
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
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: RVInstIUnary<{funct5, funct2, 0b00000}, 0b001, OPC_CUSTOM_0,
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(outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
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- }
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- let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
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- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class THShiftW_ri<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
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(ins GPR:$rs1, uimm5:$shamt),
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opcodestr, "$rd, $rs1, $shamt">;
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- let Predicates = [HasVendorXTHeadCondMov], DecoderNamespace = "XTHeadCondMov",
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- hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
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class THCondMov_rr<bits<7> funct7, string opcodestr>
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: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
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(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs1, $rs2"> {
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let Constraints = "$rd_wb = $rd";
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}
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- let Predicates = [HasVendorXTHeadMac], DecoderNamespace = "XTHeadMac",
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- hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
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class THMulAccumulate_rr<bits<7> funct7, string opcodestr>
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: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
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(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs1, $rs2"> {
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let Constraints = "$rd_wb = $rd";
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}
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- let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
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- hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class THLoadPair<bits<5> funct5, string opcodestr>
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: RVInstRBase<0b100, OPC_CUSTOM_0,
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(outs GPR:$rd, GPR:$rs2),
@@ -148,8 +143,7 @@ class THLoadPair<bits<5> funct5, string opcodestr>
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let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
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}
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- let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
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- hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class THStorePair<bits<5> funct5, string opcodestr>
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: RVInstRBase<0b101, OPC_CUSTOM_0, (outs),
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(ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
@@ -249,11 +243,11 @@ multiclass THVdotVMAQA<string opcodestr, bits<6> funct6>
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// Instructions
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//===----------------------------------------------------------------------===//
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- let Predicates = [HasVendorXTHeadBa] in
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+ let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa" in
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def TH_ADDSL : THShiftALU_rri<0b001, "th.addsl">,
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Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
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- let Predicates = [HasVendorXTHeadBb] in {
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+ let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb" in {
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def TH_SRRI : THShift_ri<0b00010, 0b001, "th.srri">;
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def TH_EXT : THBitfieldExtract_rii<0b010, "th.ext">;
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def TH_EXTU : THBitfieldExtract_rii<0b011, "th.extu">;
@@ -263,7 +257,8 @@ def TH_REV : THRev_r<0b10000, 0b01, "th.rev">;
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def TH_TSTNBZ : THRev_r<0b10000, 0b00, "th.tstnbz">;
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} // Predicates = [HasVendorXTHeadBb]
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- let Predicates = [HasVendorXTHeadBb, IsRV64], IsSignExtendingOpW = 1 in {
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+ let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
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+ IsSignExtendingOpW = 1 in {
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def TH_SRRIW : THShiftW_ri<0b0001010, 0b001, "th.srriw">;
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def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;
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} // Predicates = [HasVendorXTHeadBb, IsRV64]
@@ -273,11 +268,13 @@ let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "XTHeadBs",
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def TH_TST : THShift_ri<0b10001, 0b001, "th.tst">,
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Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
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- let Predicates = [HasVendorXTHeadCondMov] in {
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+ let Predicates = [HasVendorXTHeadCondMov],
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+ DecoderNamespace = "XTHeadCondMov" in {
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def TH_MVEQZ : THCondMov_rr<0b0100000, "th.mveqz">;
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def TH_MVNEZ : THCondMov_rr<0b0100001, "th.mvnez">;
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} // Predicates = [HasVendorXTHeadCondMov]
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+ let DecoderNamespace = "XTHeadMac" in {
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let Predicates = [HasVendorXTHeadMac] in {
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def TH_MULA : THMulAccumulate_rr<0b0010000, "th.mula">;
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def TH_MULS : THMulAccumulate_rr<0b0010001, "th.muls">;
@@ -292,7 +289,9 @@ let Predicates = [HasVendorXTHeadMac, IsRV64], IsSignExtendingOpW = 1 in {
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def TH_MULAW : THMulAccumulate_rr<0b0010010, "th.mulaw">;
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def TH_MULSW : THMulAccumulate_rr<0b0010011, "th.mulsw">;
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} // Predicates = [HasVendorXTHeadMac, IsRV64]
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+ } // DecoderNamespace = "XTHeadMac"
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+ let DecoderNamespace = "XTHeadMemPair" in {
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let Predicates = [HasVendorXTHeadMemPair] in {
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def TH_LWUD : THLoadPair<0b11110, "th.lwud">,
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Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
@@ -309,6 +308,7 @@ def TH_LDD : THLoadPair<0b11111, "th.ldd">,
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def TH_SDD : THStorePair<0b11111, "th.sdd">,
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Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
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}
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+ } // DecoderNamespace = "XTHeadMemPair"
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let Predicates = [HasVendorXTHeadMemIdx], DecoderNamespace = "XTHeadMemIdx" in {
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// T-Head Load/Store + Update instructions.
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