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jgelfman/Dataflow-Based-FPGA-Program-Synthesis-Capstone

An FPGA Program Generator written in Python that takes dsp-sig XML Dataflow Graphs created using FAUST to produce FPGA programs in VHDL.

fpga

dsp

vhdl

vivado

dataflow-compiler

• VHDL
·
• 6
·
• Updated
  on Apr 8, 2021

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