diff --git a/benchmarks/BUILD b/benchmarks/BUILD new file mode 100644 index 00000000..a66316d6 --- /dev/null +++ b/benchmarks/BUILD @@ -0,0 +1,18 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) diff --git a/benchmarks/basic/BUILD b/benchmarks/basic/BUILD new file mode 100644 index 00000000..01400ab4 --- /dev/null +++ b/benchmarks/basic/BUILD @@ -0,0 +1,20 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +exports_files(glob(["common/**"])) diff --git a/benchmarks/basic/add/BUILD b/benchmarks/basic/add/BUILD new file mode 100644 index 00000000..3e346dfe --- /dev/null +++ b/benchmarks/basic/add/BUILD @@ -0,0 +1,231 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for add """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +verilog_library( + name = "rtl", + srcs = [ + "mod_add.sv", + "top_add.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for add on asap7 with sc7p5t_rev28 +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for add on asap7 with sc7p5t_rev28 using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for add on asap7 with sc7p5t_rev28 using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for add on asap7 with sc7p5t_rev28 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for add on sky130 with sc_hd +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for add on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for add on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for add on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_add", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/add/asap7.sdc b/benchmarks/basic/add/asap7.sdc new file mode 100644 index 00000000..cabef46b --- /dev/null +++ b/benchmarks/basic/add/asap7.sdc @@ -0,0 +1 @@ +set clk_port_name "clk" \ No newline at end of file diff --git a/benchmarks/basic/add/mod_add.sv b/benchmarks/basic/add/mod_add.sv new file mode 100644 index 00000000..802e358b --- /dev/null +++ b/benchmarks/basic/add/mod_add.sv @@ -0,0 +1,8 @@ +module mod_add( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x = a + b; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/add/sky130.sdc b/benchmarks/basic/add/sky130.sdc new file mode 100644 index 00000000..3f5d1d0d --- /dev/null +++ b/benchmarks/basic/add/sky130.sdc @@ -0,0 +1,6 @@ +set clk_port_name "clk" +set clk_period 10 +set clk_half_period [format "%.5f" [expr {$clk_period / 2.0}]] + +create_clock -name clk -period $clk_period -waveform "0 $clk_half_period" \ + [get_ports -quiet $clk_port_name] \ No newline at end of file diff --git a/benchmarks/basic/add/top_add.sv b/benchmarks/basic/add/top_add.sv new file mode 100644 index 00000000..50317d6a --- /dev/null +++ b/benchmarks/basic/add/top_add.sv @@ -0,0 +1,37 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module top_add ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_add mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/benchmarks/basic/and/BUILD b/benchmarks/basic/and/BUILD new file mode 100644 index 00000000..8bdf39b9 --- /dev/null +++ b/benchmarks/basic/and/BUILD @@ -0,0 +1,231 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for and """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +verilog_library( + name = "rtl", + srcs = [ + "mod_and.sv", + "top_and.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for and on asap7 with sc7p5t_rev28 +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for and on asap7 with sc7p5t_rev28 using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for and on asap7 with sc7p5t_rev28 using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for and on asap7 with sc7p5t_rev28 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for and on sky130 with sc_hd +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for and on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for and on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for and on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_and", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/and/mod_and.sv b/benchmarks/basic/and/mod_and.sv new file mode 100644 index 00000000..daf5ac82 --- /dev/null +++ b/benchmarks/basic/and/mod_and.sv @@ -0,0 +1,8 @@ +module mod_and( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x = a & b; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/and/top_and.sv b/benchmarks/basic/and/top_and.sv new file mode 100644 index 00000000..c8593df1 --- /dev/null +++ b/benchmarks/basic/and/top_and.sv @@ -0,0 +1,37 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module top_and ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_and mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/benchmarks/basic/common/asap7.sdc b/benchmarks/basic/common/asap7.sdc new file mode 100644 index 00000000..3f5d1d0d --- /dev/null +++ b/benchmarks/basic/common/asap7.sdc @@ -0,0 +1,6 @@ +set clk_port_name "clk" +set clk_period 10 +set clk_half_period [format "%.5f" [expr {$clk_period / 2.0}]] + +create_clock -name clk -period $clk_period -waveform "0 $clk_half_period" \ + [get_ports -quiet $clk_port_name] \ No newline at end of file diff --git a/benchmarks/basic/common/place.diagonal.tcl b/benchmarks/basic/common/place.diagonal.tcl new file mode 100644 index 00000000..712452c9 --- /dev/null +++ b/benchmarks/basic/common/place.diagonal.tcl @@ -0,0 +1,64 @@ +set db [ord::get_db_block] + +set core_area [$db getCoreArea] +set core_area_x0 [$core_area xMin] +set core_area_x1 [$core_area xMax] +set core_area_width [expr {$core_area_x1 - $core_area_x0}] + +set core_area_y0 [$core_area yMin] +set core_area_y1 [$core_area yMax] +set core_area_height [expr {$core_area_y1 - $core_area_y0}] + +puts "\nCoreArea (($core_area_x0,$core_area_y0) ($core_area_x1,$core_area_y1)) ($core_area_width x $core_area_height)\n" + +set dff0 [$db findInst "mod.a0_\$_DFF_P__Q"] +set dff0_bbox [$dff0 getBBox] +set dff0_width [$dff0_bbox getDX] +set dff0_height [$dff0_bbox getDY] + +puts "\nDFF size is $dff0_width x $dff0_height\n" + +puts "\nUsing diagonal placement" +puts " * Inputs A on left edge" +puts " * Inputs B on top edge" +puts " * Outputs X on right edge" + +set pad 0 + +set y0 [expr {$core_area_y0 + $pad}] +set x0 [expr {$core_area_x0 + $pad}] +set xn [expr {$core_area_x1 - $dff0_width - $pad}] + +set flops 8 + +set y_group_size [expr {$core_area_height / ($flops + 2)}] +set x_group_size [expr {$core_area_width / ($flops + 2)}] + +set y [expr {$y0 + $y_group_size / 2 + $y_group_size}] +set x [expr {$x0 + $x_group_size / 2 + $x_group_size}] + +for {set i 0} {$i < $flops} {incr i} { + set a_dff_name "mod.a$i\_\$_DFF_P__Q" + set a_dff [$db findInst $a_dff_name] + $a_dff setLocation $x0 $y + $a_dff setPlacementStatus "PLACED" + puts "Placed on left edge $a_dff_name @ ($x0 $y)" + + set x_dff_name "x$i\_\$_DFF_P__Q" + set x_dff [$db findInst $x_dff_name] + $x_dff setLocation $xn $y + $x_dff setPlacementStatus "PLACED" + puts "Placed on right $x_dff_name @ ($xn $y)" + + set y [expr {$y + $y_group_size}] + + set b_dff_name "mod.b$i\_\$_DFF_P__Q" + set b_dff [$db findInst $b_dff_name] + $b_dff setLocation $x $y0 + $b_dff setPlacementStatus "PLACED" + puts "Placed on top edge $b_dff_name @ ($x $y0)" + + set x [expr {$x + $x_group_size}] + + puts "" +} diff --git a/benchmarks/basic/common/place.loopback.tcl b/benchmarks/basic/common/place.loopback.tcl new file mode 100644 index 00000000..bd3b553f --- /dev/null +++ b/benchmarks/basic/common/place.loopback.tcl @@ -0,0 +1,64 @@ +set db [ord::get_db_block] + +set core_area [$db getCoreArea] +set core_area_x0 [$core_area xMin] +set core_area_x1 [$core_area xMax] +set core_area_width [expr {$core_area_x1 - $core_area_x0}] + +set core_area_y0 [$core_area yMin] +set core_area_y1 [$core_area yMax] +set core_area_height [expr {$core_area_y1 - $core_area_y0}] + +puts "\nCoreArea (($core_area_x0,$core_area_y0) ($core_area_x1,$core_area_y1)) ($core_area_width x $core_area_height)\n" + +set dff0 [$db findInst "mod.a0_\$_DFF_P__Q"] +set dff0_bbox [$dff0 getBBox] +set dff0_width [$dff0_bbox getDX] +set dff0_height [$dff0_bbox getDY] + +puts "\nDFF size is $dff0_width x $dff0_height\n" + +puts "\nUsing loopback placement" +puts " * Inputs A on left edge" +puts " * Inputs B on left edge" +puts " * Outputs X on left edge" + +set pad 0 + +set y0 [expr {$core_area_y0 + $pad}] + +set x0 [expr {$core_area_x0 + $pad}] +set xn [expr {$core_area_x1 - $dff0_width - $pad}] + +set flops 8 + +set y_ff_offset [expr {$dff0_height * 2}] +set y_group_size [expr {$core_area_height / ($flops + 2)}] + +set y [expr {$y0 + $y_group_size / 2 + $y_group_size}] + +for {set i 0} {$i < $flops} {incr i} { + set a_dff_name "mod.a$i\_\$_DFF_P__Q" + set a_dff [$db findInst $a_dff_name] + set y_a $y + $a_dff setLocation $x0 $y_a + $a_dff setPlacementStatus "PLACED" + puts "Placed on left edge $a_dff_name @ ($x0 $y_a)" + + set b_dff_name "mod.b$i\_\$_DFF_P__Q" + set b_dff [$db findInst $b_dff_name] + set y_b [expr {$y + $y_ff_offset}] + $b_dff setLocation $x0 $y_b + $b_dff setPlacementStatus "PLACED" + puts "Placed on left edge $b_dff_name @ ($x0 $y_b)" + + set x_dff_name "x$i\_\$_DFF_P__Q" + set x_dff [$db findInst $x_dff_name] + set y_x [expr {$y + $y_ff_offset * 2}] + $x_dff setLocation $x0 $y_x + $x_dff setPlacementStatus "PLACED" + puts "Placed on left edge $x_dff_name @ ($x0 $y_x)" + + set y [expr {$y + $y_group_size}] + puts "" +} diff --git a/benchmarks/basic/common/place.straight.tcl b/benchmarks/basic/common/place.straight.tcl new file mode 100644 index 00000000..80bf4341 --- /dev/null +++ b/benchmarks/basic/common/place.straight.tcl @@ -0,0 +1,62 @@ +set db [ord::get_db_block] + +set core_area [$db getCoreArea] +set core_area_x0 [$core_area xMin] +set core_area_x1 [$core_area xMax] +set core_area_width [expr {$core_area_x1 - $core_area_x0}] + +set core_area_y0 [$core_area yMin] +set core_area_y1 [$core_area yMax] +set core_area_height [expr {$core_area_y1 - $core_area_y0}] + +puts "\nCoreArea (($core_area_x0,$core_area_y0) ($core_area_x1,$core_area_y1)) ($core_area_width x $core_area_height)\n" + +set dff0 [$db findInst "mod.a0_\$_DFF_P__Q"] +set dff0_bbox [$dff0 getBBox] +set dff0_width [$dff0_bbox getDX] +set dff0_height [$dff0_bbox getDY] + +puts "\nDFF size is $dff0_width x $dff0_height\n" + +puts "\nUsing 'straight' placement" +puts " * Inputs A on left edge" +puts " * Inputs B on left edge" +puts " * Outputs X on right edge" + +set pad 0 + +set y0 [expr {$core_area_y0 + $pad}] + +set x0 [expr {$core_area_x0 + $pad}] +set xn [expr {$core_area_x1 - $dff0_width - $pad}] + +set flops 8 + +set y_ff_offset [expr {$dff0_height * 2}] +set y_group_size [expr {$core_area_height / ($flops + 2)}] + +set y [expr {$y0 + $y_group_size / 2 + $y_group_size}] + +for {set i 0} {$i < $flops} {incr i} { + set a_dff_name "mod.a$i\_\$_DFF_P__Q" + set a_dff [$db findInst $a_dff_name] + $a_dff setLocation $x0 $y + $a_dff setPlacementStatus "PLACED" + puts "Placed $a_dff_name @ ($x0 $y)" + + set b_dff_name "mod.b$i\_\$_DFF_P__Q" + set b_dff [$db findInst $b_dff_name] + set y_b [expr {$y + $y_ff_offset}] + $b_dff setLocation $x0 $y_b + $b_dff setPlacementStatus "PLACED" + puts "Placed $b_dff_name @ ($x0 $y_b)" + + set x_dff_name "x$i\_\$_DFF_P__Q" + set x_dff [$db findInst $x_dff_name] + $x_dff setLocation $xn $y + $x_dff setPlacementStatus "PLACED" + puts "Placed $x_dff_name @ ($xn $y)" + + set y [expr {$y + $y_group_size}] + puts "" +} diff --git a/benchmarks/basic/common/sky130.sdc b/benchmarks/basic/common/sky130.sdc new file mode 100644 index 00000000..3f5d1d0d --- /dev/null +++ b/benchmarks/basic/common/sky130.sdc @@ -0,0 +1,6 @@ +set clk_port_name "clk" +set clk_period 10 +set clk_half_period [format "%.5f" [expr {$clk_period / 2.0}]] + +create_clock -name clk -period $clk_period -waveform "0 $clk_half_period" \ + [get_ports -quiet $clk_port_name] \ No newline at end of file diff --git a/benchmarks/basic/genbuild.py b/benchmarks/basic/genbuild.py new file mode 100755 index 00000000..47dea37b --- /dev/null +++ b/benchmarks/basic/genbuild.py @@ -0,0 +1,183 @@ +#!/usr/bin/env python3 +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +import pathlib +import subprocess + +LICENSE = [] +with open(__file__) as f: + while True: + l = next(f) + if not l.startswith("#!"): + break + while l.startswith('#'): + LICENSE.append(l[1:]) + l = next(f) + +PDKS = { + "asap7": { + "libraries": ["sc7p5t_rev28"], + "pnr": { + "core_padding_microns": 2, + "die_height_microns": 400, + "die_width_microns": 400, + "skip_detailed_routing": False, + } + }, + "sky130": { + "libraries": ['sc_hd'], + "pnr": { + "core_padding_microns": 2, + "die_height_microns": 200, + "die_width_microns": 100, + "skip_detailed_routing": False, + } + }, +} + +FILE_DIR = pathlib.Path(__file__).parent + +MODULES = [ + "and", + "xand", + "add", + "mul", +] + +PLACEMENT = [ + "straight", + "loopback", + "diagonal", +] + +for MOD_NAME in MODULES: + with open(FILE_DIR / MOD_NAME / f"top_{MOD_NAME}.sv", "w", encoding="utf-8") as top_file: + top_file.write(''.join('//'+l for l in LICENSE)) + top_file.write(f""" +module top_{MOD_NAME} ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_{MOD_NAME} mod (.a(a_), .b(b_), .x(i_)); + +endmodule +""") + + build_file_name = FILE_DIR / MOD_NAME / f"BUILD" + print("Writing ", build_file_name, "...") + with open(build_file_name, "w", encoding="utf-8") as build_file: + build_file.write(''.join('#'+l for l in LICENSE)) + build_file.write(f''' +""" Benchmark for {MOD_NAME} """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +verilog_library( + name = "rtl", + srcs = [ + "top_{MOD_NAME}.sv", + "mod_{MOD_NAME}.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) +''') + + for PDK_NAME, PDK_CONFIG in PDKS.items(): + for LIB in PDK_CONFIG['libraries']: + build_file.write(f""" +# Run for {MOD_NAME} on {PDK_NAME} with {LIB} +[ + basic_asic_flow( + name = 'basic-' + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = {PDK_CONFIG['pnr']['core_padding_microns']}, + die_height_microns = {PDK_CONFIG['pnr']['die_height_microns']}, + die_width_microns = {PDK_CONFIG['pnr']['die_width_microns']}, + sdc = "@rules_hdl//benchmarks/basic:common/{PDK_NAME}.sdc", + skip_detailed_routing = {PDK_CONFIG['pnr']['skip_detailed_routing']}, + exec_properties = dict( + mem = '16g', + ), + ), + ), + target = ":rtl", + top = "top_{MOD_NAME}", + ) + for cell_name, cell_target in for_each_{PDK_NAME}_cells("{LIB}") +] +""") + + for PLACE in PLACEMENT: + build_file.write(f""" +# Run for {MOD_NAME} on {PDK_NAME} with {LIB} using {PLACE} placement. +[ + basic_asic_flow( + name = "{PLACE}-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + sdc = "@rules_hdl//benchmarks/basic:common/{PDK_NAME}.sdc", + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.{PLACE}.tcl", + skip_detailed_routing = {PDK_CONFIG['pnr']['skip_detailed_routing']}, + core_padding_microns = {PDK_CONFIG['pnr']['core_padding_microns']}, + die_height_microns = {PDK_CONFIG['pnr']['die_height_microns']}, + die_width_microns = {PDK_CONFIG['pnr']['die_width_microns']}, + exec_properties = dict( + mem = '16g', + ), + ), + ), + target = ":rtl", + top = "top_{MOD_NAME}", + ) + for cell_name, cell_target in for_each_{PDK_NAME}_cells("{LIB}") +] +""") + + subprocess.check_call(f"buildifier {build_file_name}", shell=True) diff --git a/benchmarks/basic/mul/BUILD b/benchmarks/basic/mul/BUILD new file mode 100644 index 00000000..50c2ed4a --- /dev/null +++ b/benchmarks/basic/mul/BUILD @@ -0,0 +1,231 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for mul """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +verilog_library( + name = "rtl", + srcs = [ + "mod_mul.sv", + "top_mul.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for mul on asap7 with sc7p5t_rev28 +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for mul on asap7 with sc7p5t_rev28 using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for mul on asap7 with sc7p5t_rev28 using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for mul on asap7 with sc7p5t_rev28 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for mul on sky130 with sc_hd +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for mul on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for mul on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for mul on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_mul", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/mul/mod_mul.sv b/benchmarks/basic/mul/mod_mul.sv new file mode 100644 index 00000000..636522ac --- /dev/null +++ b/benchmarks/basic/mul/mod_mul.sv @@ -0,0 +1,8 @@ +module mod_mul( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x = a * b; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/mul/top_mul.sv b/benchmarks/basic/mul/top_mul.sv new file mode 100644 index 00000000..03a0bde1 --- /dev/null +++ b/benchmarks/basic/mul/top_mul.sv @@ -0,0 +1,37 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module top_mul ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_mul mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/benchmarks/basic/xand/BUILD b/benchmarks/basic/xand/BUILD new file mode 100644 index 00000000..0033eda7 --- /dev/null +++ b/benchmarks/basic/xand/BUILD @@ -0,0 +1,231 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" Benchmark for xand """ + +load("@bazel_skylib//rules:build_test.bzl", "build_test") +load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "for_each_sky130_cells") +load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cells_info.bzl", "for_each_asap7_cells") +load("//flows:basic_asic.bzl", "basic_asic_flow") +load("//verilog:providers.bzl", "verilog_library") + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) + +verilog_library( + name = "rtl", + srcs = [ + "mod_xand.sv", + "top_xand.sv", + ], +) + +build_test( + name = "rtl_build_test", + targets = [ + ":rtl", + ], +) + +# Run for xand on asap7 with sc7p5t_rev28 +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for xand on asap7 with sc7p5t_rev28 using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for xand on asap7 with sc7p5t_rev28 using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for xand on asap7 with sc7p5t_rev28 using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 400, + die_width_microns = 400, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/asap7.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_asap7_cells("sc7p5t_rev28") +] + +# Run for xand on sky130 with sc_hd +[ + basic_asic_flow( + name = "basic-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for xand on sky130 with sc_hd using straight placement. +[ + basic_asic_flow( + name = "straight-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.straight.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for xand on sky130 with sc_hd using loopback placement. +[ + basic_asic_flow( + name = "loopback-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.loopback.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] + +# Run for xand on sky130 with sc_hd using diagonal placement. +[ + basic_asic_flow( + name = "diagonal-" + cell_name, + cells = cell_target, + extra_args = dict( + place_and_route = dict( + core_padding_microns = 2, + die_height_microns = 200, + die_width_microns = 100, + exec_properties = dict( + mem = "16g", + ), + manual_placement_script = "@rules_hdl//benchmarks/basic:common/place.diagonal.tcl", + sdc = "@rules_hdl//benchmarks/basic:common/sky130.sdc", + skip_detailed_routing = False, + ), + ), + target = ":rtl", + top = "top_xand", + ) + for cell_name, cell_target in for_each_sky130_cells("sc_hd") +] diff --git a/benchmarks/basic/xand/mod_xand.sv b/benchmarks/basic/xand/mod_xand.sv new file mode 100644 index 00000000..ca690a1d --- /dev/null +++ b/benchmarks/basic/xand/mod_xand.sv @@ -0,0 +1,15 @@ +module mod_xand( + input wire [7:0] a, + input wire [7:0] b, + output wire [7:0] x +); + + assign x[0] = a[0] & b[0]; + assign x[1] = x[0] & a[1] & b[1]; + assign x[2] = x[1] & a[2] & b[2]; + assign x[3] = x[2] & a[3] & b[3]; + assign x[4] = x[3] & a[4] & b[4]; + assign x[5] = x[4] & a[5] & b[5]; + assign x[6] = x[5] & a[6] & b[6]; + assign x[7] = x[6] & a[7] & b[7]; +endmodule \ No newline at end of file diff --git a/benchmarks/basic/xand/top_xand.sv b/benchmarks/basic/xand/top_xand.sv new file mode 100644 index 00000000..2fb1b432 --- /dev/null +++ b/benchmarks/basic/xand/top_xand.sv @@ -0,0 +1,37 @@ +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module top_xand ( + input wire clk, + input wire [7:0] a, + input wire [7:0] b, + output reg [7:0] x +); + + reg [7:0] a_; + reg [7:0] b_; + wire [7:0] i_; + + always_ff @ (posedge clk) + a_ <= a; + + always_ff @ (posedge clk) + b_ <= b; + + always_ff @ (posedge clk) + x <= i_; + + mod_xand mod (.a(a_), .b(b_), .x(i_)); + +endmodule diff --git a/dependency_support/com_github_mithro_vlsiffra_hdl_library/BUILD b/dependency_support/com_github_mithro_vlsiffra_hdl_library/BUILD new file mode 100644 index 00000000..a66316d6 --- /dev/null +++ b/dependency_support/com_github_mithro_vlsiffra_hdl_library/BUILD @@ -0,0 +1,18 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +package( + default_applicable_licenses = ["//:package_license"], + default_visibility = ["//visibility:private"], +) diff --git a/dependency_support/com_github_mithro_vlsiffra_hdl_library/bundled.BUILD.bazel b/dependency_support/com_github_mithro_vlsiffra_hdl_library/bundled.BUILD.bazel new file mode 100644 index 00000000..5cde0bc8 --- /dev/null +++ b/dependency_support/com_github_mithro_vlsiffra_hdl_library/bundled.BUILD.bazel @@ -0,0 +1,32 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Description: +# Library of adders generated with the vlsiffra tooling (https://github.com/antonblanchard/vlsiffra). + +load("@rules_license//rules:license.bzl", "license") + +license( + name = "license", + package_name = "vlsiffra_hdl_library", +) + +licenses(["notice"]) + +exports_files(["LICENSE"]) + +package( + default_applicable_licenses = ["@com_github_mithro_vlsiffra_hdl_library//:license"], + default_visibility = ["//visibility:public"], +) diff --git a/dependency_support/com_github_mithro_vlsiffra_hdl_library/com_github_mithro_vlsiffra_hdl_library.bzl b/dependency_support/com_github_mithro_vlsiffra_hdl_library/com_github_mithro_vlsiffra_hdl_library.bzl new file mode 100644 index 00000000..c2af0f4c --- /dev/null +++ b/dependency_support/com_github_mithro_vlsiffra_hdl_library/com_github_mithro_vlsiffra_hdl_library.bzl @@ -0,0 +1,30 @@ +# Copyright 2024 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +"""vlsiffra-hdl-library - Library of adders.""" + +load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") +load("@bazel_tools//tools/build_defs/repo:utils.bzl", "maybe") + +def com_github_mithro_vlsiffra_hdl_library(): + maybe( + http_archive, + name = "com_github_mithro_vlsiffra_hdl_library", + urls = [ + "https://github.com/mithro/vlsiffra-hdl-library/archive/279bd99dcdb1cb0faf024d42ede842ca5ef56409.tar.gz", + ], + strip_prefix = "vlsiffra-hdl-library-1.3.1", + sha256 = "6a294f362d839ec3626e627eba9024963c9fefae04c66efea7e7131fba2baa0b", + build_file = Label("@rules_hdl//dependency_support/com_github_mithro_vlsiffra_hdl_library:bundled.BUILD.bazel"), + ) diff --git a/dependency_support/com_google_ortools/com_google_ortools.bzl b/dependency_support/com_google_ortools/com_google_ortools.bzl index f46f59f2..c8aef8a3 100644 --- a/dependency_support/com_google_ortools/com_google_ortools.bzl +++ b/dependency_support/com_google_ortools/com_google_ortools.bzl @@ -45,10 +45,11 @@ def com_google_ortools(): #url = "http://www.tcs.hut.fi/Software/bliss/bliss-0.73.zip", ) maybe( - new_git_repository, + http_archive, name = "eigen", - tag = "3.4.0", - remote = "https://gitlab.com/libeigen/eigen.git", + sha256 = "37f0a3859e42112b0b4ea4e7ba2e8167159cbb00dc6cf03cf46b877e360e6dfd", + strip_prefix = "eigen-454f89af9d6f3525b1df5f9ef9c86df58bf2d4d3", + url = "https://gitlab.com/libeigen/eigen/-/archive/454f89af9d6f3525b1df5f9ef9c86df58bf2d4d3/eigen-454f89af9d6f3525b1df5f9ef9c86df58bf2d4d3.tar.gz", build_file_content = """ cc_library( name = 'eigen3', diff --git a/dependency_support/com_google_skywater_pdk/cell_libraries.bzl b/dependency_support/com_google_skywater_pdk/cell_libraries.bzl index 5b25c1f6..19652b79 100644 --- a/dependency_support/com_google_skywater_pdk/cell_libraries.bzl +++ b/dependency_support/com_google_skywater_pdk/cell_libraries.bzl @@ -125,7 +125,7 @@ CELL_LIBRARIES = { "ff_n40C_5v50": ["basic", "ccsnoise"], "ff_n40C_5v50_lowhv1v65_lv1v95": ["basic"], "ff_n40C_5v50_lv1v95": ["basic", "ccsnoise"], - #"hvff_lvss_100C_5v50_lowhv1v65_lv1v60": ["basic"], + #"hvff_lvss_100C_5v50_lowhv1v65_lv1v60": ["basic"], #"hvff_lvss_100C_5v50_lv1v40": ["basic"], #"hvff_lvss_100C_5v50_lv1v60": ["basic"], #"hvff_lvss_n40C_5v50_lowhv1v65_lv1v60": ["basic"], diff --git a/dependency_support/com_google_skywater_pdk/cells_info.bzl b/dependency_support/com_google_skywater_pdk/cells_info.bzl index 01b0bd6a..b5a1c0ea 100644 --- a/dependency_support/com_google_skywater_pdk/cells_info.bzl +++ b/dependency_support/com_google_skywater_pdk/cells_info.bzl @@ -17,6 +17,8 @@ load("@rules_hdl//dependency_support/com_google_skywater_pdk:cell_libraries.bzl", "CELL_LIBRARIES") load("@rules_hdl//pdk:build_defs.bzl", "StandardCellOptionsInfo", "check_for_each_cells_args", "temp_normalize", "voltage_normalize") +_SKY130_CORNER_BITS = [cname.split("_") for libname in CELL_LIBRARIES for cname in CELL_LIBRARIES[libname]["corners"]] + SKY130_OPTIONS = StandardCellOptionsInfo( libraries = [ "sc_hd", @@ -28,21 +30,9 @@ SKY130_OPTIONS = StandardCellOptionsInfo( #"sc_hvl", ], vts = [], - corners = list(sorted({ - cname.split("_")[0]: None - for libname in CELL_LIBRARIES - for cname in CELL_LIBRARIES[libname]["corners"] - }.keys())), - volts = list(sorted({ - voltage_normalize(cname.split("_")[2]): None - for libname in CELL_LIBRARIES - for cname in CELL_LIBRARIES[libname]["corners"] - }.keys())), - temps = list(sorted({ - temp_normalize(cname.split("_")[1]): None - for libname in CELL_LIBRARIES - for cname in CELL_LIBRARIES[libname]["corners"] - }.keys())), + corners = [b[0] for b in _SKY130_CORNER_BITS], + volts = [b[2] for b in _SKY130_CORNER_BITS], + temps = [b[1] for b in _SKY130_CORNER_BITS], ) def sky130_cell_normalize(libname, corner_def): @@ -58,13 +48,13 @@ def sky130_cell_normalize(libname, corner_def): """ bits = corner_def.split("_") corner, temp, voltage = bits[:3] - v_extra = '' + v_extra = "" if len(bits) > 3: - v_extra += '_' - if bits[3].startswith('lowhv'): - v_extra += voltage_normalize(bits.pop(3)[6:])+'t' - if len(bits) > 3 and bits[3].startswith('lv'): - v_extra += 't'+voltage_normalize(bits.pop(3)[3:]) + v_extra += "_" + if bits[3].startswith("lowhv"): + v_extra += voltage_normalize(bits.pop(3)[6:]) + "t" + if len(bits) > 3 and bits[3].startswith("lv"): + v_extra += "t" + voltage_normalize(bits.pop(3)[3:]) if len(bits) > 3: fail("Found extra bits in corner definition {} (from '{}')".format(bits[3:], corner_def)) @@ -74,11 +64,11 @@ def sky130_cell_normalize(libname, corner_def): return "sky130-{n}-{c}-{v}_{t}".format( n = libname, c = corner, - v = voltage+v_extra, + v = voltage + v_extra, t = temp, ) -def for_each_sky130_cells(libname, include_vts = None, include_corners = None, include_volts = None, include_temps = None): +def for_each_sky130_cells(libname, include_vts = None, include_corners = None, include_volts = None, include_temps = None, include_adders = None): """Generate a list of each standard cell library name. Args: @@ -87,6 +77,7 @@ def for_each_sky130_cells(libname, include_vts = None, include_corners = None, i include_corners: 'all' or list of corners ('ff', 'tt', 'ss') to include in the output. include_volts: 'all' or list of voltages (in '0p55v' form) to include in the output. include_temps: 'all' or list of temperatures (in 'm40c' or '125c' form) to include in the output. + include_adders: 'all' or list of adder styles to include in the output. Returns: A list of tuples containing a unique name for the cell library @@ -120,6 +111,7 @@ def for_each_sky130_cells(libname, include_vts = None, include_corners = None, i "include_corners": include_corners, "include_volts": include_volts, "include_temps": include_temps, + "include_adders": include_adders, } check_for_each_cells_args(kwargs, SKY130_OPTIONS) @@ -143,8 +135,11 @@ def for_each_sky130_cells(libname, include_vts = None, include_corners = None, i if temp not in kwargs["include_temps"]: continue - cell_name = sky130_cell_normalize(libname, corner_def) - cell_target = "@com_google_skywater_pdk_sky130_fd_{l}//:{c}".format(l = libname, c = cell_name) - corners[cell_name] = cell_target + for add in kwargs["include_adders"]: + if add: + add = "-" + add + cell_name = sky130_cell_normalize(libname, corner_def) + add + cell_target = "@com_google_skywater_pdk_sky130_fd_{l}//:{c}".format(l = libname, c = cell_name) + corners[cell_name] = cell_target return list(sorted(corners.items())) diff --git a/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl b/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl index 4d8b891e..eef25424 100644 --- a/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl +++ b/dependency_support/com_google_skywater_pdk/com_google_skywater_pdk.bzl @@ -41,7 +41,7 @@ def com_google_skywater_pdk(): for library_name in CELL_LIBRARIES: library = CELL_LIBRARIES[library_name] - if library.get('library_type', None) == 'ip_library': + if library.get("library_type", None) == "ip_library": continue workspace_name = "com_google_skywater_pdk_" + library_name maybe( diff --git a/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl b/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl index 0bb6f8c7..3d858437 100644 --- a/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl +++ b/dependency_support/com_google_skywater_pdk/declare_cell_library.bzl @@ -17,6 +17,7 @@ cell library workspace to set things up.""" load("@rules_hdl//dependency_support/com_google_skywater_pdk:build_defs.bzl", "skywater_cell_library", "skywater_corner") load("@rules_hdl//dependency_support/com_google_skywater_pdk:cells_info.bzl", "sky130_cell_normalize") +load("//pdk:build_defs.bzl", "ADDER_TYPES") load(":cell_libraries.bzl", "CELL_LIBRARIES") def declare_cell_library(workspace_name, name): @@ -32,6 +33,31 @@ def declare_cell_library(workspace_name, name): visibility = ["//visibility:public"], ) library = CELL_LIBRARIES[name] + + common_args = dict( + srcs = native.glob( + include = [ + "cells/**/*.lef", + "cells/**/*.gds", + ], + # There are two types of lefs in the PDK. One for magic a layout + # tool that requires some different properties set in the LEF that + # are not always suitable for the downstream tools like OpenROAD + # and yosys. We're basically just choosing that we want the normal + # lefs instead of the magic ones. + # + # Currently this repo doesn't integrate magic into the flow. At + # some point it will, and we'll need to somehow have both lefs, or + # fix the lefs upstream. Just know that you may at some point in the + # future need to modify this. + exclude = [ + "cells/**/*.magic.lef", + ], + ), + visibility = ["//visibility:public"], + tech_lef = "tech/{}.tlef".format(name) if library.get("library_type", None) != "ip_library" else None, + ) + corners = library.get("corners", {}) all_corners = [] for corner in corners: @@ -60,59 +86,48 @@ def declare_cell_library(workspace_name, name): ) # Library with only just a single corner. - skywater_cell_library( - name = target_name, - srcs = native.glob( - include = [ - "cells/**/*.lef", - "cells/**/*.gds", - ], - # There are two types of lefs in the PDK. One for magic a layout - # tool that requires some different properties set in the LEF that - # are not always suitable for the downstream tools like OpenROAD - # and yosys. We're basically just choosing that we want the normal - # lefs instead of the magic ones. - # - # Currently this repo doesn't integrate magic into the flow. At - # some point it will, and we'll need to somehow have both lefs, or - # fix the lefs upstream. Just know that you may at some point in the - # future need to modify this. - exclude = [ - "cells/**/*.magic.lef", - ], - ), + corner_args = dict( process_corners = [":" + corner_name], default_corner = corner, + **common_args + ) + for add in ADDER_TYPES: + if add == "opt": + continue + skywater_cell_library( + name = target_name + "-" + add, + openroad_configuration = str(library.get("open_road_configuration", None)) + "-" + add, + **corner_args + ) + native.alias( + name = target_name + "-opt", + actual = ":" + target_name + "-fa", visibility = ["//visibility:public"], - openroad_configuration = library.get("open_road_configuration", None), - tech_lef = "tech/{}.tlef".format(name) if library.get("library_type", None) != "ip_library" else None, ) # Multi-corner library - skywater_cell_library( - name = name, - srcs = native.glob( - include = [ - "cells/**/*.lef", - "cells/**/*.gds", - ], - # There are two types of lefs in the PDK. One for magic a layout - # tool that requires some different properties set in the LEF that - # are not always suitable for the downstream tools like OpenROAD - # and yosys. We're basically just choosing that we want the normal - # lefs instead of the magic ones. - # - # Currently this repo doesn't integrate magic into the flow. At - # some point it will, and we'll need to somehow have both lefs, or - # fix the lefs upstream. Just know that you may at some point in the - # future need to modify this. - exclude = [ - "cells/**/*.magic.lef", - ], - ), + common_args = dict( process_corners = [":{}".format(corner) for corner in all_corners], default_corner = library.get("default_corner", ""), + **common_args + ) + for add in ADDER_TYPES: + if add == "opt": + continue + skywater_cell_library( + name = name + "-" + add, + openroad_configuration = str(library.get("open_road_configuration", None)) + "-" + add, + **common_args + ) + + # Map the "optimal" configuration to the full adder. + native.alias( + name = name + "-opt", + actual = ":" + name + "-fa", + visibility = ["//visibility:public"], + ) + native.alias( + name = name, + actual = ":" + name + "-fa", visibility = ["//visibility:public"], - openroad_configuration = library.get("open_road_configuration", None), - tech_lef = "tech/{}.tlef".format(name) if library.get("library_type", None) != "ip_library" else None, ) diff --git a/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD b/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD index c7947207..a3378152 100644 --- a/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD +++ b/dependency_support/com_google_skywater_pdk/sky130_fd_sc_hd/BUILD @@ -1,4 +1,5 @@ -load("//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") +load("//pdk:build_defs.bzl", "ADDER_MAPPINGS") +load("//pdk:open_road_configuration.bzl", "make_open_road_pdk_configuration") package( default_applicable_licenses = ["//:package_license"], @@ -11,8 +12,7 @@ exports_files([ "sky130hd.lyt", # Imported from OpenROAD-flow-scripts on 24.07.2023 at 6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8 from: https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/6ec980e1d49a1a8dcdd1e25ed81255b4bb8285c8/flow/platforms/sky130hd/sky130hd.lyt ]) -open_road_pdk_configuration( - name = "open_road_sky130_fd_sc_hd", +_open_road_pdk_configuration_common = dict( cell_site = "unithd", cts_buffer_cell = "sky130_fd_sc_hd__clkbuf_1", density_fill_config = "fill.json", @@ -44,10 +44,35 @@ open_road_pdk_configuration( tie_low_port = "sky130_fd_sc_hd__conb_1/LO", tie_separation = 5, tracks_file = "tracks.tcl", - visibility = [ - "//visibility:public", - ], + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "met5", wire_rc_signal_metal_layer = "met2", - ha_fa_mapping = "cell_adders.v" +) + +make_open_road_pdk_configuration( + name = "open_road_sky130_fd_sc_hd-nofa", + common = _open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road_sky130_fd_sc_hd-fa", + common = _open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road_sky130_fd_sc_hd-" + add, + actual = ":open_road_sky130_fd_sc_hd-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road_sky130_fd_sc_hd-opt", + actual = ":open_road_sky130_fd_sc_hd-fa", + visibility = ["//visibility:public"], ) diff --git a/dependency_support/dependency_support.bzl b/dependency_support/dependency_support.bzl index 0939f47e..e2b99b63 100644 --- a/dependency_support/dependency_support.bzl +++ b/dependency_support/dependency_support.bzl @@ -25,6 +25,7 @@ load("@rules_hdl//dependency_support/boost:boost.bzl", "boost") load("@rules_hdl//dependency_support/com_github_fmtlib_fmt:com_github_fmtlib_fmt.bzl", "com_github_fmtlib_fmt") load("@rules_hdl//dependency_support/com_github_gabime_spdlog:com_github_gabime_spdlog.bzl", "com_github_gabime_spdlog") load("@rules_hdl//dependency_support/com_github_libbacktrace:com_github_libbacktrace.bzl", "com_github_libbacktrace") +load("@rules_hdl//dependency_support/com_github_mithro_vlsiffra_hdl_library:com_github_mithro_vlsiffra_hdl_library.bzl", "com_github_mithro_vlsiffra_hdl_library") load("@rules_hdl//dependency_support/com_github_ninja_build_ninja:com_github_ninja_build_ninja.bzl", "com_github_ninja_build_ninja") load("@rules_hdl//dependency_support/com_github_quantamhd_lemon:com_github_quantamhd_lemon.bzl", "com_github_quantamhd_lemon") load("@rules_hdl//dependency_support/com_github_westes_flex:com_github_westes_flex.bzl", "com_github_westes_flex") @@ -75,6 +76,7 @@ def dependency_support(): com_github_fmtlib_fmt() com_github_gabime_spdlog() com_github_libbacktrace() + com_github_mithro_vlsiffra_hdl_library() com_github_ninja_build_ninja() com_github_quantamhd_lemon() com_github_westes_flex() diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl index 35488f13..1cebd77f 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl @@ -1,6 +1,6 @@ """ASAP7 PDK rules.""" -load("@rules_hdl//pdk:build_defs.bzl", "CornerInfo", "StandardCellInfo") +load("@rules_hdl//pdk:build_defs.bzl", "ADDER_TYPES", "CornerInfo", "StandardCellInfo") load("@rules_hdl//pdk:open_road_configuration.bzl", "OpenRoadPdkInfo") def asap7_srams_files(name = None, rev = None, tracks = None, has_gds = True): @@ -149,55 +149,41 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds ) # CCS delay model - asap7_cell_library( - name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args), + asap7_cell_library_common = dict( srcs = [ ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), ], cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), - platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), - default_corner_delay_model = "ccs", - default_corner_swing = "SS", - openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), - tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), - visibility = [ - "//visibility:public", - ], - ) - asap7_cell_library( - name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_tt".format(**args), - srcs = [ - ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), - #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), - ], - cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), - platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), default_corner_delay_model = "ccs", - default_corner_swing = "TT", - openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), - tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), - visibility = [ - "//visibility:public", - ], - ) - asap7_cell_library( - name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ff".format(**args), - srcs = [ - ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), - #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), - ], - cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), - default_corner_delay_model = "ccs", - default_corner_swing = "FF", - openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), visibility = [ "//visibility:public", ], ) + for add in ADDER_TYPES: + args["add"] = add + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss-{add}".format(**args), + default_corner_swing = "SS", + openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}-{add}".format(**args), + **asap7_cell_library_common + ) + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_tt-{add}".format(**args), + default_corner_swing = "TT", + openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}-{add}".format(**args), + **asap7_cell_library_common + ) + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ff-{add}".format(**args), + default_corner_swing = "FF", + openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}-{add}".format(**args), + **asap7_cell_library_common + ) + def _asap7_cell_library_impl(ctx): liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"] liberty_files = [file for file in liberty_files if "_{}_".format(ctx.attr.default_corner_delay_model) in file.basename] diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py index fef44181..c3ddc210 100755 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/build-BUILD.py @@ -56,7 +56,8 @@ the 7.5 track library using RVT transistors and slow corner. """ -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") +load("@rules_hdl//pdk:build_defs.bzl", "ADDER_MAPPINGS") +load("@rules_hdl//pdk:open_road_configuration.bzl", "make_open_road_pdk_configuration", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl index 250d84fd..2a428bba 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/cells_info.bzl @@ -40,7 +40,7 @@ ASAP7_OPTIONS = StandardCellOptionsInfo( ], ) -def for_each_asap7_cells(libname, include_vts = None, include_corners = None, include_volts = None, include_temps = None): +def for_each_asap7_cells(libname, include_vts = None, include_corners = None, include_volts = None, include_temps = None, include_adders = None): """Generate a list of each standard cell library name. Args: @@ -49,6 +49,7 @@ def for_each_asap7_cells(libname, include_vts = None, include_corners = None, in include_corners: 'all' or list of corners ('ff', 'tt', 'ss') to include in the output. include_volts: 'all' or list of voltages (in '0p55v' form) to include in the output. include_temps: 'all' or list of temperatures (in 'm40c' or '125c' form) to include in the output. + include_adders: 'all' or list of adder styles to include in the output. Returns: A list of tuples containing a unique name for the cell library @@ -81,6 +82,7 @@ def for_each_asap7_cells(libname, include_vts = None, include_corners = None, in "include_corners": include_corners, "include_volts": include_volts, "include_temps": include_temps, + "include_adders": include_adders, } check_for_each_cells_args(kwargs, ASAP7_OPTIONS) @@ -106,6 +108,9 @@ def for_each_asap7_cells(libname, include_vts = None, include_corners = None, in libname_short = libname.replace("rev", "") # "@org_theopenroadproject_asap7sc7p5t_27//:asap7-sc7p5t_rev27_rvt-ccs_ss - cell_target = "@org_theopenroadproject_asap7{}//:{}".format(libname_short, cell_name) - output.append((cell_name, cell_target)) + for add in kwargs["include_adders"]: + if add: + add = "-" + add + cell_target = "@org_theopenroadproject_asap7{}//:{}{}".format(libname_short, cell_name, add) + output.append((cell_name + add, cell_target)) return output diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel index 326b291f..844162ab 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel @@ -40,11 +40,27 @@ By default if not otherwise explicitly specified the default selection will be the 7.5 track library using RVT transistors and slow corner. """ -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") +load("@rules_hdl//pdk:build_defs.bzl", "ADDER_MAPPINGS") +load("@rules_hdl//pdk:open_road_configuration.bzl", "make_open_road_pdk_configuration", "open_road_pdk_configuration") +load("@rules_license//rules:license.bzl", "license") +# Arizona State Predictive PDK and Cell Library +package( + default_applicable_licenses = ["@org_theopenroadproject_asap7sc6t_26//:license"], + default_visibility = ["//visibility:public"], +) + +license( + name = "license", + package_name = "asap7sc6t_26", +) + +licenses(["notice"]) + +exports_files(["LICENSE"]) # From org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl """ ASAP7 "rev 26" 6 track standard cell library using low VT transistors """ @@ -57,8 +73,7 @@ asap7_cells_files( vt = "lvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_lvt", +_sc6t_rev26_lvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc6t", cts_buffer_cell = "BUFx4_ASAP7_6t_L", do_not_use_cell_list = [ @@ -100,10 +115,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOxp5_ASAP7_6t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt-nofa", + common = _sc6t_rev26_lvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt-fa", + common = _sc6t_rev26_lvt_open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc6t_rev26_lvt-" + add, + actual = ":open_road-asap7-sc6t_rev26_lvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc6t_rev26_lvt-opt", + actual = ":open_road-asap7-sc6t_rev26_lvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl """ ASAP7 "rev 26" 6 track standard cell library using regular VT transistors """ @@ -115,7 +159,7 @@ asap7_cells_files( vt = "rvt", ) -open_road_pdk_configuration( +_sc6t_rev26_rvt_open_road_pdk_configuration_common = dict( name = "open_road-asap7-sc6t_rev26_rvt", cell_site = "asap7sc6t", cts_buffer_cell = "BUFx4_ASAP7_6t_R", @@ -158,10 +202,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOxp5_ASAP7_6t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt-nofa", + common = _sc6t_rev26_rvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt-fa", + common = _sc6t_rev26_rvt_open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc6t_rev26_rvt-" + add, + actual = ":open_road-asap7-sc6t_rev26_rvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc6t_rev26_rvt-opt", + actual = ":open_road-asap7-sc6t_rev26_rvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl """ ASAP7 "rev 26" 6 track standard cell library using super-low VT transistors """ @@ -173,7 +246,7 @@ asap7_cells_files( vt = "slvt", ) -open_road_pdk_configuration( +_sc6t_rev26_slvt_open_road_pdk_configuration_common = dict( name = "open_road-asap7-sc6t_rev26_slvt", cell_site = "asap7sc6t", cts_buffer_cell = "BUFx4_ASAP7_6t_SL", @@ -216,10 +289,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOxp5_ASAP7_6t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt-nofa", + common = _sc6t_rev26_slvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt-fa", + common = _sc6t_rev26_slvt_open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc6t_rev26_slvt-" + add, + actual = ":open_road-asap7-sc6t_rev26_slvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc6t_rev26_slvt-opt", + actual = ":open_road-asap7-sc6t_rev26_slvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc6t_26/common.bzl ########################################################################## """ ASAP7 "rev 26" 6 track standard cell library with SRAM blocks. """ diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl index 48f55955..b34c765a 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-lvt.bzl @@ -22,8 +22,7 @@ asap7_cells_files( vt = "lvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_lvt", +_sc6t_rev26_lvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc6t", cts_buffer_cell = "BUFx4_ASAP7_6t_L", do_not_use_cell_list = [ @@ -65,6 +64,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOxp5_ASAP7_6t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt-nofa", + common = _sc6t_rev26_lvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_lvt-fa", + common = _sc6t_rev26_lvt_open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc6t_rev26_lvt-" + add, + actual = ":open_road-asap7-sc6t_rev26_lvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc6t_rev26_lvt-opt", + actual = ":open_road-asap7-sc6t_rev26_lvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl index fafb59ae..4356ba0d 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-rvt.bzl @@ -22,8 +22,7 @@ asap7_cells_files( vt = "rvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_rvt", +_sc6t_rev26_rvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc6t", cts_buffer_cell = "BUFx4_ASAP7_6t_R", do_not_use_cell_list = [ @@ -65,6 +64,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOxp5_ASAP7_6t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt-nofa", + common = _sc6t_rev26_rvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_rvt-fa", + common = _sc6t_rev26_rvt_open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc6t_rev26_rvt-" + add, + actual = ":open_road-asap7-sc6t_rev26_rvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc6t_rev26_rvt-opt", + actual = ":open_road-asap7-sc6t_rev26_rvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl index 130cbb9d..e8c40c52 100644 --- a/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc6t_26/cells-slvt.bzl @@ -22,8 +22,7 @@ asap7_cells_files( vt = "slvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc6t_rev26_slvt", +_sc6t_rev26_slvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc6t", cts_buffer_cell = "BUFx4_ASAP7_6t_SL", do_not_use_cell_list = [ @@ -65,6 +64,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOxp5_ASAP7_6t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", ) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt-nofa", + common = _sc6t_rev26_slvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc6t_rev26_slvt-fa", + common = _sc6t_rev26_slvt_open_road_pdk_configuration_common, + ha_fa_mapping = "cell_adders.v", +) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc6t_rev26_slvt-" + add, + actual = ":open_road-asap7-sc6t_rev26_slvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc6t_rev26_slvt-opt", + actual = ":open_road-asap7-sc6t_rev26_slvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel index bd563c50..caeb003c 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel @@ -40,11 +40,27 @@ By default if not otherwise explicitly specified the default selection will be the 7.5 track library using RVT transistors and slow corner. """ -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") +load("@rules_hdl//pdk:build_defs.bzl", "ADDER_MAPPINGS") +load("@rules_hdl//pdk:open_road_configuration.bzl", "make_open_road_pdk_configuration", "open_road_pdk_configuration") +load("@rules_license//rules:license.bzl", "license") + +# Arizona State Predictive PDK and Cell Library +package( + default_applicable_licenses = ["@org_theopenroadproject_asap7sc7p5t_27//:license"], + default_visibility = ["//visibility:public"], +) + +license( + name = "license", + package_name = "asap7sc7p5t_27", +) +licenses(["notice"]) + +exports_files(["LICENSE"]) # From org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl """ ASAP7 "rev 27" 7.5 track standard cell library using Low VT transistors """ @@ -52,14 +68,13 @@ load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7 # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_lvt", + has_gds = False, rev = "27", tracks = "7p5t", vt = "lvt", - has_gds = False, ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_lvt", +_sc7p5t_rev27_lvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_L", do_not_use_cell_list = [ @@ -101,25 +116,52 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt-nofa", + common = _sc7p5t_rev27_lvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt-fa", + common = _sc7p5t_rev27_lvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev27_lvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev27_lvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev27_lvt-opt", + actual = ":open_road-asap7-sc7p5t_rev27_lvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl """ ASAP7 "rev 27" 7.5 track standard cell library using regular VT transistors """ # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_rvt", + has_gds = True, rev = "27", tracks = "7p5t", vt = "rvt", - has_gds = True, ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_rvt", +_sc7p5t_rev27_rvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ @@ -161,11 +203,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt-nofa", + common = _sc7p5t_rev27_rvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt-fa", + common = _sc7p5t_rev27_rvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev27_rvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev27_rvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev27_rvt-opt", + actual = ":open_road-asap7-sc7p5t_rev27_rvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl ########################################################################## """ @@ -276,6 +346,7 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_4x.pdn", pin_horizontal_metal_layer = "M4", @@ -289,7 +360,6 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", - ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) ########################################################################## @@ -301,14 +371,13 @@ open_road_pdk_configuration( # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_slvt", + has_gds = False, rev = "27", tracks = "7p5t", vt = "slvt", - has_gds = False, ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_slvt", +_sc7p5t_rev27_slvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_SL", do_not_use_cell_list = [ @@ -350,11 +419,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt-nofa", + common = _sc7p5t_rev27_slvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt-fa", + common = _sc7p5t_rev27_slvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev27_slvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev27_slvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev27_slvt-opt", + actual = ":open_road-asap7-sc7p5t_rev27_slvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc7p5t_27/common.bzl ########################################################################## """ ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. """ diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl index 918405a9..7f4ad1b6 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-lvt.bzl @@ -17,14 +17,13 @@ # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_lvt", + has_gds = False, rev = "27", tracks = "7p5t", vt = "lvt", - has_gds = False, ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_lvt", +_sc7p5t_rev27_lvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_L", do_not_use_cell_list = [ @@ -66,7 +65,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt-nofa", + common = _sc7p5t_rev27_lvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_lvt-fa", + common = _sc7p5t_rev27_lvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev27_lvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev27_lvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev27_lvt-opt", + actual = ":open_road-asap7-sc7p5t_rev27_lvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl index 46260807..41950214 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt.bzl @@ -17,14 +17,13 @@ # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_rvt", + has_gds = True, rev = "27", tracks = "7p5t", vt = "rvt", - has_gds = True, ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_rvt", +_sc7p5t_rev27_rvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ @@ -66,7 +65,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt-nofa", + common = _sc7p5t_rev27_rvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_rvt-fa", + common = _sc7p5t_rev27_rvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev27_rvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev27_rvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev27_rvt-opt", + actual = ":open_road-asap7-sc7p5t_rev27_rvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl index b98c2ff5..6cf36e75 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl @@ -121,6 +121,7 @@ open_road_pdk_configuration( "M7": "0.5", }, global_routing_signal_layers = "M2-M7", + ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", klayout_tech_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.lyt", pdn_config = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:pdn_config_4x.pdn", pin_horizontal_metal_layer = "M4", @@ -134,7 +135,6 @@ open_road_pdk_configuration( tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_4x.tcl", wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", - ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) ########################################################################## diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl index c59d5cde..c5acb90f 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-slvt.bzl @@ -17,14 +17,13 @@ # ------------------------------------------------------------------------ asap7_cells_files( name = "asap7-cells-sc7p5t_rev27_slvt", + has_gds = False, rev = "27", tracks = "7p5t", vt = "slvt", - has_gds = False, ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev27_slvt", +_sc7p5t_rev27_slvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_SL", do_not_use_cell_list = [ @@ -66,7 +65,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt-nofa", + common = _sc7p5t_rev27_slvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev27_slvt-fa", + common = _sc7p5t_rev27_slvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev27_slvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev27_slvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev27_slvt-opt", + actual = ":open_road-asap7-sc7p5t_rev27_slvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel index 76c81829..de1a0e43 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel @@ -40,11 +40,27 @@ By default if not otherwise explicitly specified the default selection will be the 7.5 track library using RVT transistors and slow corner. """ -load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cell_library") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_cells_files") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:asap7.bzl", "asap7_srams_files") +load("@rules_hdl//pdk:build_defs.bzl", "ADDER_MAPPINGS") +load("@rules_hdl//pdk:open_road_configuration.bzl", "make_open_road_pdk_configuration", "open_road_pdk_configuration") +load("@rules_license//rules:license.bzl", "license") +# Arizona State Predictive PDK and Cell Library +package( + default_applicable_licenses = ["@org_theopenroadproject_asap7sc7p5t_28//:license"], + default_visibility = ["//visibility:public"], +) + +license( + name = "license", + package_name = "asap7sc7p5t_28", +) + +licenses(["notice"]) + +exports_files(["LICENSE"]) # From org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl """ ASAP7 "rev 28" 7.5 track standard cell library using Low VT transistors """ @@ -57,8 +73,7 @@ asap7_cells_files( vt = "lvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_lvt", +_sc7p5t_rev28_lvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_L", do_not_use_cell_list = [ @@ -100,11 +115,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_lvt-nofa", + common = _sc7p5t_rev28_lvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_lvt-fa", + common = _sc7p5t_rev28_lvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev28_lvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev28_lvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev28_lvt-opt", + actual = ":open_road-asap7-sc7p5t_rev28_lvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl """ ASAP7 "rev 28" 7.5 track standard cell library using regular VT transistors """ @@ -116,8 +159,7 @@ asap7_cells_files( vt = "rvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_rvt", +_sc7p5t_rev28_rvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ @@ -159,11 +201,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_rvt-nofa", + common = _sc7p5t_rev28_rvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_rvt-fa", + common = _sc7p5t_rev28_rvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev28_rvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev28_rvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev28_rvt-opt", + actual = ":open_road-asap7-sc7p5t_rev28_rvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl """ ASAP7 "rev 28" 7.5 track standard cell library using Super-Low VT transistors """ @@ -175,8 +245,7 @@ asap7_cells_files( vt = "slvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_slvt", +_sc7p5t_rev28_slvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_SL", do_not_use_cell_list = [ @@ -218,11 +287,39 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt-nofa", + common = _sc7p5t_rev28_slvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt-fa", + common = _sc7p5t_rev28_slvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev28_slvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev28_slvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev28_slvt-opt", + actual = ":open_road-asap7-sc7p5t_rev28_slvt-fa", + visibility = ["//visibility:public"], +) + # From org_theopenroadproject_asap7sc7p5t_28/common.bzl ########################################################################## """ ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. """ diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl index b97bc556..31c29dd2 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-lvt.bzl @@ -22,8 +22,7 @@ asap7_cells_files( vt = "lvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_lvt", +_sc7p5t_rev28_lvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_L", do_not_use_cell_list = [ @@ -65,7 +64,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_L/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_lvt-nofa", + common = _sc7p5t_rev28_lvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_lvt-fa", + common = _sc7p5t_rev28_lvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_L.v", ) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev28_lvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev28_lvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev28_lvt-opt", + actual = ":open_road-asap7-sc7p5t_rev28_lvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl index ec10602a..ac590671 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-rvt.bzl @@ -22,8 +22,7 @@ asap7_cells_files( vt = "rvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_rvt", +_sc7p5t_rev28_rvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_R", do_not_use_cell_list = [ @@ -65,7 +64,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_R/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_rvt-nofa", + common = _sc7p5t_rev28_rvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_rvt-fa", + common = _sc7p5t_rev28_rvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_R.v", ) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev28_rvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev28_rvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev28_rvt-opt", + actual = ":open_road-asap7-sc7p5t_rev28_rvt-fa", + visibility = ["//visibility:public"], +) diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl index 8b5a042a..289d66e2 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/cells-slvt.bzl @@ -22,8 +22,7 @@ asap7_cells_files( vt = "slvt", ) -open_road_pdk_configuration( - name = "open_road-asap7-sc7p5t_rev28_slvt", +_sc7p5t_rev28_slvt_open_road_pdk_configuration_common = dict( cell_site = "asap7sc7p5t", cts_buffer_cell = "BUFx4_ASAP7_75t_SL", do_not_use_cell_list = [ @@ -65,7 +64,35 @@ open_road_pdk_configuration( tie_low_port = "TIELOx1_ASAP7_75t_SL/L", tie_separation = 0, tracks_file = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:tracks_1x.tcl", + visibility = ["//visibility:public"], wire_rc_clock_metal_layer = "M5", wire_rc_signal_metal_layer = "M2", +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt-nofa", + common = _sc7p5t_rev28_slvt_open_road_pdk_configuration_common, +) + +make_open_road_pdk_configuration( + name = "open_road-asap7-sc7p5t_rev28_slvt-fa", + common = _sc7p5t_rev28_slvt_open_road_pdk_configuration_common, ha_fa_mapping = "@rules_hdl//dependency_support/org_theopenroadproject_asap7_pdk_r1p7:cell_adders_SL.v", ) + +# FIXME: Add in the adder mappers +[ + alias( + name = "open_road-asap7-sc7p5t_rev28_slvt-" + add, + actual = ":open_road-asap7-sc7p5t_rev28_slvt-fa", + visibility = ["//visibility:public"], + ) + for add in ADDER_MAPPINGS +] + +# Map the "optimal" configuration to the full adder +alias( + name = "open_road-asap7-sc7p5t_rev28_slvt-opt", + actual = ":open_road-asap7-sc7p5t_rev28_slvt-fa", + visibility = ["//visibility:public"], +) diff --git a/pdk/build_defs.bzl b/pdk/build_defs.bzl index 3a6fcbf4..45c42943 100644 --- a/pdk/build_defs.bzl +++ b/pdk/build_defs.bzl @@ -38,7 +38,64 @@ CornerInfo = provider( }, ) -StandardCellOptionsInfo = provider( +ADDER_TYPES = { + "opt": "Default configuration, should be 'optimal'.", + "fa": "Enable Full Adder and Half Adder cell mapping.", + "nofa": "Disable Full Adder and Half Adder cell mapping.", + "ripple": "Ripple carry Adder -- Extremely slowest but very area efficient.", + "brentkung": "Brent Kung Adder -- .", + "hancarlson": "Han Carlson Adder -- .", + "koggestone": "Kogge Stone Adder -- .", +} + +ADDER_MAPPINGS = [ + "ripple", + "brentkung", + "hancarlson", + "koggestone", +] + +def _init_standard_cell_options_info(*, libraries, vts, corners, volts, temps, adders = tuple(ADDER_TYPES.keys())): + normalized_libraries = {} + for lib in libraries: + normalized_libraries[lib.lower()] = None + + if not normalized_libraries: + fail("No library names provided.") + + normalized_vts = {} + for vt in vts: + normalized_vts[vt.lower()] = None + + normalized_corners = {} + for corner in corners: + normalized_corners[corner.lower()] = None + + normalized_volts = {} + for volt in volts: + normalized_volts[voltage_normalize(volt)] = None + + normalized_temps = {} + for temp in temps: + normalized_temps[temp_normalize(temp)] = None + + for add in adders: + invalid = [] + if add not in ADDER_TYPES: + invalid.append(add) + if invalid: + fail("Invalid adder mapping option provided: {} (valid: {})".format(", ".join(invalid), ADDER_TYPES.keys())) + + return { + "libraries": list(sorted(normalized_libraries.keys())), + "vts": list(sorted(normalized_vts.keys())), + "corners": list(sorted(normalized_corners.keys())), + "volts": list(sorted(normalized_volts.keys())), + "temps": list(sorted(normalized_temps.keys())), + "adders": list(sorted(adders)), + } + +StandardCellOptionsInfo, _new_standard_cell_options_info = provider( "Provides information about what standard cell options are available", fields = { "libraries": "A list of available standard cell library names.", @@ -46,7 +103,9 @@ StandardCellOptionsInfo = provider( "corners": "A list of valid corners names.", "volts": "A list of (normalize) voltage levels names used in timing characterization.", "temps": "A list of (normalize) temperature values names used in timing characterization.", + "adders": "A list of adder types and styles supported.", }, + init = _init_standard_cell_options_info, ) def temp_format(i): @@ -275,7 +334,7 @@ def check_for_each_cells_args(kwargs, options): # fail("options should be a `StandardCellOptionsInfo` object.") if kwargs["libname"] not in options.libraries: - fail("Invalid library name: " + kwargs["libname"]) + fail("Invalid library name: {} (valid: {})".format(kwargs["libname"], options.libraries)) # Validate the provided voltage threadholds if kwargs["include_vts"] in ("all", None): @@ -283,7 +342,7 @@ def check_for_each_cells_args(kwargs, options): for vt in kwargs["include_vts"]: if vt not in options.vts: - fail("Invalid vt: {} (from {})".format(vt, kwargs["include_vts"])) + fail("Invalid vt value in `include_vts`: {} (from {})".format(vt, kwargs["include_vts"])) # Valid the provided corners if kwargs["include_corners"] in ("all", None): @@ -291,7 +350,7 @@ def check_for_each_cells_args(kwargs, options): for corner in kwargs["include_corners"]: if corner not in options.corners: - fail("Invalid corner: {} (from {})".format(corner, kwargs["include_corners"])) + fail("Invalid corner value in `include_corners`: {} (from {})".format(corner, kwargs["include_corners"])) # Validate and normalize the provided volts values if kwargs["include_volts"] in ("all", None): @@ -302,7 +361,7 @@ def check_for_each_cells_args(kwargs, options): for voltage in kwargs["include_volts"]: if voltage not in options.volts: - fail("Invalid volts: {} (from {})".format(voltage, kwargs["include_volts"])) + fail("Invalid volts value in `include_volts`: {} (from {})".format(voltage, kwargs["include_volts"])) # Validate and normalize the provided temperature values if kwargs["include_temps"] in ("all", None): @@ -313,4 +372,12 @@ def check_for_each_cells_args(kwargs, options): for temp in kwargs["include_temps"]: if temp not in options.temps: - fail("Invalid temp: {} (from {})".format(temp, kwargs["include_temps"])) + fail("Invalid temp value in `include_temps`: {} (from {})".format(temp, kwargs["include_temps"])) + + # Validate the adder mapping requested + if kwargs["include_adders"] in ("all", None): + kwargs["include_adders"] = list(options.adders) + + for add in kwargs["include_adders"]: + if add not in options.adders: + fail("Invalid adder mapping value in `include_adders`: {} (from {})".format(temp, kwargs["include_adders"])) diff --git a/pdk/open_road_configuration.bzl b/pdk/open_road_configuration.bzl index 29ceb232..d0130581 100644 --- a/pdk/open_road_configuration.bzl +++ b/pdk/open_road_configuration.bzl @@ -87,6 +87,11 @@ def _open_road_pdk_configuration_impl(ctx): ), ] +def make_open_road_pdk_configuration(common = {}, **kwargs): + for k, v in kwargs.items(): + common[k] = v + return open_road_pdk_configuration(**common) + open_road_pdk_configuration = rule( implementation = _open_road_pdk_configuration_impl, attrs = { diff --git a/place_and_route/build_defs.bzl b/place_and_route/build_defs.bzl index b749e194..1f7936cd 100644 --- a/place_and_route/build_defs.bzl +++ b/place_and_route/build_defs.bzl @@ -95,6 +95,7 @@ place_and_route = rule( ), "sdc": attr.label(allow_single_file = True), "pin_placement_script": attr.label(allow_single_file = [".tcl"], doc = "See https://openroad.readthedocs.io/en/latest/main/src/ppl/README.html for syntax"), + "manual_placement_script": attr.label(allow_single_file = [".tcl"], doc = "TCL script which performs placement of certain cells."), "clocks": attr.string_dict(), "die_width_microns": attr.int(), "die_height_microns": attr.int(), diff --git a/place_and_route/private/global_placement.bzl b/place_and_route/private/global_placement.bzl index 9ffa6a54..6006e9d8 100644 --- a/place_and_route/private/global_placement.bzl +++ b/place_and_route/private/global_placement.bzl @@ -30,17 +30,29 @@ def global_placement(ctx, open_road_info): """ open_road_configuration = get_open_road_configuration(ctx.attr.synthesized_rtl[SynthesisInfo]) - timing_setup_command_struct = timing_setup_commands(ctx) + open_road_commands = [] + + # Timing setup + timing_setup_command_struct = timing_setup_commands(ctx) inputs = timing_setup_command_struct.inputs + open_road_commands += timing_setup_command_struct.commands - open_road_commands = timing_setup_command_struct.commands + [ + # Global placement + open_road_commands.append( "global_placement -timing_driven -routability_driven -density {density} -pad_left {pad_left} -pad_right {pad_right}".format( density = ctx.attr.placement_density, #TODO(bazel): When bazel 4.0.0 is avaliable use float command pad_left = open_road_configuration.global_placement_cell_pad, pad_right = open_road_configuration.global_placement_cell_pad, ), - ] + ) + + # Manual placement + if ctx.file.manual_placement_script: + inputs.append(ctx.file.manual_placement_script) + open_road_commands.append( + "source {}".format(ctx.file.manual_placement_script.path), + ) command_output = openroad_command( ctx, diff --git a/place_and_route/private/place_pins.bzl b/place_and_route/private/place_pins.bzl index a20bcc81..df158412 100644 --- a/place_and_route/private/place_pins.bzl +++ b/place_and_route/private/place_pins.bzl @@ -29,35 +29,45 @@ def place_pins(ctx, open_road_info): open_road_info: OpenRoadInfo provider from a previous step. """ - open_road_configuration = get_open_road_configuration(ctx.attr.synthesized_rtl[SynthesisInfo]) - timing_setup_command_struct = timing_setup_commands(ctx) - inputs = timing_setup_command_struct.inputs - tapcell_command = "tapcell -distance {tapcell_distance} -tapcell_master {tapcell}".format( - tapcell = open_road_configuration.tap_cell, - tapcell_distance = open_road_configuration.tapcell_distance, - endcap = open_road_configuration.endcap_cell, - ) + open_road_commands = [] - if open_road_configuration.tapcell_tcl: - inputs = inputs + [ - open_road_configuration.tapcell_tcl, - ] - tapcell_command = "source {}".format(open_road_configuration.tapcell_tcl.path) + # Timing setup + timing_setup_command_struct = timing_setup_commands(ctx) + inputs = timing_setup_command_struct.inputs + open_road_commands += timing_setup_command_struct.commands - if ctx.file.pin_placement_script: - inputs.append(ctx.file.pin_placement_script) + # Pin placement + if ctx.file.pin_placement_script: + inputs.append(ctx.file.pin_placement_script) + open_road_commands.append( + "source {}".format(ctx.file.pin_placement_script.path), + ) - open_road_commands = timing_setup_command_struct.commands + [ - "source {}".format(ctx.file.pin_placement_script.path) if ctx.file.pin_placement_script else "", + # FIXME: Should this be else the pin_placement_script? + open_road_commands.append( "place_pins -hor_layers {hor_layers} -ver_layers {ver_layers} {min_pin_distance}".format( hor_layers = open_road_configuration.pin_horizontal_metal_layer, ver_layers = open_road_configuration.pin_vertical_metal_layer, min_pin_distance = "-min_distance {}".format(ctx.attr.min_pin_distance) if ctx.attr.min_pin_distance else "", ), - tapcell_command, - ] + ) + + # Tap cell configuration + if open_road_configuration.tapcell_tcl: + inputs.append(open_road_configuration.tapcell_tcl) + open_road_commands.append( + "source {}".format(open_road_configuration.tapcell_tcl.path), + ) + else: + open_road_commands.append( + "tapcell -distance {tapcell_distance} -tapcell_master {tapcell}".format( + tapcell = open_road_configuration.tap_cell, + tapcell_distance = open_road_configuration.tapcell_distance, + endcap = open_road_configuration.endcap_cell, + ), + ) command_output = openroad_command( ctx, diff --git a/synthesis/BUILD b/synthesis/BUILD index 36aae206..888f0e1f 100644 --- a/synthesis/BUILD +++ b/synthesis/BUILD @@ -22,6 +22,7 @@ package( ) exports_files(["synth.tcl"]) + exports_files(["abc.script"]) pkg_tar( diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index 84a632d7..77d2d9bb 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -275,7 +275,7 @@ synthesize_rtl = rule( ), "adder_mapping": attr.label( allow_single_file = True, - doc = "Verilog file that maps yosys adder to PDK adders." + doc = "Verilog file that maps yosys adder to PDK adders.", ), "target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"), "output_file_name": attr.string(doc = "The output file name."), diff --git a/tests/BUILD b/tests/BUILD index bfe56e85..dd33e288 100644 --- a/tests/BUILD +++ b/tests/BUILD @@ -74,6 +74,9 @@ place_and_route( core_padding_microns = 20, die_height_microns = 200, die_width_microns = 200, + exec_properties = dict( + mem = "16g", + ), placement_density = "0.7", synthesized_rtl = ":verilog_adder-synth", ) @@ -84,6 +87,9 @@ place_and_route( core_padding_microns = 20, die_height_microns = 200, die_width_microns = 200, + exec_properties = dict( + mem = "16g", + ), placement_density = "0.7", sdc = "constraint.sdc", synthesized_rtl = ":verilog_counter-synth", @@ -120,12 +126,18 @@ place_and_route( EXTRA_ARGS = { "verilog_counter": { "place_and_route": dict( + exec_properties = dict( + mem = "16g", + ), sdc = "constraint.sdc", ), }, "verilog_adder": { "place_and_route": dict( clock_period = None, # Combinational only design + exec_properties = dict( + mem = "16g", + ), ), }, }