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Tim 'mithro' Ansell
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Merge pull request #236 from mithro/asap7-multi-corner
Add multiple corners.
2 parents 313819d + 12dea9a commit aca8d0a

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10 files changed

+168
-57
lines changed

10 files changed

+168
-57
lines changed

‎dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl

Lines changed: 43 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -139,8 +139,18 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds
139139

140140
# Library configuration
141141
# ------------------------------------------------------------------------
142-
asap7_cell_library(
142+
# Default library is slow-slow corner using CCS
143+
native.alias(
143144
name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
145+
actual = ":asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args),
146+
visibility = [
147+
"//visibility:public",
148+
],
149+
)
150+
151+
# CCS delay model
152+
asap7_cell_library(
153+
name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args),
144154
srcs = [
145155
":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
146156
#":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
@@ -155,6 +165,38 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds
155165
"//visibility:public",
156166
],
157167
)
168+
asap7_cell_library(
169+
name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_tt".format(**args),
170+
srcs = [
171+
":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
172+
#":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
173+
],
174+
cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
175+
platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
176+
default_corner_delay_model = "ccs",
177+
default_corner_swing = "TT",
178+
openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
179+
tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
180+
visibility = [
181+
"//visibility:public",
182+
],
183+
)
184+
asap7_cell_library(
185+
name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ff".format(**args),
186+
srcs = [
187+
":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
188+
#":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
189+
],
190+
cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
191+
platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
192+
default_corner_delay_model = "ccs",
193+
default_corner_swing = "FF",
194+
openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
195+
tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
196+
visibility = [
197+
"//visibility:public",
198+
],
199+
)
158200

159201
def _asap7_cell_library_impl(ctx):
160202
liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"]

‎dependency_support/org_theopenroadproject_asap7sc6t_26/bundled.BUILD.bazel

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -245,3 +245,11 @@ filegroup(
245245
name = "asap7-misc-sc6t_rev26_4x-lef",
246246
srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"],
247247
)
248+
249+
# Default rev26 cell library is the RVT library using slow-slow corner with CCS
250+
# modeling.
251+
alias(
252+
name = "asap7-sc6t_rev26",
253+
actual = ":asap7-sc6t_rev26_rvt-ccs_ss",
254+
visibility = ["//visibility:public"],
255+
)

‎dependency_support/org_theopenroadproject_asap7sc6t_26/common.bzl

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,3 +36,11 @@ filegroup(
3636
name = "asap7-misc-sc6t_rev26_4x-lef",
3737
srcs = ["techlef_misc/asap7sc6t_tech_4x_210831.lef"],
3838
)
39+
40+
# Default rev26 cell library is the RVT library using slow-slow corner with CCS
41+
# modeling.
42+
alias(
43+
name = "asap7-sc6t_rev26",
44+
actual = ":asap7-sc6t_rev26_rvt-ccs_ss",
45+
visibility = ["//visibility:public"],
46+
)

‎dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -215,7 +215,7 @@ filegroup(
215215
# Library configuration
216216
# ------------------------------------------------------------------------
217217
asap7_cell_library(
218-
name = "asap7-sc7p5t_rev27_rvt_4x",
218+
name = "asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
219219
srcs = [
220220
":asap7-cells-sc7p5t_rev27_rvt_4x-lib7z",
221221
# ":asap7-srams-sc7p5t_rev27_4x-lib7z",
@@ -231,6 +231,14 @@ asap7_cell_library(
231231
],
232232
)
233233

234+
alias(
235+
name = "asap7-sc7p5t_rev27_rvt_4x",
236+
actual = ":asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
237+
visibility = [
238+
"//visibility:public",
239+
],
240+
)
241+
234242
# OpenROAD configuration
235243
# ------------------------------------------------------------------------
236244
open_road_pdk_configuration(
@@ -368,3 +376,11 @@ filegroup(
368376
name = "asap7-misc-sc7p5t_rev27_4x-lef",
369377
srcs = ["techlef_misc/asap7_tech_4x_201209.lef"],
370378
)
379+
380+
# Default rev27 cell library is the RVT library using slow-slow corner with CCS
381+
# modeling.
382+
alias(
383+
name = "asap7-sc7p5t_rev27",
384+
actual = ":asap7-sc7p5t_rev27_rvt-ccs_ss",
385+
visibility = ["//visibility:public"],
386+
)

‎dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ filegroup(
6262
# Library configuration
6363
# ------------------------------------------------------------------------
6464
asap7_cell_library(
65-
name = "asap7-sc7p5t_rev27_rvt_4x",
65+
name = "asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
6666
srcs = [
6767
":asap7-cells-sc7p5t_rev27_rvt_4x-lib7z",
6868
# ":asap7-srams-sc7p5t_rev27_4x-lib7z",
@@ -78,6 +78,14 @@ asap7_cell_library(
7878
],
7979
)
8080

81+
alias(
82+
name = "asap7-sc7p5t_rev27_rvt_4x",
83+
actual = ":asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
84+
visibility = [
85+
"//visibility:public",
86+
],
87+
)
88+
8189
# OpenROAD configuration
8290
# ------------------------------------------------------------------------
8391
open_road_pdk_configuration(

‎dependency_support/org_theopenroadproject_asap7sc7p5t_27/common.bzl

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,3 +36,11 @@ filegroup(
3636
name = "asap7-misc-sc7p5t_rev27_4x-lef",
3737
srcs = ["techlef_misc/asap7_tech_4x_201209.lef"],
3838
)
39+
40+
# Default rev27 cell library is the RVT library using slow-slow corner with CCS
41+
# modeling.
42+
alias(
43+
name = "asap7-sc7p5t_rev27",
44+
actual = ":asap7-sc7p5t_rev27_rvt-ccs_ss",
45+
visibility = ["//visibility:public"],
46+
)

‎dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -241,3 +241,11 @@ filegroup(
241241
name = "asap7-misc-sc7p5t_rev28_4x-lef",
242242
srcs = ["techlef_misc/asap7_tech_4x_201209.lef"],
243243
)
244+
245+
# Default rev28 cell library is the RVT library using slow-slow corner with CCS
246+
# modeling.
247+
alias(
248+
name = "asap7-sc7p5t_rev28",
249+
actual = ":asap7-sc7p5t_rev28_rvt-ccs_ss",
250+
visibility = ["//visibility:public"],
251+
)

‎dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,11 @@ filegroup(
3232
name = "asap7-misc-sc7p5t_rev28_4x-lef",
3333
srcs = ["techlef_misc/asap7_tech_4x_201209.lef"],
3434
)
35+
36+
# Default rev28 cell library is the RVT library using slow-slow corner with CCS
37+
# modeling.
38+
alias(
39+
name = "asap7-sc7p5t_rev28",
40+
actual = ":asap7-sc7p5t_rev28_rvt-ccs_ss",
41+
visibility = ["//visibility:public"],
42+
)

‎flows/asap7.bzl

Lines changed: 58 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ load("//place_and_route:build_defs.bzl", "place_and_route")
2020
load("//static_timing:build_defs.bzl", "run_opensta")
2121
load("//synthesis:build_defs.bzl", "synthesize_rtl")
2222

23-
def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20):
23+
def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20, corners = ("ccs_ss", "ccs_tt", "ccs_ff")):
2424
"""Generate targets for a quick basic ASAP7 flow.
2525
2626
Args:
@@ -31,70 +31,74 @@ def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20):
3131
vt: VT type ("rvt", "lvt", "slvt").
3232
has_gds: Cells have GDS layouts.
3333
size: Size of the die in microns.
34+
corners: List of corners to generate rules for (default is `ccs_ss`, `ccs_tt`, `ccs_ff`).
3435
"""
3536
if rev not in [26, 27, 28]:
3637
fail("Invalid rev {}".format(repr(rev)))
3738
if tracks not in ["7p5t", "6t"]:
3839
fail("Invalid rev {}".format(repr(tracks)))
3940

40-
a = {
41-
"name": target,
42-
"tracks": tracks,
43-
"rev": rev,
44-
"vt": vt,
45-
}
41+
# TODO: Add the NLDM support once it works with OpenROAD.
42+
for corner in corners:
43+
a = {
44+
"name": target,
45+
"tracks": tracks,
46+
"rev": rev,
47+
"vt": vt,
48+
"corn": corner,
49+
}
4650

47-
synthesize_rtl(
48-
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
49-
standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}".format(**a),
50-
target_clock_period_pico_seconds = 10000,
51-
top_module = "counter",
52-
deps = [
53-
":{name}".format(**a),
54-
],
55-
)
56-
build_test(
57-
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
58-
targets = [
59-
":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
60-
],
61-
)
62-
63-
run_opensta(
64-
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a),
65-
synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
66-
)
67-
build_test(
68-
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a),
69-
targets = [
70-
":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
71-
],
72-
)
51+
synthesize_rtl(
52+
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
53+
standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}-{corn}".format(**a),
54+
target_clock_period_pico_seconds = 10000,
55+
top_module = "counter",
56+
deps = [
57+
":{name}".format(**a),
58+
],
59+
)
60+
build_test(
61+
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
62+
targets = [
63+
":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
64+
],
65+
)
7366

74-
place_and_route(
75-
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
76-
core_padding_microns = 1,
77-
die_height_microns = size,
78-
die_width_microns = size,
79-
placement_density = "0.65",
80-
sdc = "constraint.sdc",
81-
synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
82-
)
83-
build_test(
84-
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
85-
targets = [
86-
":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
87-
],
88-
)
67+
run_opensta(
68+
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a),
69+
synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
70+
)
71+
build_test(
72+
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a),
73+
targets = [
74+
":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
75+
],
76+
)
8977

90-
if has_gds:
91-
gds_write(
92-
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a),
93-
implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
78+
place_and_route(
79+
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
80+
core_padding_microns = 1,
81+
die_height_microns = size,
82+
die_width_microns = size,
83+
placement_density = "0.65",
84+
sdc = "constraint.sdc",
85+
synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
9486
)
9587
build_test(
96-
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a),
88+
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
9789
targets = [
98-
":{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a),
90+
":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
9991
],
10092
)
93+
94+
if has_gds:
95+
gds_write(
96+
name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a),
97+
implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
98+
)
99+
build_test(
100+
name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a),
101+
targets = [
102+
":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a),
103+
],
104+
)

‎synthesis/tests/BUILD

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ asap7_targets(
148148
asap7_targets(
149149
name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x",
150150
size = 2000,
151+
corners = ["ccs_ss"],
151152
has_gds = False, # No GDS for the 4x cells
152153
rev = 27,
153154
target = "verilog_counter",

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