Error in exporting the IP while building the hls model

[sandeep1404]

Hello everyone,
I tried to run the part1_getting_started notebook file from hls4ml_tutorial, the model is getting synthesized, but when I try to export the Ip to build block diagram and generate bitstream file it is giving me error as mentioned below:

***** EXPORT IP *****
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/sandeep/vivado/Vivado/2019.1/data/ip'.
WARNING: [IP_Flow 19-4832] The IP name 'myproject_axi_ap_fpext_1_no_dsp_32' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'myproject_axi_ap_fpext_1_no_dsp_32'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'myproject_axi_ap_fpext_1_no_dsp_32'...
bad lexical cast: source type value could not be interpreted as target
    while executing
"rdi::set_property core_revision 2303251142 {component component_1}"
    invoked from within
"set_property core_revision $Revision $core"
    (file "run_ippack.tcl" line 838)
INFO: [Common 17-206] Exiting Vivado at Sat Mar 25 11:42:38 2023...
ERROR: [IMPL 213-28] Failed to generate IP.
command 'ap_source' returned error code
    while executing
"source build_prj.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [HLS 200-112] Total elapsed time: 461.85 seconds; peak allocated memory: 1.416 GB.
INFO: [Common 17-206] Exiting vivado_hls at Sat Mar 25 11:42:39 2023...
Vivado synthesis report not found.
Cosim report not found.
Timing report not found.
Vivado synthesis report not found.
Cosim report not found.
Timing report not found. 

my model summary is :

Model: "sequential"
_________________________________________________________________
 Layer (type)                Output Shape              Param #   
=================================================================
 fc1 (Dense)                 (None, 64)                1088      
                                                                 
 relu1 (Activation)          (None, 64)                0         
                                                                 
 fc2 (Dense)                 (None, 32)                2080      
                                                                 
 relu2 (Activation)          (None, 32)                0         
                                                                 
 fc3 (Dense)                 (None, 32)                1056      
                                                                 
 relu3 (Activation)          (None, 32)                0         
                                                                 
 output (Dense)              (None, 5)                 165       
                                                                 
 softmax (Activation)        (None, 5)                 0         
                                                                 
=================================================================
Total params: 4,389
Trainable params: 4,389
Non-trainable params: 0
_________________________________________________________________

hls_model = hls4ml.converters.convert_from_keras_model(model,
                                                       hls_config=config,
                                                       output_dir='model_1/hls4ml_prj_lhc',
                                                       backend='VivadoAccelerator',
                                                        board='pynq-z2')

I used VivadoAccelerator as the backend
can anyone please tell me whats the issue is, I saw few solutions mentioned in xilinx website [https://support.xilinx.com/s/article/76960?language=en_US] but they are not working. can anyone help me in solving this issue.

[Stefanvanaardt]

Hi, a bit late, but the date issue was the problem for me on older Vivado installations, solved with the patch: https://support.xilinx.com/s/article/76960?language=en_US