Synthesizable limit for # of parameters (ZCU104)

[wilfredkisku]

What could be an upper bound to the number of parameters that a model can have to be synthesizable using hls4ml? Apart from quantizing and model reduction is there any way we can port complex models with high parameter values into the FPGA fabric? Is there a way to model architectures for FPGA using hls4ml that can achieve good accuracy on the ImageNet dataset with low-precision models and with fewer parameters?

[jmduarte]

This is an interesting research question. In general, it's hard to answer precisely because there are different tradeoffs, especially between model size/accuracy and target latency / II. You can fit a larger, more accurate model at the cost of longer latency/II (effectively by reusing resources).

We could probably come up with some good heuristics by running some scans, but I'm not aware of a comprehensive study.