Merge pull request #3775 from tymcauley/fix-warnings

Author: jerryz123

dependencies/diplomacy

@@ -78,7 +78,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
         // We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it)
         // !!! think about this more -- what if illegal?
-        val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
+        val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).view.mapValues(_.flatMap(_._2)).toMap
         val reductionMask = AddressDecoder(sizes1.values.toList)
         val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address
           (AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), v.U)

src/main/scala/amba/axi4/Fragmenter.scala

@@ -54,7 +54,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
       val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil
       mp.copy(
         echoFields = field ++ mp.echoFields,
-        masters    = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) })
+        masters    = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) }.toIndexedSeq)
     },
     slaveFn = { sp => sp
     })

src/main/scala/amba/axi4/IdIndexer.scala

@@ -1703,7 +1703,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
           flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
         }),
       ROMBASE       -> RegFieldGroup("debug_rom", Some("Debug ROM"),
-        (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
+        (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).toIndexedSeq.zipWithIndex.map{case (x, i) =>
           RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
     )
 

src/main/scala/devices/debug/Debug.scala

@@ -99,7 +99,7 @@ object BootROM {
     }
 
     val bootrom = bootROMDomainWrapper {
-      LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
+      LazyModule(new TLROM(params.address, params.size, contents.toIndexedSeq, true, tlbus.beatBytes))
     }
 
     bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }

src/main/scala/devices/tilelink/BootROM.scala

@@ -4,7 +4,10 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
+import org.chipsalliance.diplomacy.nodes.NodeHandle
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
 import freechips.rocketchip.tilelink._
 
 abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096)

src/main/scala/devices/tilelink/BusBypass.scala

@@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.resources.{SimpleDevice}
 
 /** Adds a /dev/null slave that does not raise ready for any incoming traffic.

src/main/scala/devices/tilelink/Deadlock.scala

@@ -12,8 +12,9 @@ object AddressDecoder
   type Partitions = Seq[Partition]
 
   val addressOrder = Ordering.ordered[AddressSet]
-  val portOrder = Ordering.Iterable(addressOrder)
-  val partitionOrder = Ordering.Iterable(portOrder)
+  import Ordering.Implicits._
+  val portOrder = Ordering[Seq[AddressSet]]
+  val partitionOrder = Ordering[Seq[Seq[AddressSet]]]
 
   // Find the minimum subset of bits needed to disambiguate port addresses.
   // ie: inspecting only the bits in the output, you can look at an address
@@ -126,7 +127,7 @@ object AddressDecoder
           println("  For bit %x, %s".format(bit, score.toString))
         (score, bit, result)
       }
-      val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Iterable[Int]](_._1.toIterable))
+      val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Seq[Int]](_._1))
       if (debug) println("=> Selected bit 0x%x".format(bestBit))
       bestBit +: recurse(bestPartitions, bits.filter(_ != bestBit))
     }

src/main/scala/diplomacy/AddressDecoder.scala

@@ -5,7 +5,7 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Elaborate, Convert}
 import firrtl.AnnotationSeq
 import firrtl.options.TargetDirAnnotation
-import freechips.rocketchip.diplomacy.LazyModule
+import org.chipsalliance.diplomacy.lazymodule.LazyModule
 import org.chipsalliance.cde.config.{Config, Parameters}
 import mainargs._
 
@@ -22,7 +22,7 @@ object Main {
         .getConstructor(classOf[Parameters])
         .newInstance(new Config(config.foldRight(Parameters.empty) {
           case (currentName, config) =>
-            val currentConfig = Class.forName(currentName).newInstance.asInstanceOf[Config]
+            val currentConfig = Class.forName(currentName).getDeclaredConstructor().newInstance().asInstanceOf[Config]
             currentConfig ++ config
         })) match {
           case m: RawModule => m
@@ -51,6 +51,6 @@ object Main {
     freechips.rocketchip.util.ElaborationArtefacts.files.foreach{ case (ext, contents) => os.write.over(os.Path(dir) / s"${config.mkString("_")}.${ext}", contents()) }
   }
 
-  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
+  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args.toIndexedSeq)
 }
 

src/main/scala/diplomacy/Main.scala

@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.diplomacy
 
+import scala.language.implicitConversions
+
 import chisel3._
 import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
 import freechips.rocketchip.util.ShiftQueue
@@ -30,8 +32,8 @@ case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
   require (start <= end, "Id ranges cannot be negative.")
 
   def compare(x: IdRange) = {
-    val primary   = (this.start - x.start).signum
-    val secondary = (x.end - this.end).signum
+    val primary   = (this.start - x.start).sign
+    val secondary = (x.end - this.end).sign
     if (primary != 0) primary else secondary
   }
 
@@ -119,7 +121,7 @@ object TransferSizes {
   def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
   def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
 
-  implicit def asBool(x: TransferSizes) = !x.none
+  implicit def asBool(x: TransferSizes): Boolean = !x.none
 }
 
 // AddressSets specify the address space managed by the manager