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Merge pull request #4068 from alainmarcel/alainmarcel-patch-1
gen_loop var
2 parents 65d5fdd + d73aeb0 commit 06cfd11

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‎include/Surelog/DesignCompile/CompileHelper.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,8 @@ class CompileHelper final {
274274
UHDM::any* compileVariable(DesignComponent* component, const FileContent* fC,
275275
NodeId nodeId, CompileDesign* compileDesign,
276276
Reduce reduce, UHDM::any* pstmt,
277-
ValuedComponentI* instance, bool muteErrors);
277+
ValuedComponentI* instance, bool muteErrors,
278+
bool implicitInt = false);
278279

279280
UHDM::typespec* compileTypespec(DesignComponent* component,
280281
const FileContent* fC, NodeId nodeId,

‎src/DesignCompile/CompileGenStmt.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ UHDM::VectorOfgen_stmt* CompileHelper::compileGenStmt(
299299
fC->populateCoreMembers(varInit, varInit, assign_stmt);
300300
if (variables* varb = (variables*)compileVariable(
301301
component, fC, Var, compileDesign, Reduce::No, assign_stmt, nullptr,
302-
false)) {
302+
/*Mute errors*/ false, /*Implicit int*/ true)) {
303303
assign_stmt->Lhs(varb);
304304
varb->VpiParent(assign_stmt);
305305
varb->VpiName(fC->SymName(Var));

‎src/DesignCompile/CompileType.cpp‎

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -250,7 +250,7 @@ variables* CompileHelper::getSimpleVarFromTypespec(
250250
UHDM::any* CompileHelper::compileVariable(
251251
DesignComponent* component, const FileContent* fC, NodeId declarationId,
252252
CompileDesign* compileDesign, Reduce reduce, UHDM::any* pstmt,
253-
SURELOG::ValuedComponentI* instance, bool muteErrors) {
253+
SURELOG::ValuedComponentI* instance, bool muteErrors, bool implicitInt) {
254254
UHDM::Serializer& s = compileDesign->getSerializer();
255255
Design* design = compileDesign->getCompiler()->getDesign();
256256
UHDM::any* result = nullptr;
@@ -318,8 +318,15 @@ UHDM::any* CompileHelper::compileVariable(
318318
VObjectType decl_type = fC->Type(declarationId);
319319
if (decl_type != VObjectType::paPs_or_hierarchical_identifier &&
320320
decl_type != VObjectType::paImplicit_class_handle) {
321-
ts = compileTypespec(component, fC, declarationId, compileDesign, reduce,
322-
pstmt, instance, true);
321+
if (implicitInt) {
322+
ts = buildIntTypespec(compileDesign, fC->getFileId(), "", "",
323+
fC->Line(declarationId), fC->Column(declarationId),
324+
fC->EndLine(declarationId),
325+
fC->EndColumn(declarationId));
326+
} else {
327+
ts = compileTypespec(component, fC, declarationId, compileDesign, reduce,
328+
pstmt, instance, true);
329+
}
323330
}
324331
bool isSigned = true;
325332
const NodeId signId = fC->Sibling(variable);
@@ -402,6 +409,14 @@ UHDM::any* CompileHelper::compileVariable(
402409
var->Typespec(tsRef);
403410
}
404411
result = var;
412+
} else if (implicitInt) {
413+
int_var* var = s.MakeInt_var();
414+
ref_typespec* tsRef = s.MakeRef_typespec();
415+
tsRef->VpiParent(var);
416+
tsRef->Actual_typespec(ts);
417+
var->Typespec(tsRef);
418+
var->VpiSigned(isSigned);
419+
result = var;
405420
} else {
406421
ref_var* ref = s.MakeRef_var();
407422
if (ts) {

‎src/DesignCompile/UhdmWriter.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3482,6 +3482,22 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
34823482
}
34833483
}
34843484
}
3485+
} else if (parent->UhdmType() == uhdmgen_for) {
3486+
gen_for* for_stmt = (gen_for*)parent;
3487+
if (VectorOfany* inits = for_stmt->VpiForInitStmts()) {
3488+
for (auto init : *inits) {
3489+
if (init->UhdmType() == uhdmassignment) {
3490+
assignment* as = (assignment*)init;
3491+
const expr* lhs = as->Lhs();
3492+
if (lhs && lhs->VpiName() == name) {
3493+
if (lhs->UhdmType() == uhdmref_var) continue;
3494+
if (lhs->UhdmType() == uhdmref_obj) continue;
3495+
ref->Actual_group((expr*)lhs);
3496+
break;
3497+
}
3498+
}
3499+
}
3500+
}
34853501
} else if (parent->UhdmType() == uhdmbegin) {
34863502
begin* b = (begin*)parent;
34873503
if (auto vars = b->Variables()) {

‎tests/ArianeElab/ArianeElab.log‎

Lines changed: 15 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -20196,10 +20196,10 @@ if_else 14
2019620196
if_stmt 18
2019720197
immediate_assert 14
2019820198
import_typespec 3
20199-
int_typespec 1309
20200-
int_var 72
20199+
int_typespec 1308
20200+
int_var 71
2020120201
io_decl 224
20202-
logic_net 14
20202+
logic_net 13
2020320203
logic_typespec 1506
2020420204
logic_var 116
2020520205
long_int_typespec 4
@@ -20215,8 +20215,7 @@ port 42
2021520215
range 1670
2021620216
ref_module 6
2021720217
ref_obj 1740
20218-
ref_typespec 5534
20219-
ref_var 1
20218+
ref_typespec 5532
2022020219
return_stmt 212
2022120220
string_typespec 836
2022220221
string_var 8
@@ -20227,7 +20226,7 @@ tagged_pattern 828
2022720226
type_parameter 2
2022820227
typespec_member 954
2022920228
union_typespec 4
20230-
unsupported_typespec 27
20229+
unsupported_typespec 26
2023120230
var_select 48
2023220231
=== UHDM Object Stats End ===
2023320232
[INF:UH0707] Elaborating UHDM...
@@ -20259,10 +20258,10 @@ if_else 48
2025920258
if_stmt 36
2026020259
immediate_assert 63
2026120260
import_typespec 3
20262-
int_typespec 1309
20263-
int_var 145
20261+
int_typespec 1308
20262+
int_var 144
2026420263
io_decl 573
20265-
logic_net 14
20264+
logic_net 13
2026620265
logic_typespec 1506
2026720266
logic_var 224
2026820267
long_int_typespec 4
@@ -20278,8 +20277,7 @@ port 84
2027820277
range 1670
2027920278
ref_module 6
2028020279
ref_obj 3945
20281-
ref_typespec 6487
20282-
ref_var 1
20280+
ref_typespec 6485
2028320281
return_stmt 684
2028420282
string_typespec 836
2028520283
string_var 22
@@ -20290,7 +20288,7 @@ tagged_pattern 828
2029020288
type_parameter 2
2029120289
typespec_member 954
2029220290
union_typespec 4
20293-
unsupported_typespec 27
20291+
unsupported_typespec 26
2029420292
var_select 216
2029520293
=== UHDM Object Stats End ===
2029620294
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/ArianeElab/slpp_all/surelog.uhdm ...
@@ -94013,13 +94011,6 @@ design: (work@top)
9401394011
|vpiLhs:
9401494012
\_parameter: (work@fpnew_top.NUM_FORMATS), line:1969:27, endln:1969:38
9401594013
|vpiDefName:work@fpnew_top
94016-
|vpiNet:
94017-
\_logic_net: (work@fpnew_top.fmt), line:1971:24, endln:1971:27
94018-
|vpiParent:
94019-
\_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:1958:1, endln:1987:10
94020-
|vpiName:fmt
94021-
|vpiFullName:work@fpnew_top.fmt
94022-
|vpiNetType:1
9402394014
|vpiGenStmt:
9402494015
\_gen_for:
9402594016
|vpiParent:
@@ -94044,9 +94035,10 @@ design: (work@top)
9404494035
\_int_var: (work@fpnew_top.fmt), line:1971:15, endln:1971:18
9404594036
|vpiFullName:work@fpnew_top.fmt
9404694037
|vpiActual:
94047-
\_int_typespec:
94038+
\_int_typespec: , line:1971:15, endln:1971:18
9404894039
|vpiName:fmt
9404994040
|vpiFullName:work@fpnew_top.fmt
94041+
|vpiSigned:1
9405094042
|vpiCondition:
9405194043
\_operation: , line:1971:24, endln:1971:47
9405294044
|vpiParent:
@@ -94059,7 +94051,7 @@ design: (work@top)
9405994051
|vpiName:fmt
9406094052
|vpiFullName:work@fpnew_top.fmt
9406194053
|vpiActual:
94062-
\_logic_net: (work@fpnew_top.fmt), line:1971:24, endln:1971:27
94054+
\_int_var: (work@fpnew_top.fmt), line:1971:15, endln:1971:18
9406394055
|vpiOperand:
9406494056
\_operation: , line:1971:30, endln:1971:47
9406594057
|vpiParent:
@@ -94090,7 +94082,7 @@ design: (work@top)
9409094082
|vpiName:fmt
9409194083
|vpiFullName:work@fpnew_top.fmt
9409294084
|vpiActual:
94093-
\_logic_net: (work@fpnew_top.fmt), line:1971:24, endln:1971:27
94085+
\_int_var: (work@fpnew_top.fmt), line:1971:15, endln:1971:18
9409494086
|vpiStmt:
9409594087
\_named_begin: (work@fpnew_top.gen_nanbox_check)
9409694088
|vpiParent:
@@ -164649,6 +164641,7 @@ design: (work@top)
164649164641
\_int_typespec: , line:1969:14, endln:1969:26
164650164642
|vpiParent:
164651164643
\_parameter: (work@fpnew_top.NUM_FORMATS), line:1969:27, endln:1969:38
164644+
\_int_typespec: , line:1971:15, endln:1971:18
164652164645
\_int_typespec: , line:1971:30, endln:1971:33
164653164646
|vpiSigned:1
164654164647
\_int_typespec: , line:1972:16, endln:1972:28
@@ -183184,7 +183177,6 @@ design: (work@top)
183184183177
\_int_typespec:
183185183178
\_int_typespec:
183186183179
\_int_typespec:
183187-
\_int_typespec:
183188183180
\_function: (ariane_pkg::range_check), line:745:5, endln:748:30
183189183181
|vpiParent:
183190183182
\_module_inst: work@fpu_wrap ([email protected]_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2035:13, endln:2050:15

‎tests/ArianeElab2/ArianeElab2.log‎

Lines changed: 20 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -20806,10 +20806,10 @@ if_else 14
2080620806
if_stmt 18
2080720807
immediate_assert 14
2080820808
import_typespec 3
20809-
int_typespec 1418
20810-
int_var 80
20809+
int_typespec 1410
20810+
int_var 72
2081120811
io_decl 224
20812-
logic_net 15
20812+
logic_net 13
2081320813
logic_typespec 75763
2081420814
logic_var 599
2081520815
long_int_typespec 4
@@ -20825,8 +20825,7 @@ port 42
2082520825
range 137586
2082620826
ref_module 12
2082720827
ref_obj 1781
20828-
ref_typespec 197816
20829-
ref_var 2
20828+
ref_typespec 197806
2083020829
return_stmt 212
2083120830
string_typespec 43804
2083220831
string_var 8
@@ -20837,7 +20836,7 @@ tagged_pattern 43796
2083720836
type_parameter 7
2083820837
typespec_member 19530
2083920838
union_typespec 4
20840-
unsupported_typespec 28
20839+
unsupported_typespec 26
2084120840
=== UHDM Object Stats End ===
2084220841
[INF:UH0707] Elaborating UHDM...
2084320842
=== UHDM Object Stats Begin (Elaborated Model) ===
@@ -20867,10 +20866,10 @@ if_else 48
2086720866
if_stmt 36
2086820867
immediate_assert 63
2086920868
import_typespec 3
20870-
int_typespec 1418
20871-
int_var 153
20869+
int_typespec 1410
20870+
int_var 145
2087220871
io_decl 573
20873-
logic_net 15
20872+
logic_net 13
2087420873
logic_typespec 75763
2087520874
logic_var 707
2087620875
long_int_typespec 4
@@ -20886,8 +20885,7 @@ port 84
2088620885
range 137586
2088720886
ref_module 12
2088820887
ref_obj 4215
20889-
ref_typespec 202042
20890-
ref_var 2
20888+
ref_typespec 202032
2089120889
return_stmt 684
2089220890
string_typespec 43804
2089320891
string_var 22
@@ -20898,7 +20896,7 @@ tagged_pattern 43796
2089820896
type_parameter 7
2089920897
typespec_member 19530
2090020898
union_typespec 4
20901-
unsupported_typespec 28
20899+
unsupported_typespec 26
2090220900
=== UHDM Object Stats End ===
2090320901
[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/ArianeElab2/slpp_all/surelog.uhdm ...
2090420902
[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/ArianeElab2/slpp_all/checker/surelog.chk.html ...
@@ -94597,13 +94595,6 @@ design: (work@top)
9459794595
|vpiLhs:
9459894596
\_parameter: (work@fpnew_opgroup_block.NUM_OPERANDS), line:1971:27, endln:1971:39
9459994597
|vpiDefName:work@fpnew_opgroup_block
94600-
|vpiNet:
94601-
\_logic_net: (work@fpnew_opgroup_block.fmt), line:1974:23, endln:1974:26
94602-
|vpiParent:
94603-
\_module_inst: work@fpnew_opgroup_block (work@fpnew_opgroup_block), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:1958:1, endln:2002:10
94604-
|vpiName:fmt
94605-
|vpiFullName:work@fpnew_opgroup_block.fmt
94606-
|vpiNetType:1
9460794598
|vpiGenStmt:
9460894599
\_gen_for:
9460994600
|vpiParent:
@@ -94628,9 +94619,10 @@ design: (work@top)
9462894619
\_int_var: (work@fpnew_opgroup_block.fmt), line:1974:14, endln:1974:17
9462994620
|vpiFullName:work@fpnew_opgroup_block.fmt
9463094621
|vpiActual:
94631-
\_int_typespec:
94622+
\_int_typespec: , line:1974:14, endln:1974:17
9463294623
|vpiName:fmt
9463394624
|vpiFullName:work@fpnew_opgroup_block.fmt
94625+
|vpiSigned:1
9463494626
|vpiCondition:
9463594627
\_operation: , line:1974:23, endln:1974:46
9463694628
|vpiParent:
@@ -94643,7 +94635,7 @@ design: (work@top)
9464394635
|vpiName:fmt
9464494636
|vpiFullName:work@fpnew_opgroup_block.fmt
9464594637
|vpiActual:
94646-
\_logic_net: (work@fpnew_opgroup_block.fmt), line:1974:23, endln:1974:26
94638+
\_int_var: (work@fpnew_opgroup_block.fmt), line:1974:14, endln:1974:17
9464794639
|vpiOperand:
9464894640
\_operation: , line:1974:29, endln:1974:46
9464994641
|vpiParent:
@@ -94674,7 +94666,7 @@ design: (work@top)
9467494666
|vpiName:fmt
9467594667
|vpiFullName:work@fpnew_opgroup_block.fmt
9467694668
|vpiActual:
94677-
\_logic_net: (work@fpnew_opgroup_block.fmt), line:1974:23, endln:1974:26
94669+
\_int_var: (work@fpnew_opgroup_block.fmt), line:1974:14, endln:1974:17
9467894670
|vpiStmt:
9467994671
\_named_begin: (work@fpnew_opgroup_block.gen_parallel_slices)
9468094672
|vpiParent:
@@ -95458,13 +95450,6 @@ design: (work@top)
9545895450
|vpiLhs:
9545995451
\_parameter: (work@fpnew_top.NUM_FORMATS), line:2017:27, endln:2017:38
9546095452
|vpiDefName:work@fpnew_top
95461-
|vpiNet:
95462-
\_logic_net: (work@fpnew_top.opgrp), line:2019:27, endln:2019:32
95463-
|vpiParent:
95464-
\_module_inst: work@fpnew_top (work@fpnew_top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2006:1, endln:2039:10
95465-
|vpiName:opgrp
95466-
|vpiFullName:work@fpnew_top.opgrp
95467-
|vpiNetType:1
9546895453
|vpiGenStmt:
9546995454
\_gen_for:
9547095455
|vpiParent:
@@ -95489,9 +95474,10 @@ design: (work@top)
9548995474
\_int_var: (work@fpnew_top.opgrp), line:2019:16, endln:2019:21
9549095475
|vpiFullName:work@fpnew_top.opgrp
9549195476
|vpiActual:
95492-
\_int_typespec:
95477+
\_int_typespec: , line:2019:16, endln:2019:21
9549395478
|vpiName:opgrp
9549495479
|vpiFullName:work@fpnew_top.opgrp
95480+
|vpiSigned:1
9549595481
|vpiCondition:
9549695482
\_operation: , line:2019:27, endln:2019:53
9549795483
|vpiParent:
@@ -95504,7 +95490,7 @@ design: (work@top)
9550495490
|vpiName:opgrp
9550595491
|vpiFullName:work@fpnew_top.opgrp
9550695492
|vpiActual:
95507-
\_logic_net: (work@fpnew_top.opgrp), line:2019:27, endln:2019:32
95493+
\_int_var: (work@fpnew_top.opgrp), line:2019:16, endln:2019:21
9550895494
|vpiOperand:
9550995495
\_operation: , line:2019:35, endln:2019:53
9551095496
|vpiParent:
@@ -95535,7 +95521,7 @@ design: (work@top)
9553595521
|vpiName:opgrp
9553695522
|vpiFullName:work@fpnew_top.opgrp
9553795523
|vpiActual:
95538-
\_logic_net: (work@fpnew_top.opgrp), line:2019:27, endln:2019:32
95524+
\_int_var: (work@fpnew_top.opgrp), line:2019:16, endln:2019:21
9553995525
|vpiStmt:
9554095526
\_named_begin: (work@fpnew_top.gen_operation_groups)
9554195527
|vpiParent:
@@ -172639,6 +172625,7 @@ design: (work@top)
172639172625
\_int_typespec: , line:1971:14, endln:1971:26
172640172626
|vpiParent:
172641172627
\_parameter: (work@fpnew_opgroup_block.NUM_OPERANDS), line:1971:27, endln:1971:39
172628+
\_int_typespec: , line:1974:14, endln:1974:17
172642172629
\_int_typespec: , line:1974:29, endln:1974:32
172643172630
|vpiSigned:1
172644172631
\_logic_typespec: , line:1976:16, endln:1976:21
@@ -172711,6 +172698,7 @@ design: (work@top)
172711172698
\_int_typespec: , line:2017:14, endln:2017:26
172712172699
|vpiParent:
172713172700
\_parameter: (work@fpnew_top.NUM_FORMATS), line:2017:27, endln:2017:38
172701+
\_int_typespec: , line:2019:16, endln:2019:21
172714172702
\_int_typespec: , line:2019:35, endln:2019:38
172715172703
|vpiSigned:1
172716172704
\_int_typespec: , line:2020:16, endln:2020:28
@@ -196173,8 +196161,6 @@ design: (work@top)
196173196161
|vpiActual:
196174196162
\_int_typespec: , line:1979:5, endln:1979:40
196175196163
\_int_typespec:
196176-
\_int_typespec:
196177-
\_int_typespec:
196178196164
\_function: (ariane_pkg::range_check), line:745:5, endln:748:30
196179196165
|vpiParent:
196180196166
\_module_inst: work@fpu_wrap ([email protected]_ariane.ex_stage_i.fpu_gen.fpu_i), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2091:13, endln:2106:15

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