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Identation & Error Removal Commit 2
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8 files changed

+474
-467
lines changed

8 files changed

+474
-467
lines changed

‎src/Mealy000Sequence.v

Lines changed: 86 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -1,99 +1,101 @@
11
module mealy_ooo(clk,rst,inp,out);
2+
3+
input clk, rst, inp;
4+
output out;
25

3-
input clk, rst, inp;
4-
output out;
5-
6-
reg[1:0] state;
7-
reg out;
8-
9-
always @(posedge clk, posedge rst)
6+
reg[1:0] state;
7+
reg out;
108

11-
begin
12-
if(rst)
13-
begin
14-
state <= 2'b00;
15-
out <= 0;
16-
end
17-
else
18-
begin
19-
case(state)
20-
2'b00:
21-
begin
22-
if(inp)
23-
begin
24-
state <= 2'b00;
25-
out <= 0;
26-
end
27-
else
28-
begin
29-
state <= 2'b01;
30-
out <=0;
31-
end
32-
end
33-
2'b01:
34-
begin
35-
if(inp)
36-
begin
37-
state <= 2'b00;
38-
out <= 0;
39-
end
40-
else
41-
begin
42-
state <= 2'b10;
43-
out <= 0;
44-
end
45-
end
46-
2'b10:
47-
begin
48-
if(inp)
49-
begin
50-
state <= 2'b00;
51-
out <= 0;
52-
end
53-
else
54-
begin
55-
state <= 2'b10;
56-
out <= 1;
57-
end
58-
end
59-
default:
60-
begin
61-
state <= 2'b00;
62-
out <= 0;
63-
end
64-
endcase
65-
end
9+
always @(posedge clk, posedge rst)
6610

67-
end
11+
begin
12+
if(rst)
13+
begin
14+
state <= 2'b00;
15+
out <= 0;
16+
end
17+
else
18+
begin
19+
case(state)
20+
2'b00:
21+
begin
22+
if(inp)
23+
begin
24+
state <= 2'b00;
25+
out <= 0;
26+
end
27+
else
28+
begin
29+
state <= 2'b01;
30+
out <=0;
31+
end
32+
end
33+
2'b01:
34+
begin
35+
if(inp)
36+
begin
37+
state <= 2'b00;
38+
out <= 0;
39+
end
40+
else
41+
begin
42+
state <= 2'b10;
43+
out <= 0;
44+
end
45+
end
46+
2'b10:
47+
begin
48+
if(inp)
49+
begin
50+
state <= 2'b00;
51+
out <= 0;
52+
end
53+
else
54+
begin
55+
state <= 2'b10;
56+
out <= 1;
57+
end
58+
end
59+
default:
60+
begin
61+
state <= 2'b00;
62+
out <= 0;
63+
end
64+
endcase
65+
end
66+
end
6867
endmodule
6968

7069

7170

7271
module fsm_testbench;
7372

74-
reg clk, rst, inp;
75-
wire out;
76-
wire[1:0] state;
77-
reg[15:0] sequence;
78-
integer i;
73+
reg clk, rst, inp;
74+
wire out;
75+
wire[1:0] state;
76+
reg[15:0] sequence;
77+
integer i;
7978

80-
mealy_ooo dut( clk, rst, inp, out);
79+
mealy_ooo dut( clk, rst, inp, out);
8180

82-
initial
83-
begin
84-
85-
clk = 0;
86-
rst = 1;
87-
sequence = 16'b0101011101111000;
88-
#5 rst = 0;
81+
initial
82+
begin
83+
$dumpfile("vcd/Mealy000Sequence.vcd");
84+
$dumpvars(0,fsm_testbench);
85+
$monitor("State = ", state, " Input = ", inp, ", Output = ", out);
86+
87+
clk = 0;
88+
rst = 1;
89+
sequence = 16'b0101011101111000;
90+
#5 rst = 0;
8991

90-
for( i = 0; i <= 15; i = i + 1)
91-
begin
92-
inp = sequence[i];
93-
#2 clk = 1;
94-
#2 clk = 0;
95-
$display("State = ", state, " Input = ", inp, ", Output = ", out);
96-
end
92+
for( i = 0; i <= 15; i = i + 1)
93+
begin
94+
inp = sequence[i];
95+
#2 clk = 1;
96+
#2 clk = 0;
97+
98+
end
9799

98-
end
100+
end
99101
endmodule

‎src/Mealy1001Sequence.v

Lines changed: 51 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,51 +1,52 @@
11
module mealy_1001( clk, rst, inp, out);
2-
input clk, rst, inp;
3-
output out;
4-
reg[1:0] state;
5-
reg out;
6-
always @( posedge clk, posedge rst ) begin
7-
if( rst ) begin
8-
state <= 2'b00;
9-
out <= 0;
10-
end
11-
else begin
12-
case( state )
13-
2'b00: begin
2+
input clk, rst, inp;
3+
output out;
4+
reg[1:0] state;
5+
reg out;
6+
always @( posedge clk, posedge rst ) begin
7+
if( rst ) begin
8+
state <= 2'b00;
9+
out <= 0;
10+
end
11+
else
12+
begin
13+
case( state )
14+
2'b00: begin
1415
if( inp ) begin
15-
state <= 2'b01;
16-
out <= 0;
16+
state <= 2'b01;
17+
out <= 0;
1718
end
1819
else begin
1920
state <= 2'b00;
2021
out <= 0;
2122
end
22-
end
23+
end
2324

24-
2'b01: begin
25+
2'b01: begin
2526
if( inp ) begin
2627
state <= 2'b01;
2728
out <= 0;
2829
end
2930
else begin
30-
state <= 2'b10;
31-
out <= 0;
31+
state <= 2'b10;
32+
out <= 0;
3233
end
3334

34-
end
35+
end
3536

36-
2'b10: begin
37+
2'b10: begin
3738
if( inp ) begin
3839
state <= 2'b01;
3940
out <= 0;
4041
end
4142
else begin
42-
state <= 2'b11;
43-
out <= 0;
43+
state <= 2'b11;
44+
out <= 0;
4445
end
4546

46-
end
47+
end
4748

48-
2'b11: begin
49+
2'b11: begin
4950
if( inp ) begin
5051
state <= 2'b00;
5152
out <= 1;
@@ -55,45 +56,47 @@ module mealy_1001( clk, rst, inp, out);
5556
out <= 0;
5657
end
5758

58-
end
59+
end
5960

60-
default: begin
61+
default: begin
6162
state <= 2'b00;
6263
out <= 0;
63-
end
64-
endcase
65-
end
64+
end
65+
endcase
66+
end
6667
end
6768

6869
endmodule
6970

7071

7172
module fsm_testbench;
7273

73-
reg clk, rst, inp;
74-
wire out;
75-
wire [1:0]state;
76-
reg[15:0] sequence;
77-
integer i;
74+
reg clk, rst, inp;
75+
wire out;
76+
wire [1:0]state;
77+
reg[15:0] sequence;
78+
integer i;
7879

79-
mealy_1001 dut( clk, rst, inp, out);
80+
mealy_1001 dut( clk, rst, inp, out);
8081

81-
initial
82-
begin
82+
initial
83+
begin
8384

84-
clk = 0;
85-
rst = 1;
86-
sequence = 16'b0101_0111_0111_1001;
87-
#5 rst = 0;
85+
$dumpfile("vcd/Mealy1001Sequence.vcd");
86+
$dumpvars(0,fsm_testbench);
87+
$monitor("State = ", state, " Input = ", inp, ", Output = ", out);
8888

89-
for( i = 0; i <= 15; i = i + 1)
90-
begin
91-
inp = sequence[i];
92-
#2 clk = 1;
93-
#2 clk = 0;
94-
$display("State = ", state, " Input = ", inp, ", output = ", out);
89+
clk = 0;
90+
rst = 1;
91+
sequence = 16'b0101_0111_0111_1001;
92+
#5 rst = 0;
9593

96-
end
94+
for( i = 0; i <= 15; i = i + 1)
95+
begin
96+
inp = sequence[i];
97+
#2 clk = 1;
98+
#2 clk = 0;
99+
end
97100

98101
end
99102

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